OV - attention-clang-skl512 - Loop 52 - attention-clang-skl512

	Loop Id: 52	Module: attention-clang-skl512	Source: attention_v2.cpp:26-33	Coverage: 6.38%

0x4724 MOV	0x28(%RSP),%R15

0x4729 NOPL	(%RAX)

0x4730 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x4734 VDIVSS	0x1d4(%RSP),%XMM0,%XMM0

0x473d MOV	0x8(%RSP),%RAX

0x4742 LEA	(%RAX,%RDI,1),%R8D

0x4746 MOV	0x78(%RSP),%R13

0x474b VMOVSS	%XMM0,(%R13,%R8,4)

0x4752 INC	%RDI

0x4755 CMP	0x50(%RSP),%RDI

0x475a MOV	0x48(%RSP),%RAX

0x475f MOV	%R15,%RBX

0x4762 MOV	0x150(%RSP),%R15

0x476a JE	46e0

0x4770 VPXOR	%XMM0,%XMM0,%XMM0

0x4774 MOV	0x30(%RSP),%RAX

0x4779 CMP	$0x4,%EAX

0x477c JB	479b

0x477e MOV	%EDI,%R8D

0x4781 ADD	0xd8(%RSP),%R8D

0x4789 SETB	%R8B

0x478d OR	0xe0(%RSP),%R8B

0x4795 JE	4900

0x479b XOR	%R9D,%R9D

0x479e TEST	$0x3,%R12B

0x47a2 JE	4800

0x47a4 MOV	0x48(%RSP),%R13

0x47a9 MOV	%R13,%R10

0x47ac IMUL	%R9,%R10

0x47b0 ADD	%RDI,%R10

0x47b3 MOV	0xd0(%RSP),%R11

0x47bb MOV	%R9,%R8

0x47be MOV	0x20(%RSP),%RSI

0x47c3 MOV	0x28(%RSP),%R15

0x47c8 NOPL	(%RAX,%RAX,1)

  (54) 0x47d0 LEA	(%RCX,%R8,1),%EBX

  (54) 0x47d4 VMOVSS	(%RSI,%RBX,4),%XMM1

  (54) 0x47d9 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (54) 0x47dd MOV	%R10D,%EBX

  (54) 0x47e0 VMOVSS	(%R15,%RBX,4),%XMM2

  (54) 0x47e6 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (54) 0x47ea VFMADD231SD	%XMM2,%XMM1,%XMM0

  (54) 0x47ef INC	%R8

  (54) 0x47f2 ADD	%R13,%R10

  (54) 0x47f5 DEC	%R11

  (54) 0x47f8 JNE	47d0

0x47fa JMP	480d

0x4800 MOV	%R9,%R8

0x4803 MOV	0x20(%RSP),%RSI

0x4808 MOV	0x28(%RSP),%R15

0x480d MOV	0x30(%RSP),%RAX

0x4812 SUB	%RAX,%R9

0x4815 CMP	$-0x4,%R9

0x4819 MOV	0x270(%RSP),%RDX

0x4821 JA	4730

0x4827 LEA	0x3(%R8),%R9

0x482b MOV	0x48(%RSP),%RBX

0x4830 IMUL	%RBX,%R9

0x4834 ADD	%RDI,%R9

0x4837 LEA	0x2(%R8),%R10

0x483b IMUL	%RBX,%R10

0x483f ADD	%RDI,%R10

0x4842 MOV	%RBX,%R11

0x4845 IMUL	%R8,%R11

0x4849 ADD	%RDI,%R11

0x484c LEA	0x1(%R8),%R13

0x4850 IMUL	%RBX,%R13

0x4854 ADD	%RDI,%R13

0x4857 NOPW	(%RAX,%RAX,1)

  (53) 0x4860 LEA	(%RCX,%R8,1),%EBX

  (53) 0x4864 VMOVSS	(%RSI,%RBX,4),%XMM1

  (53) 0x4869 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (53) 0x486d MOV	%R11D,%EBX

  (53) 0x4870 VMOVSS	(%R15,%RBX,4),%XMM2

  (53) 0x4876 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (53) 0x487a LEA	0x1(%RCX,%R8,1),%EBX

  (53) 0x487f VMOVSS	(%RSI,%RBX,4),%XMM3

  (53) 0x4884 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (53) 0x4888 MOV	%R13D,%EBX

  (53) 0x488b VMOVSS	(%R15,%RBX,4),%XMM4

  (53) 0x4891 VCVTSS2SD	%XMM4,%XMM4,%XMM4

  (53) 0x4895 VFMADD213SD	%XMM0,%XMM1,%XMM2

  (53) 0x489a LEA	0x2(%RCX,%R8,1),%EBX

  (53) 0x489f VMOVSS	(%RSI,%RBX,4),%XMM0

  (53) 0x48a4 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (53) 0x48a8 VFMADD213SD	%XMM2,%XMM3,%XMM4

  (53) 0x48ad MOV	%R10D,%EBX

  (53) 0x48b0 VMOVSS	(%R15,%RBX,4),%XMM1

  (53) 0x48b6 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (53) 0x48ba VFMADD213SD	%XMM4,%XMM0,%XMM1

  (53) 0x48bf LEA	0x3(%RCX,%R8,1),%EBX

  (53) 0x48c4 VMOVSS	(%RSI,%RBX,4),%XMM0

  (53) 0x48c9 VCVTSS2SD	%XMM0,%XMM0,%XMM2

  (53) 0x48cd MOV	%R9D,%EBX

  (53) 0x48d0 VMOVSS	(%R15,%RBX,4),%XMM0

  (53) 0x48d6 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (53) 0x48da VFMADD213SD	%XMM1,%XMM2,%XMM0

  (53) 0x48df ADD	$0x4,%R8

  (53) 0x48e3 ADD	%RDX,%R9

  (53) 0x48e6 ADD	%RDX,%R10

  (53) 0x48e9 ADD	%RDX,%R11

  (53) 0x48ec ADD	%RDX,%R13

  (53) 0x48ef CMP	%R8,%RAX

  (53) 0x48f2 JNE	4860

0x48f8 JMP	4730

0x4900 CMP	$0x20,%EAX

0x4903 JAE	4915

0x4905 XOR	%R8D,%R8D

0x4908 MOV	0x20(%RSP),%RAX

0x490d MOV	%RBX,%R15

0x4910 JMP	49fc

0x4915 VPXOR	%XMM0,%XMM0,%XMM0

0x4919 XOR	%R8D,%R8D

0x491c VPXOR	%XMM1,%XMM1,%XMM1

0x4920 VXORPS	%XMM2,%XMM2,%XMM2

0x4924 VXORPS	%XMM3,%XMM3,%XMM3

0x4928 MOV	0x20(%RSP),%RSI

0x492d MOV	0x258(%RSP),%R10

0x4935 NOPW	%CS:(%RAX,%RAX,1)

  (55) 0x4940 LEA	(%RCX,%R8,1),%R9D

  (55) 0x4944 VCVTPS2PD	(%RSI,%R9,4),%ZMM4

  (55) 0x494b VCVTPS2PD	0x20(%RSI,%R9,4),%ZMM5

  (55) 0x4953 VCVTPS2PD	0x40(%RSI,%R9,4),%ZMM6

  (55) 0x495b VCVTPS2PD	0x60(%RSI,%R9,4),%ZMM7

  (55) 0x4963 LEA	(%RDI,%R8,1),%R9D

  (55) 0x4967 VCVTPS2PD	(%RBX,%R9,4),%ZMM8

  (55) 0x496e VFMADD231PD	%ZMM8,%ZMM4,%ZMM0

  (55) 0x4974 VCVTPS2PD	0x20(%RBX,%R9,4),%ZMM4

  (55) 0x497c VFMADD231PD	%ZMM4,%ZMM5,%ZMM1

  (55) 0x4982 VCVTPS2PD	0x40(%RBX,%R9,4),%ZMM4

  (55) 0x498a VFMADD231PD	%ZMM4,%ZMM6,%ZMM2

  (55) 0x4990 VCVTPS2PD	0x60(%RBX,%R9,4),%ZMM4

  (55) 0x4998 VFMADD231PD	%ZMM4,%ZMM7,%ZMM3

  (55) 0x499e ADD	$0x20,%R8

  (55) 0x49a2 CMP	%R8,%R10

  (55) 0x49a5 JNE	4940

0x49a7 VADDPD	%ZMM0,%ZMM1,%ZMM0

0x49ad VADDPD	%ZMM2,%ZMM3,%ZMM1

0x49b3 VADDPD	%ZMM0,%ZMM1,%ZMM0

0x49b9 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x49c0 VADDPD	%ZMM1,%ZMM0,%ZMM0

0x49c6 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x49cc VADDPD	%XMM1,%XMM0,%XMM0

0x49d0 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x49d5 VADDSD	%XMM1,%XMM0,%XMM0

0x49d9 CMP	%R10D,%EAX

0x49dc JE	4724

0x49e2 MOV	%R10,%R8

0x49e5 MOV	%R10,%R9

0x49e8 TEST	$0x1c,%R12B

0x49ec MOV	0x20(%RSP),%RAX

0x49f1 MOV	0x28(%RSP),%R15

0x49f6 JE	479e

0x49fc VMOVQ	%XMM0,%XMM0

0x4a00 MOV	0xc8(%RSP),%RSI

0x4a08 NOPL	(%RAX,%RAX,1)

  (56) 0x4a10 LEA	(%RCX,%R8,1),%R9D

  (56) 0x4a14 VCVTPS2PD	(%RAX,%R9,4),%YMM1

  (56) 0x4a1a LEA	(%RDI,%R8,1),%R9D

  (56) 0x4a1e VCVTPS2PD	(%R15,%R9,4),%YMM2

  (56) 0x4a24 VFMADD231PD	%YMM2,%YMM1,%YMM0

  (56) 0x4a29 ADD	$0x4,%R8

  (56) 0x4a2d CMP	%R8,%RSI

  (56) 0x4a30 JNE	4a10

0x4a32 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x4a38 VADDPD	%XMM1,%XMM0,%XMM0

0x4a3c VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x4a41 VADDSD	%XMM1,%XMM0,%XMM0

0x4a45 MOV	%RSI,%R9

0x4a48 CMP	%ESI,0x30(%RSP)

0x4a4c JE	4730

0x4a52 JMP	479e

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.19
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.42
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.79
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.50
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	24.56
CQA cycles if fully vectorized	17.97
Front-end cycles	25.50
P0 cycles	14.25
P1 cycles	14.25
P2 cycles	13.00
P3 cycles	13.00
P4 cycles	1.00
P5 cycles	14.25
P6 cycles	14.25
P7 cycles	1.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	101.00
Nb uops	102.00
Nb loads	26.00
Nb stores	1.00
Nb stack references	15.00
FLOP/cycle	1.53
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.57
Bytes prefetched	0.00
Bytes loaded	189.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	30.77
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	46.15
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	41.67
Vector-efficiency ratio all	21.88
Vector-efficiency ratio load	11.93
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	41.35
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	17.71

Metric	Value
CQA speedup if no scalar integer	3.19
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.42
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.79
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.50
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	24.56
CQA cycles if fully vectorized	17.97
Front-end cycles	25.50
P0 cycles	14.25
P1 cycles	14.25
P2 cycles	13.00
P3 cycles	13.00
P4 cycles	1.00
P5 cycles	14.25
P6 cycles	14.25
P7 cycles	1.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	101.00
Nb uops	102.00
Nb loads	26.00
Nb stores	1.00
Nb stack references	15.00
FLOP/cycle	1.53
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.57
Bytes prefetched	0.00
Bytes loaded	189.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	30.77
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	46.15
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	41.67
Vector-efficiency ratio all	21.88
Vector-efficiency ratio load	11.93
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	41.35
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	17.71

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.50 to 8.00 cycles (3.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 25.50 to 17.97 cycles (1.42x speedup).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
46% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 39 FP arithmetical operations:

38: addition or subtraction
1: divide

The binary loop is loading 189 bytes (23 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	101
nb uops	102
loop length	481
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.50 cycles
front end	25.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	14.25	14.25	13.00	13.00	1.00	14.25	14.25	1.00
cycles	14.25	14.25	13.00	13.00	1.00	14.25	14.25	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	25.50
Dispatch	14.25
DIV/SQRT	3.00
Overall L1	25.50

Vectorization ratios

INT

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	72%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	87%

INT+FP

all	30%
load	0%
store	0%
mul	0%
add-sub	46%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	41%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	38%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	26%

INT+FP

all	21%
load	11%
store	6%
mul	12%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.50 cycles. At this rate:

5% of peak load performance is reached (7.41 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.16 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.50 to 14.25 cycles (1.79x speedup).

ASM code

In the binary file, the address of the loop is: 4770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x28(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
VDIVSS 0x1d4(%RSP),%XMM0,%XMM0	1	1	0	0.50	0.50	0	0	0	0	11	3	scal (6.3%)
MOV 0x8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RAX,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x78(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R13,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x50(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV 0x48(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R15,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x150(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 46e0 <main+0x2140>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x30(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP $0x4,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JB 479b <main+0x21fb>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0xd8(%RSP),%R8D	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0xe0(%RSP),%R8B	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4900 <main+0x2360>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST $0x3,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4800 <main+0x2260>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x48(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xd0(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x28(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 480d <main+0x226d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x28(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x30(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x270(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JA 4730 <main+0x2190>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x3(%R8),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x48(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %RBX,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,%R11	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x1(%R8),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %RBX,%R13	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4730 <main+0x2190>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JAE 4915 <main+0x2375>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
JMP 49fc <main+0x245c>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x20(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x258(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R10D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 4724 <main+0x2184>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0x1c,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x28(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 479e <main+0x21fe>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	scal (12.5%)
MOV 0xc8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %ESI,0x30(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4730 <main+0x2190>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 479e <main+0x21fe>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.50 to 8.00 cycles (3.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
46% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 39 FP arithmetical operations:

38: addition or subtraction
1: divide

The binary loop is loading 189 bytes (23 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	101
nb uops	102
loop length	481
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.50 cycles
front end	25.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	14.25	14.25	13.00	13.00	1.00	14.25	14.25	1.00
cycles	14.25	14.25	13.00	13.00	1.00	14.25	14.25	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	25.50
Dispatch	14.25
DIV/SQRT	3.00
Overall L1	25.50

Vectorization ratios

INT

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	72%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	87%

INT+FP

all	30%
load	0%
store	0%
mul	0%
add-sub	46%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	41%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	38%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	26%

INT+FP

all	21%
load	11%
store	6%
mul	12%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.50 cycles. At this rate:

5% of peak load performance is reached (7.41 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.16 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x28(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
VDIVSS 0x1d4(%RSP),%XMM0,%XMM0	1	1	0	0.50	0.50	0	0	0	0	11	3	scal (6.3%)
MOV 0x8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RAX,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x78(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R13,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x50(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV 0x48(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R15,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x150(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 46e0 <main+0x2140>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x30(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP $0x4,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JB 479b <main+0x21fb>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0xd8(%RSP),%R8D	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0xe0(%RSP),%R8B	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4900 <main+0x2360>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST $0x3,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4800 <main+0x2260>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x48(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xd0(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x28(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 480d <main+0x226d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x28(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x30(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x270(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JA 4730 <main+0x2190>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x3(%R8),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x48(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %RBX,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,%R11	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x1(%R8),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %RBX,%R13	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4730 <main+0x2190>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JAE 4915 <main+0x2375>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
JMP 49fc <main+0x245c>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x20(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x258(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R10D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 4724 <main+0x2184>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0x1c,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x28(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 479e <main+0x21fe>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	scal (12.5%)
MOV 0xc8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %ESI,0x30(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4730 <main+0x2190>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 479e <main+0x21fe>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code