OV - attention-clang-skl512 - Loop 46 - attention-clang-skl512

	Loop Id: 46	Module: attention-clang-skl512	Source: attention_v2.cpp:43-61	Coverage: 0.45%

0x4ac0 MOV	0xa8(%RSP),%RAX

0x4ac8 VMOVSS	%XMM1,(%RAX,%R13,4)

0x4ace MOV	0x148(%RSP),%RCX

0x4ad6 INC	%RCX

0x4ad9 MOV	0xb8(%RSP),%RAX

0x4ae1 MOV	0x248(%RSP),%RSI

0x4ae9 ADD	%RAX,%RSI

0x4aec ADD	%RAX,%RDI

0x4aef MOV	0x1c8(%RSP),%RDX

0x4af7 ADD	%RAX,%RDX

0x4afa MOV	%RDX,%RAX

0x4afd MOV	%RBX,%R8

0x4b00 CMP	0x50(%RSP),%RBX

0x4b05 MOV	%RCX,%RBX

0x4b08 MOV	0x228(%RSP),%R12

0x4b10 JE	5100

0x4b16 MOV	%RAX,0x1c8(%RSP)

0x4b1e MOV	%RBX,%R9

0x4b21 AND	$-0x8,%R9

0x4b25 CMP	$0x8,%RBX

0x4b29 JAE	4b40

0x4b2b XOR	%EAX,%EAX

0x4b2d VMOVSS	0x14cf(%RIP),%XMM1

0x4b35 JMP	4c60

0x4b40 CMP	$0x40,%RBX

0x4b44 JAE	4b60

0x4b46 XOR	%EAX,%EAX

0x4b48 VMOVSS	0x14b4(%RIP),%XMM1

0x4b50 JMP	4c0a

0x4b60 MOV	%RBX,%RCX

0x4b63 AND	$-0x40,%RCX

0x4b67 MOV	$0x7ffffffffffffff8,%RAX

0x4b71 ADD	$-0x38,%RAX

0x4b75 AND	%RBX,%RAX

0x4b78 XOR	%EDX,%EDX

0x4b7a VBROADCASTSS	0x1480(%RIP),%ZMM3

0x4b84 VMOVAPS	%ZMM3,%ZMM0

0x4b8a VMOVAPS	%ZMM3,%ZMM1

0x4b90 VMOVAPS	%ZMM3,%ZMM2

0x4b96 NOPW	%CS:(%RAX,%RAX,1)

  (35) 0x4ba0 VMAXPS	-0xc0(%RSI,%RDX,4),%ZMM0,%ZMM0

  (35) 0x4ba8 VMAXPS	-0x80(%RSI,%RDX,4),%ZMM1,%ZMM1

  (35) 0x4bb0 VMAXPS	-0x40(%RSI,%RDX,4),%ZMM2,%ZMM2

  (35) 0x4bb8 VMAXPS	(%RSI,%RDX,4),%ZMM3,%ZMM3

  (35) 0x4bbf ADD	$0x40,%RDX

  (35) 0x4bc3 CMP	%RDX,%RCX

  (35) 0x4bc6 JNE	4ba0

0x4bc8 VMAXPS	%ZMM1,%ZMM0,%ZMM0

0x4bce VMAXPS	%ZMM3,%ZMM2,%ZMM1

0x4bd4 VMAXPS	%ZMM1,%ZMM0,%ZMM0

0x4bda VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x4be1 VMAXPS	%YMM1,%YMM0,%YMM0

0x4be5 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x4beb VMAXPS	%XMM1,%XMM0,%XMM0

0x4bef VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x4bf4 VMAXPS	%XMM1,%XMM0,%XMM0

0x4bf8 VMOVSHDUP	%XMM0,%XMM1

0x4bfc VMAXSS	%XMM1,%XMM0,%XMM1

0x4c00 CMP	%RAX,%RBX

0x4c03 JE	4c6d

0x4c05 TEST	$0x38,%BL

0x4c08 JE	4c60

0x4c0a MOV	%RAX,%RCX

0x4c0d MOV	%RBX,%RAX

0x4c10 MOV	$0x7ffffffffffffff8,%RDX

0x4c1a AND	%RDX,%RAX

0x4c1d VBROADCASTSS	%XMM1,%YMM0

0x4c22 NOPW	%CS:(%RAX,%RAX,1)

  (50) 0x4c30 VMAXPS	(%RDI,%RCX,4),%YMM0,%YMM0

  (50) 0x4c35 ADD	$0x8,%RCX

  (50) 0x4c39 CMP	%RCX,%R9

  (50) 0x4c3c JNE	4c30

0x4c3e VEXTRACTF128	$0x1,%YMM0,%XMM1

0x4c44 VMAXPS	%XMM1,%XMM0,%XMM0

0x4c48 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x4c4d VMAXPS	%XMM1,%XMM0,%XMM0

0x4c51 VMOVSHDUP	%XMM0,%XMM1

0x4c55 VMAXSS	%XMM1,%XMM0,%XMM1

0x4c59 JMP	4c68

  (49) 0x4c60 VMAXSS	(%RDI,%RAX,4),%XMM1,%XMM1

  (49) 0x4c65 INC	%RAX

  (49) 0x4c68 CMP	%RAX,%RBX

  (49) 0x4c6b JNE	4c60

0x4c6d CMP	$0x4,%RBX

0x4c71 MOV	%RBX,0x148(%RSP)

0x4c79 MOV	%RDI,0x8(%RSP)

0x4c7e VMOVAPS	%XMM1,0x100(%RSP)

0x4c87 MOV	%RSI,0x248(%RSP)

0x4c8f MOV	%R8,0x240(%RSP)

0x4c97 MOV	%R9,0xc0(%RSP)

0x4c9f JAE	4cb0

0x4ca1 VXORPS	%XMM2,%XMM2,%XMM2

0x4ca5 XOR	%R13D,%R13D

0x4ca8 JMP	4f30

0x4cb0 CMP	$0x20,%RBX

0x4cb4 JAE	4cd0

0x4cb6 VXORPS	%XMM2,%XMM2,%XMM2

0x4cba XOR	%R13D,%R13D

0x4cbd JMP	4e77

0x4cd0 MOV	%RBX,%RAX

0x4cd3 AND	$-0x20,%RAX

0x4cd7 MOV	%RAX,0x268(%RSP)

0x4cdf MOV	$0x7ffffffffffffff8,%RAX

0x4ce9 LEA	-0x18(%RAX),%R13

0x4ced AND	%RBX,%R13

0x4cf0 VBROADCASTSS	%XMM1,%YMM0

0x4cf5 VMOVAPS	%YMM0,0x300(%RSP)

0x4cfe VXORPS	%XMM1,%XMM1,%XMM1

0x4d02 XOR	%EBX,%EBX

0x4d04 VXORPS	%XMM2,%XMM2,%XMM2

0x4d08 VXORPS	%XMM3,%XMM3,%XMM3

0x4d0c VXORPD	%XMM4,%XMM4,%XMM4

  (36) 0x4d10 VMOVAPD	%YMM4,0x360(%RSP)

  (36) 0x4d19 VMOVAPS	%YMM3,0x280(%RSP)

  (36) 0x4d22 VMOVAPS	%YMM2,0x2a0(%RSP)

  (36) 0x4d2b VMOVAPS	%YMM1,0xe0(%RSP)

  (36) 0x4d34 VMOVUPS	(%RDI,%RBX,4),%YMM0

  (36) 0x4d39 VMOVUPS	0x20(%RDI,%RBX,4),%YMM1

  (36) 0x4d3f VMOVUPS	0x40(%RDI,%RBX,4),%YMM2

  (36) 0x4d45 VMOVUPS	0x60(%RDI,%RBX,4),%YMM3

  (36) 0x4d4b VMOVAPS	0x300(%RSP),%YMM4

  (36) 0x4d54 VSUBPS	%YMM4,%YMM0,%YMM0

  (36) 0x4d58 VSUBPS	%YMM4,%YMM1,%YMM1

  (36) 0x4d5c VMOVAPS	%YMM1,0x2c0(%RSP)

  (36) 0x4d65 VSUBPS	%YMM4,%YMM2,%YMM1

  (36) 0x4d69 VMOVAPS	%YMM1,0x2e0(%RSP)

  (36) 0x4d72 VSUBPS	%YMM4,%YMM3,%YMM1

  (36) 0x4d76 VMOVAPS	%YMM1,0x340(%RSP)

  (36) 0x4d7f CALL	10d0 <_ZGVdN8v_expf@plt>

  (36) 0x4d84 VMOVAPS	%YMM0,0x320(%RSP)

  (36) 0x4d8d VMOVAPS	0x2c0(%RSP),%YMM0

  (36) 0x4d96 CALL	10d0 <_ZGVdN8v_expf@plt>

  (36) 0x4d9b VMOVAPS	%YMM0,0x2c0(%RSP)

  (36) 0x4da4 VMOVAPS	0x2e0(%RSP),%YMM0

  (36) 0x4dad CALL	10d0 <_ZGVdN8v_expf@plt>

  (36) 0x4db2 VMOVAPS	%YMM0,0x2e0(%RSP)

  (36) 0x4dbb VMOVAPS	0x340(%RSP),%YMM0

  (36) 0x4dc4 CALL	10d0 <_ZGVdN8v_expf@plt>

  (36) 0x4dc9 VMOVAPS	0x360(%RSP),%YMM4

  (36) 0x4dd2 VMOVAPS	0x280(%RSP),%YMM3

  (36) 0x4ddb VMOVAPS	0x2a0(%RSP),%YMM2

  (36) 0x4de4 VMOVAPS	0xe0(%RSP),%YMM1

  (36) 0x4ded MOV	0x8(%RSP),%RDI

  (36) 0x4df2 VADDPS	0x320(%RSP),%YMM1,%YMM1

  (36) 0x4dfb VADDPS	0x2c0(%RSP),%YMM2,%YMM2

  (36) 0x4e04 VADDPS	0x2e0(%RSP),%YMM3,%YMM3

  (36) 0x4e0d VADDPS	%YMM4,%YMM0,%YMM4

  (36) 0x4e11 ADD	$0x20,%RBX

  (36) 0x4e15 CMP	%RBX,0x268(%RSP)

  (36) 0x4e1d JNE	4d10

0x4e23 VADDPS	%YMM1,%YMM2,%YMM0

0x4e27 VADDPS	%YMM0,%YMM3,%YMM0

0x4e2b VADDPS	%YMM0,%YMM4,%YMM0

0x4e2f VEXTRACTF128	$0x1,%YMM0,%XMM1

0x4e35 VADDPS	%XMM1,%XMM0,%XMM0

0x4e39 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x4e3e VADDPS	%XMM1,%XMM0,%XMM0

0x4e42 VMOVSHDUP	%XMM0,%XMM1

0x4e46 VADDSS	%XMM1,%XMM0,%XMM2

0x4e4a MOV	0x148(%RSP),%RBX

0x4e52 CMP	%R13,%RBX

0x4e55 JNE	4e65

0x4e57 VMOVAPS	0x100(%RSP),%XMM1

0x4e60 JMP	4f6e

0x4e65 TEST	$0x1c,%BL

0x4e68 VMOVAPS	0x100(%RSP),%XMM1

0x4e71 JE	4f30

0x4e77 MOV	%RBX,%RCX

0x4e7a MOV	%R13,%RBX

0x4e7d VXORPS	%XMM0,%XMM0,%XMM0

0x4e81 VBLENDPS	$0x1,%XMM2,%XMM0,%XMM2

0x4e87 MOV	%RCX,%RAX

0x4e8a AND	$-0x4,%RAX

0x4e8e MOV	%RAX,0x2a0(%RSP)

0x4e96 MOV	$0x7ffffffffffffff8,%RAX

0x4ea0 LEA	0x4(%RAX),%R13

0x4ea4 AND	%RCX,%R13

0x4ea7 VBROADCASTSS	%XMM1,%XMM0

0x4eac VMOVAPS	%XMM0,0x280(%RSP)

0x4eb5 NOPW	%CS:(%RAX,%RAX,1)

  (48) 0x4ec0 VMOVAPS	%XMM2,0xe0(%RSP)

  (48) 0x4ec9 VMOVUPS	(%RDI,%RBX,4),%XMM0

  (48) 0x4ece VSUBPS	0x280(%RSP),%XMM0,%XMM0

  (48) 0x4ed7 VZEROUPPER

  (48) 0x4eda CALL	1080 <_ZGVbN4v_expf@plt>

  (48) 0x4edf VMOVAPS	0xe0(%RSP),%XMM2

  (48) 0x4ee8 MOV	0x8(%RSP),%RDI

  (48) 0x4eed VADDPS	%XMM2,%XMM0,%XMM2

  (48) 0x4ef1 ADD	$0x4,%RBX

  (48) 0x4ef5 CMP	%RBX,0x2a0(%RSP)

  (48) 0x4efd JNE	4ec0

0x4eff VSHUFPD	$0x1,%XMM2,%XMM2,%XMM0

0x4f04 VADDPS	%XMM0,%XMM2,%XMM0

0x4f08 VMOVSHDUP	%XMM0,%XMM1

0x4f0c VADDSS	%XMM1,%XMM0,%XMM2

0x4f10 MOV	0x148(%RSP),%RBX

0x4f18 CMP	%R13,%RBX

0x4f1b VMOVAPS	0x100(%RSP),%XMM1

0x4f24 JE	4f6e

0x4f26 NOPW	%CS:(%RAX,%RAX,1)

  (37) 0x4f30 VMOVAPS	%XMM2,0xe0(%RSP)

  (37) 0x4f39 VMOVSS	(%RDI,%R13,4),%XMM0

  (37) 0x4f3f VSUBSS	%XMM1,%XMM0,%XMM0

  (37) 0x4f43 VZEROUPPER

  (37) 0x4f46 CALL	1130 <expf@plt>

  (37) 0x4f4b VMOVAPS	0xe0(%RSP),%XMM2

  (37) 0x4f54 VMOVAPS	0x100(%RSP),%XMM1

  (37) 0x4f5d MOV	0x8(%RSP),%RDI

  (37) 0x4f62 VADDSS	%XMM2,%XMM0,%XMM2

  (37) 0x4f66 INC	%R13

  (37) 0x4f69 CMP	%R13,%RBX

  (37) 0x4f6c JNE	4f30

0x4f6e CMP	$0x8,%RBX

0x4f72 VMOVAPS	%XMM2,0xe0(%RSP)

0x4f7b JAE	4fa0

0x4f7d MOV	%RBX,%RCX

0x4f80 XOR	%EBX,%EBX

0x4f82 MOV	0x1c8(%RSP),%R12

0x4f8a VMOVAPS	%XMM1,%XMM2

0x4f8e JMP	5040

0x4fa0 MOV	$0x7ffffffffffffff8,%RAX

0x4faa AND	%RAX,%RBX

0x4fad VBROADCASTSS	%XMM2,%YMM0

0x4fb2 VMOVAPS	%YMM0,0x2a0(%RSP)

0x4fbb VBROADCASTSS	%XMM1,%YMM0

0x4fc0 VMOVAPS	%YMM0,0x280(%RSP)

0x4fc9 XOR	%R13D,%R13D

0x4fcc MOV	0x1c8(%RSP),%R12

0x4fd4 NOPW	%CS:(%RAX,%RAX,1)

  (38) 0x4fe0 VMOVUPS	(%RDI,%R13,4),%YMM0

  (38) 0x4fe6 VSUBPS	0x280(%RSP),%YMM0,%YMM0

  (38) 0x4fef CALL	10d0 <_ZGVdN8v_expf@plt>

  (38) 0x4ff4 MOV	0x8(%RSP),%RDI

  (38) 0x4ff9 VDIVPS	0x2a0(%RSP),%YMM0,%YMM0

  (38) 0x5002 VMOVUPS	%YMM0,(%R12,%R13,4)

  (38) 0x5008 ADD	$0x8,%R13

  (38) 0x500c CMP	%R13,0xc0(%RSP)

  (38) 0x5014 JNE	4fe0

0x5016 MOV	0x148(%RSP),%RCX

0x501e CMP	%RBX,%RCX

0x5021 VMOVAPS	0x100(%RSP),%XMM2

0x502a VMOVAPS	0xe0(%RSP),%XMM1

0x5033 JE	5087

0x5035 NOPW	%CS:(%RAX,%RAX,1)

  (47) 0x5040 VMOVSS	(%RDI,%RBX,4),%XMM0

  (47) 0x5045 VSUBSS	%XMM2,%XMM0,%XMM0

  (47) 0x5049 MOV	%R12,%R13

  (47) 0x504c MOV	%RCX,%R12

  (47) 0x504f VZEROUPPER

  (47) 0x5052 CALL	1130 <expf@plt>

  (47) 0x5057 VMOVAPS	0x100(%RSP),%XMM2

  (47) 0x5060 MOV	%R12,%RCX

  (47) 0x5063 MOV	%R13,%R12

  (47) 0x5066 VMOVAPS	0xe0(%RSP),%XMM1

  (47) 0x506f MOV	0x8(%RSP),%RDI

  (47) 0x5074 VDIVSS	%XMM1,%XMM0,%XMM0

  (47) 0x5078 VMOVSS	%XMM0,(%R13,%RBX,4)

  (47) 0x507f INC	%RBX

  (47) 0x5082 CMP	%RBX,%RCX

  (47) 0x5085 JNE	5040

0x5087 MOV	0x240(%RSP),%R13

0x508f LEA	0x1(%R13),%RBX

0x5093 CMP	0x50(%RSP),%RBX

0x5098 JAE	4ac0

0x509e MOV	0x220(%RSP),%RDX

0x50a6 SUB	%R13D,%EDX

0x50a9 SAL	$0x2,%RDX

0x50ad MOV	$0x3fffffffc,%RAX

0x50b7 AND	%RAX,%RDX

0x50ba ADD	$0x4,%RDX

0x50be MOV	0x218(%RSP),%RDI

0x50c6 IMUL	%R13,%RDI

0x50ca ADD	$0x4,%RDI

0x50ce AND	%RAX,%RDI

0x50d1 ADD	0x10(%RSP),%RDI

0x50d6 XOR	%ESI,%ESI

0x50d8 VZEROUPPER

0x50db CALL	1070 <memset@plt>

0x50e0 VMOVAPS	0xe0(%RSP),%XMM1

0x50e9 MOV	0x8(%RSP),%RDI

0x50ee JMP	4ac0

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.11
CQA speedup if FP arith vectorized	2.11
CQA speedup if fully vectorized	1.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	46.00
CQA cycles if no scalar integer	21.75
CQA cycles if FP arith vectorized	21.80
CQA cycles if fully vectorized	28.33
Front-end cycles	46.00
P0 cycles	25.50
P1 cycles	25.50
P2 cycles	14.50
P3 cycles	14.17
P4 cycles	16.00
P5 cycles	25.50
P6 cycles	25.50
P7 cycles	14.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	180.00
Nb uops	184.00
Nb loads	27.00
Nb stores	15.00
Nb stack references	19.00
FLOP/cycle	0.83
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.09
Bytes prefetched	0.00
Bytes loaded	252.00
Bytes stored	212.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	43.97
Vectorization ratio load	28.57
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	46.15
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.14
Vector-efficiency ratio all	22.20
Vector-efficiency ratio load	15.18
Vector-efficiency ratio store	22.08
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.60
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.75

Metric	Value
CQA speedup if no scalar integer	2.11
CQA speedup if FP arith vectorized	2.11
CQA speedup if fully vectorized	1.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	46.00
CQA cycles if no scalar integer	21.75
CQA cycles if FP arith vectorized	21.80
CQA cycles if fully vectorized	28.33
Front-end cycles	46.00
P0 cycles	25.50
P1 cycles	25.50
P2 cycles	14.50
P3 cycles	14.17
P4 cycles	16.00
P5 cycles	25.50
P6 cycles	25.50
P7 cycles	14.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	180.00
Nb uops	184.00
Nb loads	27.00
Nb stores	15.00
Nb stack references	19.00
FLOP/cycle	0.83
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.09
Bytes prefetched	0.00
Bytes loaded	252.00
Bytes stored	212.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	43.97
Vectorization ratio load	28.57
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	46.15
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.14
Vector-efficiency ratio all	22.20
Vector-efficiency ratio load	15.18
Vector-efficiency ratio store	22.08
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.60
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:43-61
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43-44,47,52,55,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 210 paths individually, rerun with max-paths=210
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 210 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 46.00 to 21.75 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 46.00 to 28.33 cycles (1.62x speedup).

Details

43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
46% of SSE/AVX addition or subtraction instructions are used in vector version.
47% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

memset@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 3 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:52
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 7 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 4 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time). 3 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 252 bytes (63 single precision FP elements). The binary loop is storing 212 bytes (53 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	180
nb uops	184
loop length	943
used x86 registers	11
used mmx registers	0
used xmm registers	5
used ymm registers	5
used zmm registers	4
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	46.00 cycles
front end	46.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	25.50	25.50	14.50	14.17	16.00	25.50	25.50	14.33
cycles	25.50	25.50	14.50	14.17	16.00	25.50	25.50	14.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	46.00
Dispatch	25.50
Overall L1	46.00

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	79%
load	66%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

INT+FP

all	43%
load	28%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	46%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	30%
load	18%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	29%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

INT+FP

all	22%
load	15%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 46.00 cycles. At this rate:

4% of peak load performance is reached (5.48 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.61 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 46.00 to 25.50 cycles (1.80x speedup).

ASM code

In the binary file, the address of the loop is: 4b16

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xa8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%RAX,%R13,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x148(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xb8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x248(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RAX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD %RAX,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0x1c8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RAX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP 0x50(%RSP),%RBX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x228(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 5100 <main+0x2b60>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x1c8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $-0x8,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $0x8,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4b40 <main+0x25a0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS 0x14cf(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
JMP 4c60 <main+0x26c0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x40,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4b60 <main+0x25c0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS 0x14b4(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
JMP 4c0a <main+0x266a>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $-0x40,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV $0x7ffffffffffffff8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD $-0x38,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RBX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VBROADCASTSS 0x1480(%RIP),%ZMM3	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
VMOVAPS %ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVAPS %ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVAPS %ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VMAXPS %ZMM3,%ZMM2,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VMAXPS %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %RAX,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 4c6d <main+0x26cd>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x38,%BL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4c60 <main+0x26c0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x7ffffffffffffff8,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
AND %RDX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
JMP 4c68 <main+0x26c8>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x4,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,0x148(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,0x8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
VMOVAPS %XMM1,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
MOV %RSI,0x248(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %R8,0x240(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %R9,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
JAE 4cb0 <main+0x2710>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4f30 <main+0x2990>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4cd0 <main+0x2730>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4e77 <main+0x28d7>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $-0x20,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,0x268(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0x7ffffffffffffff8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
LEA -0x18(%RAX),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND %RBX,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x300(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VADDPS %YMM1,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM3,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM4,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x148(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %R13,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JNE 4e65 <main+0x28c5>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JMP 4f6e <main+0x29ce>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
TEST $0x1c,%BL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4f30 <main+0x2990>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VBLENDPS $0x1,%XMM2,%XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $-0x4,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,0x2a0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0x7ffffffffffffff8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
LEA 0x4(%RAX),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND %RCX,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x280(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VSHUFPD $0x1,%XMM2,%XMM2,%XMM0	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDPS %XMM0,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x148(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %R13,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4f6e <main+0x29ce>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x8,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS %XMM2,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
JAE 4fa0 <main+0x2a00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x1c8(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VMOVAPS %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 5040 <main+0x2aa0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV $0x7ffffffffffffff8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VBROADCASTSS %XMM2,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x2a0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x280(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1c8(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x148(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %RBX,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS 0x100(%RSP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 5087 <main+0x2ae7>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x240(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%R13),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x50(%RSP),%RBX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JAE 4ac0 <main+0x2520>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x220(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
SUB %R13D,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV $0x3fffffffc,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x4,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x218(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
IMUL %R13,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD $0x4,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD 0x10(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1070 <memset@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
MOV 0x8(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JMP 4ac0 <main+0x2520>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:43-61
Module	attention-clang-skl512

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 210 paths individually, rerun with max-paths=210
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
46% of SSE/AVX addition or subtraction instructions are used in vector version.
47% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

memset@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 3 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:52
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 252 bytes (63 single precision FP elements). The binary loop is storing 212 bytes (53 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	180
nb uops	184
loop length	943
used x86 registers	11
used mmx registers	0
used xmm registers	5
used ymm registers	5
used zmm registers	4
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	46.00 cycles
front end	46.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	25.50	25.50	14.50	14.17	16.00	25.50	25.50	14.33
cycles	25.50	25.50	14.50	14.17	16.00	25.50	25.50	14.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	46.00
Dispatch	25.50
Overall L1	46.00

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	79%
load	66%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

INT+FP

all	43%
load	28%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	46%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	30%
load	18%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	29%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

INT+FP

all	22%
load	15%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 46.00 cycles. At this rate:

4% of peak load performance is reached (5.48 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.61 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4b16

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xa8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%RAX,%R13,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x148(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xb8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x248(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RAX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD %RAX,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0x1c8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RAX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP 0x50(%RSP),%RBX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x228(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 5100 <main+0x2b60>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x1c8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $-0x8,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $0x8,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4b40 <main+0x25a0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS 0x14cf(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
JMP 4c60 <main+0x26c0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x40,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4b60 <main+0x25c0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS 0x14b4(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
JMP 4c0a <main+0x266a>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $-0x40,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV $0x7ffffffffffffff8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD $-0x38,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RBX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VBROADCASTSS 0x1480(%RIP),%ZMM3	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
VMOVAPS %ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVAPS %ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVAPS %ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VMAXPS %ZMM3,%ZMM2,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VMAXPS %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %RAX,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 4c6d <main+0x26cd>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x38,%BL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4c60 <main+0x26c0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x7ffffffffffffff8,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
AND %RDX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
JMP 4c68 <main+0x26c8>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x4,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,0x148(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,0x8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
VMOVAPS %XMM1,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
MOV %RSI,0x248(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %R8,0x240(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %R9,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
JAE 4cb0 <main+0x2710>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4f30 <main+0x2990>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4cd0 <main+0x2730>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4e77 <main+0x28d7>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $-0x20,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,0x268(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0x7ffffffffffffff8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
LEA -0x18(%RAX),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND %RBX,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x300(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VADDPS %YMM1,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM3,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM4,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x148(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %R13,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JNE 4e65 <main+0x28c5>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JMP 4f6e <main+0x29ce>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
TEST $0x1c,%BL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4f30 <main+0x2990>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VBLENDPS $0x1,%XMM2,%XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $-0x4,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,0x2a0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0x7ffffffffffffff8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
LEA 0x4(%RAX),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND %RCX,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x280(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VSHUFPD $0x1,%XMM2,%XMM2,%XMM0	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDPS %XMM0,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x148(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %R13,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4f6e <main+0x29ce>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x8,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS %XMM2,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
JAE 4fa0 <main+0x2a00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x1c8(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VMOVAPS %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 5040 <main+0x2aa0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV $0x7ffffffffffffff8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VBROADCASTSS %XMM2,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x2a0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x280(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1c8(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x148(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %RBX,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS 0x100(%RSP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 5087 <main+0x2ae7>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x240(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%R13),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x50(%RSP),%RBX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JAE 4ac0 <main+0x2520>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x220(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
SUB %R13D,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV $0x3fffffffc,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x4,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x218(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
IMUL %R13,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD $0x4,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD 0x10(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1070 <memset@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
MOV 0x8(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JMP 4ac0 <main+0x2520>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code