OV - attention-clang-skl512 - Loop 41 - attention-clang-skl512

	Loop Id: 41	Module: attention-clang-skl512	Source: attention_v2.cpp:27-33	Coverage: 0.80%

0x51a0 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x51a4 MOV	0x8(%RSP),%RAX

0x51a9 LEA	(%RAX,%RDI,1),%R8D

0x51ad MOV	0x70(%RSP),%R13

0x51b2 VMOVSS	%XMM0,(%R13,%R8,4)

0x51b9 INC	%RDI

0x51bc CMP	0x30(%RSP),%RDI

0x51c1 MOV	0x40(%RSP),%RBX

0x51c6 JE	5150

0x51c8 VXORPS	%XMM0,%XMM0,%XMM0

0x51cc MOV	0x50(%RSP),%RAX

0x51d1 CMP	$0x4,%EAX

0x51d4 JB	51f3

0x51d6 MOV	%EDI,%R8D

0x51d9 ADD	0x1e8(%RSP),%R8D

0x51e1 SETB	%R8B

0x51e5 OR	0xe0(%RSP),%R8B

0x51ed JE	5360

0x51f3 XOR	%R9D,%R9D

0x51f6 MOV	0x278(%RSP),%R11

0x51fe TEST	%R11,%R11

0x5201 JE	5270

0x5203 MOV	%R12,%R10

0x5206 IMUL	%R9,%R10

0x520a ADD	%RDI,%R10

0x520d MOV	%R9,%R8

0x5210 MOV	0x50(%RSP),%RAX

0x5215 MOV	0x10(%RSP),%RDX

0x521a NOPW	(%RAX,%RAX,1)

  (43) 0x5220 LEA	(%RCX,%R8,1),%EBX

  (43) 0x5224 VMOVSS	(%RDX,%RBX,4),%XMM1

  (43) 0x5229 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (43) 0x522d MOV	%R10D,%EBX

  (43) 0x5230 VMOVSS	(%R15,%RBX,4),%XMM2

  (43) 0x5236 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (43) 0x523a VFMADD231SD	%XMM2,%XMM1,%XMM0

  (43) 0x523f INC	%R8

  (43) 0x5242 ADD	%R12,%R10

  (43) 0x5245 DEC	%R11

  (43) 0x5248 JNE	5220

0x524a SUB	%RAX,%R9

0x524d CMP	$-0x4,%R9

0x5251 LEA	(,%R12,4),%RSI

0x5259 JA	51a0

0x525f JMP	5292

0x5270 MOV	%R9,%R8

0x5273 MOV	0x50(%RSP),%RAX

0x5278 MOV	0x10(%RSP),%RDX

0x527d SUB	%RAX,%R9

0x5280 CMP	$-0x4,%R9

0x5284 LEA	(,%R12,4),%RSI

0x528c JA	51a0

0x5292 LEA	0x3(%R8),%R9

0x5296 IMUL	%R12,%R9

0x529a ADD	%RDI,%R9

0x529d LEA	0x2(%R8),%R10

0x52a1 IMUL	%R12,%R10

0x52a5 ADD	%RDI,%R10

0x52a8 MOV	%R12,%R11

0x52ab IMUL	%R8,%R11

0x52af ADD	%RDI,%R11

0x52b2 LEA	0x1(%R8),%R13

0x52b6 IMUL	%R12,%R13

0x52ba ADD	%RDI,%R13

0x52bd NOPL	(%RAX)

  (42) 0x52c0 LEA	(%RCX,%R8,1),%EBX

  (42) 0x52c4 VMOVSS	(%RDX,%RBX,4),%XMM1

  (42) 0x52c9 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (42) 0x52cd MOV	%R11D,%EBX

  (42) 0x52d0 VMOVSS	(%R15,%RBX,4),%XMM2

  (42) 0x52d6 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (42) 0x52da LEA	0x1(%RCX,%R8,1),%EBX

  (42) 0x52df VMOVSS	(%RDX,%RBX,4),%XMM3

  (42) 0x52e4 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (42) 0x52e8 MOV	%R13D,%EBX

  (42) 0x52eb VMOVSS	(%R15,%RBX,4),%XMM4

  (42) 0x52f1 VCVTSS2SD	%XMM4,%XMM4,%XMM4

  (42) 0x52f5 VFMADD213SD	%XMM0,%XMM1,%XMM2

  (42) 0x52fa LEA	0x2(%RCX,%R8,1),%EBX

  (42) 0x52ff VMOVSS	(%RDX,%RBX,4),%XMM0

  (42) 0x5304 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (42) 0x5308 VFMADD213SD	%XMM2,%XMM3,%XMM4

  (42) 0x530d MOV	%R10D,%EBX

  (42) 0x5310 VMOVSS	(%R15,%RBX,4),%XMM1

  (42) 0x5316 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (42) 0x531a VFMADD213SD	%XMM4,%XMM0,%XMM1

  (42) 0x531f LEA	0x3(%RCX,%R8,1),%EBX

  (42) 0x5324 VMOVSS	(%RDX,%RBX,4),%XMM0

  (42) 0x5329 VCVTSS2SD	%XMM0,%XMM0,%XMM2

  (42) 0x532d MOV	%R9D,%EBX

  (42) 0x5330 VMOVSS	(%R15,%RBX,4),%XMM0

  (42) 0x5336 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (42) 0x533a VFMADD213SD	%XMM1,%XMM2,%XMM0

  (42) 0x533f ADD	$0x4,%R8

  (42) 0x5343 ADD	%RSI,%R9

  (42) 0x5346 ADD	%RSI,%R10

  (42) 0x5349 ADD	%RSI,%R11

  (42) 0x534c ADD	%RSI,%R13

  (42) 0x534f CMP	%R8,%RAX

  (42) 0x5352 JNE	52c0

0x5358 JMP	51a0

0x5360 CMP	$0x20,%EAX

0x5363 JAE	5372

0x5365 XOR	%R8D,%R8D

0x5368 MOV	0x10(%RSP),%RDX

0x536d JMP	5458

0x5372 VXORPS	%XMM0,%XMM0,%XMM0

0x5376 XOR	%R8D,%R8D

0x5379 VXORPS	%XMM1,%XMM1,%XMM1

0x537d VXORPS	%XMM2,%XMM2,%XMM2

0x5381 VXORPS	%XMM3,%XMM3,%XMM3

0x5385 MOV	0x250(%RSP),%R10

0x538d MOV	0x10(%RSP),%RDX

0x5392 NOPW	%CS:(%RAX,%RAX,1)

  (44) 0x53a0 LEA	(%RCX,%R8,1),%R9D

  (44) 0x53a4 VCVTPS2PD	(%RDX,%R9,4),%ZMM4

  (44) 0x53ab VCVTPS2PD	0x20(%RDX,%R9,4),%ZMM5

  (44) 0x53b3 VCVTPS2PD	0x40(%RDX,%R9,4),%ZMM6

  (44) 0x53bb VCVTPS2PD	0x60(%RDX,%R9,4),%ZMM7

  (44) 0x53c3 LEA	(%RDI,%R8,1),%R9D

  (44) 0x53c7 VCVTPS2PD	(%R15,%R9,4),%ZMM8

  (44) 0x53ce VFMADD231PD	%ZMM8,%ZMM4,%ZMM0

  (44) 0x53d4 VCVTPS2PD	0x20(%R15,%R9,4),%ZMM4

  (44) 0x53dc VFMADD231PD	%ZMM4,%ZMM5,%ZMM1

  (44) 0x53e2 VCVTPS2PD	0x40(%R15,%R9,4),%ZMM4

  (44) 0x53ea VFMADD231PD	%ZMM4,%ZMM6,%ZMM2

  (44) 0x53f0 VCVTPS2PD	0x60(%R15,%R9,4),%ZMM4

  (44) 0x53f8 VFMADD231PD	%ZMM4,%ZMM7,%ZMM3

  (44) 0x53fe ADD	$0x20,%R8

  (44) 0x5402 CMP	%R8,%R10

  (44) 0x5405 JNE	53a0

0x5407 VADDPD	%ZMM0,%ZMM1,%ZMM0

0x540d VADDPD	%ZMM2,%ZMM3,%ZMM1

0x5413 VADDPD	%ZMM0,%ZMM1,%ZMM0

0x5419 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x5420 VADDPD	%ZMM1,%ZMM0,%ZMM0

0x5426 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x542c VADDPD	%XMM1,%XMM0,%XMM0

0x5430 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5435 VADDSD	%XMM1,%XMM0,%XMM0

0x5439 CMP	%R10D,%EAX

0x543c JE	51a0

0x5442 MOV	%R10,%R8

0x5445 MOV	%R10,%R9

0x5448 TESTB	$0x1c,0x48(%RSP)

0x544d MOV	0x10(%RSP),%RDX

0x5452 JE	51f6

0x5458 VMOVQ	%XMM0,%XMM0

0x545c MOV	0x260(%RSP),%RAX

0x5464 NOPW	%CS:(%RAX,%RAX,1)

  (45) 0x5470 LEA	(%RCX,%R8,1),%R9D

  (45) 0x5474 VCVTPS2PD	(%RDX,%R9,4),%YMM1

  (45) 0x547a LEA	(%RDI,%R8,1),%R9D

  (45) 0x547e VCVTPS2PD	(%R15,%R9,4),%YMM2

  (45) 0x5484 VFMADD231PD	%YMM2,%YMM1,%YMM0

  (45) 0x5489 ADD	$0x4,%R8

  (45) 0x548d CMP	%R8,%RAX

  (45) 0x5490 JNE	5470

0x5492 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x5498 VADDPD	%XMM1,%XMM0,%XMM0

0x549c VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x54a1 VADDSD	%XMM1,%XMM0,%XMM0

0x54a5 MOV	%RAX,%R9

0x54a8 CMP	%EAX,0x50(%RSP)

0x54ac JE	51a0

0x54b2 JMP	51f6

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.57
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	23.18
CQA cycles if fully vectorized	16.01
Front-end cycles	24.00
P0 cycles	15.25
P1 cycles	15.25
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	1.00
P5 cycles	15.25
P6 cycles	15.25
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	95.00
Nb uops	96.00
Nb loads	19.00
Nb stores	1.00
Nb stack references	12.00
FLOP/cycle	1.58
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.58
Bytes prefetched	0.00
Bytes loaded	130.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	30.77
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	42.86
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	21.78
Vector-efficiency ratio load	11.41
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	39.29
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.06

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.57
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	23.18
CQA cycles if fully vectorized	16.01
Front-end cycles	24.00
P0 cycles	15.25
P1 cycles	15.25
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	1.00
P5 cycles	15.25
P6 cycles	15.25
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	95.00
Nb uops	96.00
Nb loads	19.00
Nb stores	1.00
Nb stack references	12.00
FLOP/cycle	1.58
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.58
Bytes prefetched	0.00
Bytes loaded	130.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	30.77
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	42.86
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	21.78
Vector-efficiency ratio load	11.41
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	39.29
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.06

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.00 to 8.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 24.00 to 16.01 cycles (1.50x speedup).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
42% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 130 bytes (16 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	95
nb uops	96
loop length	442
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.00 cycles
front end	24.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	15.25	15.25	9.50	9.50	1.00	15.25	15.25	1.00
cycles	15.25	15.25	9.50	9.50	1.00	15.25	15.25	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.00
Dispatch	15.25
Overall L1	24.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	80%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	30%
load	0%
store	0%
mul	0%
add-sub	42%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	38%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

INT+FP

all	21%
load	11%
store	6%
mul	12%
add-sub	39%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

4% of peak load performance is reached (5.42 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.17 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 15.25 cycles (1.57x speedup).

ASM code

In the binary file, the address of the loop is: 51c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
MOV 0x8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RAX,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x70(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R13,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x30(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV 0x40(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 5150 <main+0x2bb0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x50(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP $0x4,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JB 51f3 <main+0x2c53>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0x1e8(%RSP),%R8D	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0xe0(%RSP),%R8B	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 5360 <main+0x2dc0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x278(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
TEST %R11,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 5270 <main+0x2cd0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA (,%R12,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
JA 51a0 <main+0x2c00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 5292 <main+0x2cf2>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA (,%R12,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
JA 51a0 <main+0x2c00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x3(%R8),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R12,%R11	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x1(%R8),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R13	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 51a0 <main+0x2c00>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JAE 5372 <main+0x2dd2>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JMP 5458 <main+0x2eb8>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x250(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R10D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 51a0 <main+0x2c00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TESTB $0x1c,0x48(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (1.6%)
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 51f6 <main+0x2c56>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	scal (12.5%)
MOV 0x260(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %EAX,0x50(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 51a0 <main+0x2c00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 51f6 <main+0x2c56>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.00 to 8.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
42% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 130 bytes (16 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	95
nb uops	96
loop length	442
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.00 cycles
front end	24.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	15.25	15.25	9.50	9.50	1.00	15.25	15.25	1.00
cycles	15.25	15.25	9.50	9.50	1.00	15.25	15.25	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.00
Dispatch	15.25
Overall L1	24.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	80%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	30%
load	0%
store	0%
mul	0%
add-sub	42%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	38%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

INT+FP

all	21%
load	11%
store	6%
mul	12%
add-sub	39%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

4% of peak load performance is reached (5.42 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.17 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 51c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
MOV 0x8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RAX,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x70(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R13,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x30(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV 0x40(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 5150 <main+0x2bb0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x50(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP $0x4,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JB 51f3 <main+0x2c53>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0x1e8(%RSP),%R8D	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0xe0(%RSP),%R8B	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 5360 <main+0x2dc0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x278(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
TEST %R11,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 5270 <main+0x2cd0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA (,%R12,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
JA 51a0 <main+0x2c00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 5292 <main+0x2cf2>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA (,%R12,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
JA 51a0 <main+0x2c00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x3(%R8),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R12,%R11	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x1(%R8),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R13	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 51a0 <main+0x2c00>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JAE 5372 <main+0x2dd2>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JMP 5458 <main+0x2eb8>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x250(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R10D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 51a0 <main+0x2c00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TESTB $0x1c,0x48(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (1.6%)
MOV 0x10(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 51f6 <main+0x2c56>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	scal (12.5%)
MOV 0x260(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %EAX,0x50(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 51a0 <main+0x2c00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 51f6 <main+0x2c56>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code