OV - attention-clang-skl512 - Loop 38 - attention-clang-skl512

0x4fe0 VMOVUPS	(%RDI,%R13,4),%YMM0    [1]

0x4fe6 VSUBPS	0x280(%RSP),%YMM0,%YMM0    [2]

0x4fef CALL	10d0 <_ZGVdN8v_expf@plt>

0x4ff4 MOV	0x8(%RSP),%RDI    [2]

0x4ff9 VDIVPS	0x2a0(%RSP),%YMM0,%YMM0    [2]

0x5002 VMOVUPS	%YMM0,(%R12,%R13,4)    [3]

0x5008 ADD	$0x8,%R13

0x500c CMP	%R13,0xc0(%RSP)    [2]

0x5014 JNE	4fe0

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P0,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	2.25
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	2.00
DIV/SQRT cycles	5.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	5.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	3.20
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.80
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P0,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	2.25
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	2.00
DIV/SQRT cycles	5.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	5.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	3.20
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.80
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:55-56.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 2.50 cycles (2.00x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.00 to 2.25 cycles (2.22x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZGVdN8v_expf@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:56

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction
8: divide

The binary loop is loading 112 bytes (28 single precision FP elements). The binary loop is storing 32 bytes (8 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	9
nb uops	9
loop length	54
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.50	1.00	2.50	2.50	2.00	1.00	1.50	2.00
cycles	1.50	1.00	2.50	2.50	2.00	1.00	1.50	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	5.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	2.50
DIV/SQRT	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

17% of peak load performance is reached (22.40 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (6.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4fe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVUPS (%RDI,%R13,4),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VSUBPS 0x280(%RSP),%YMM0,%YMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0x8(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VDIVPS 0x2a0(%RSP),%YMM0,%YMM0	1	1	0	0.50	0.50	0	0	0	0	11	5	vect (50.0%)
VMOVUPS %YMM0,(%R12,%R13,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
ADD $0x8,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R13,0xc0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 4fe0 <main+0x2a40>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:55-56.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 2.50 cycles (2.00x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.00 to 2.25 cycles (2.22x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZGVdN8v_expf@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:56

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction
8: divide

The binary loop is loading 112 bytes (28 single precision FP elements). The binary loop is storing 32 bytes (8 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	9
nb uops	9
loop length	54
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.50	1.00	2.50	2.50	2.00	1.00	1.50	2.00
cycles	1.50	1.00	2.50	2.50	2.00	1.00	1.50	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	5.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	2.50
DIV/SQRT	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

17% of peak load performance is reached (22.40 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (6.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4fe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVUPS (%RDI,%R13,4),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VSUBPS 0x280(%RSP),%YMM0,%YMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0x8(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VDIVPS 0x2a0(%RSP),%YMM0,%YMM0	1	1	0	0.50	0.50	0	0	0	0	11	5	vect (50.0%)
VMOVUPS %YMM0,(%R12,%R13,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
ADD $0x8,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R13,0xc0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 4fe0 <main+0x2a40>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code