OV - attention-clang-skl512 - Loop 35 - attention-clang-skl512

0x4ba0 VMAXPS	-0xc0(%RSI,%RDX,4),%ZMM0,%ZMM0    [1]

0x4ba8 VMAXPS	-0x80(%RSI,%RDX,4),%ZMM1,%ZMM1    [1]

0x4bb0 VMAXPS	-0x40(%RSI,%RDX,4),%ZMM2,%ZMM2    [1]

0x4bb8 VMAXPS	(%RSI,%RDX,4),%ZMM3,%ZMM3    [1]

0x4bbf ADD	$0x40,%RDX

0x4bc3 CMP	%RDX,%RCX

0x4bc6 JNE	4ba0

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 47 - 48

--------------------------------------------------------------------------------

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks
Function	main
Source	attention_v2.cpp:47-48
Source loop unroll info	unrolled by 64
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	64
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	4.00
Front-end cycles	2.50
P0 cycles	2.00
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	1.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	6.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks
Function	main
Source	attention_v2.cpp:47-48
Source loop unroll info	unrolled by 64
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	64
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	4.00
Front-end cycles	2.50
P0 cycles	2.00
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	1.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	6.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:47-48
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:47-48.

It is main loop of related source loop which is unrolled by 64 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

4 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes (64 single precision FP elements).

General properties

nb instructions	7
nb uops	6
loop length	40
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	4
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	1.00	2.00	2.00	0.00	2.00	1.00	0.00
cycles	2.00	1.00	2.00	2.00	0.00	2.00	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	2.50
Dispatch	2.00
Data deps.	4.00
Overall L1	4.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

50% of peak load performance is reached (64.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ba0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
VMAXPS -0xc0(%RSI,%RDX,4),%ZMM0,%ZMM0	1	0.50	0	0.50	0.50	0.50	0	4	0.50	vect (100.0%)
VMAXPS -0x80(%RSI,%RDX,4),%ZMM1,%ZMM1	1	0.50	0	0.50	0.50	0.50	0	4	0.50	vect (100.0%)
VMAXPS -0x40(%RSI,%RDX,4),%ZMM2,%ZMM2	1	0.50	0	0.50	0.50	0.50	0	4	0.50	vect (100.0%)
VMAXPS (%RSI,%RDX,4),%ZMM3,%ZMM3	1	0.50	0	0.50	0.50	0.50	0	4	0.50	vect (100.0%)
ADD $0x40,%RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
CMP %RDX,%RCX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JNE 4ba0 <main+0x2600>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:47-48
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:47-48.

It is main loop of related source loop which is unrolled by 64 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

4 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes (64 single precision FP elements).

General properties

nb instructions	7
nb uops	6
loop length	40
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	4
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	1.00	2.00	2.00	0.00	2.00	1.00	0.00
cycles	2.00	1.00	2.00	2.00	0.00	2.00	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	2.50
Dispatch	2.00
Data deps.	4.00
Overall L1	4.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

50% of peak load performance is reached (64.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ba0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
VMAXPS -0xc0(%RSI,%RDX,4),%ZMM0,%ZMM0	1	0.50	0	0.50	0.50	0.50	0	4	0.50	vect (100.0%)
VMAXPS -0x80(%RSI,%RDX,4),%ZMM1,%ZMM1	1	0.50	0	0.50	0.50	0.50	0	4	0.50	vect (100.0%)
VMAXPS -0x40(%RSI,%RDX,4),%ZMM2,%ZMM2	1	0.50	0	0.50	0.50	0.50	0	4	0.50	vect (100.0%)
VMAXPS (%RSI,%RDX,4),%ZMM3,%ZMM3	1	0.50	0	0.50	0.50	0.50	0	4	0.50	vect (100.0%)
ADD $0x40,%RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
CMP %RDX,%RCX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JNE 4ba0 <main+0x2600>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code