OV - attention-clang-skl256 - Loop 78 - attention-clang-skl256

	Loop Id: 78	Module: attention-clang-skl256	Source: random.tcc:404-409	Coverage: 0.02%

0x2f40 VMOVDQA	%YMM0,%YMM1

0x2f44 VMOVDQU	0x3b8(%RSP,%RCX,8),%YMM2    [1]

0x2f4d VMOVDQU	0x3d8(%RSP,%RCX,8),%YMM3    [1]

0x2f56 VMOVDQU	0x3f8(%RSP,%RCX,8),%YMM4    [1]

0x2f5f VMOVDQU	0x418(%RSP,%RCX,8),%YMM0    [1]

0x2f68 VALIGNQ	$0x3,%YMM1,%YMM2,%YMM1

0x2f6f VALIGNQ	$0x3,%YMM2,%YMM3,%YMM5

0x2f76 VALIGNQ	$0x3,%YMM3,%YMM4,%YMM6

0x2f7d VALIGNQ	$0x3,%YMM4,%YMM0,%YMM7

0x2f84 VPAND	%YMM2,%YMM13,%YMM8

0x2f88 VPAND	%YMM3,%YMM13,%YMM9

0x2f8c VPAND	%YMM4,%YMM13,%YMM10

0x2f90 VPAND	%YMM0,%YMM13,%YMM11

0x2f94 VPTERNLOGQ	$-0x8,%YMM12,%YMM1,%YMM8

0x2f9b VPTERNLOGQ	$-0x8,%YMM12,%YMM5,%YMM9

0x2fa2 VPTERNLOGQ	$-0x8,%YMM12,%YMM6,%YMM10

0x2fa9 VPTERNLOGQ	$-0x8,%YMM12,%YMM7,%YMM11

0x2fb0 VPSRLQ	$0x1,%YMM8,%YMM1

0x2fb6 VPSRLQ	$0x1,%YMM9,%YMM5

0x2fbc VPSRLQ	$0x1,%YMM10,%YMM6

0x2fc2 VPSRLQ	$0x1,%YMM11,%YMM7

0x2fc8 VPXOR	0x1018(%RSP,%RCX,8),%YMM1,%YMM1    [1]

0x2fd1 VPXOR	0x1038(%RSP,%RCX,8),%YMM5,%YMM5    [1]

0x2fda VPXOR	0x1058(%RSP,%RCX,8),%YMM6,%YMM6    [1]

0x2fe3 VPXOR	0x1078(%RSP,%RCX,8),%YMM7,%YMM7    [1]

0x2fec VPTESTMQ	%YMM14,%YMM2,%K1

0x2ff2 VPTESTMQ	%YMM14,%YMM3,%K2

0x2ff8 VPTESTMQ	%YMM14,%YMM4,%K3

0x2ffe VPTESTMQ	%YMM14,%YMM0,%K4

0x3004 VPXORQ	%YMM15,%YMM1,%YMM1{%K1}

0x300a VPXORQ	%YMM15,%YMM5,%YMM5{%K2}

0x3010 VPXORQ	%YMM15,%YMM6,%YMM6{%K3}

0x3016 VPXORQ	%YMM15,%YMM7,%YMM7{%K4}

0x301c VMOVDQU	%YMM1,0x3b0(%RSP,%RCX,8)    [1]

0x3025 VMOVDQU	%YMM5,0x3d0(%RSP,%RCX,8)    [1]

0x302e VMOVDQU	%YMM6,0x3f0(%RSP,%RCX,8)    [1]

0x3037 VMOVDQU	%YMM7,0x410(%RSP,%RCX,8)    [1]

0x3040 ADD	$0x10,%RCX

0x3044 CMP	$0xe0,%RCX

0x304b JNE	2f40

/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 404 - 409

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.75
CQA cycles if no scalar integer	10.75
CQA cycles if FP arith vectorized	10.75
CQA cycles if fully vectorized	5.38
Front-end cycles	10.75
P0 cycles	9.33
P1 cycles	9.33
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	9.33
P6 cycles	2.00
P7 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	8.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.72
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.75
CQA cycles if no scalar integer	10.75
CQA cycles if FP arith vectorized	10.75
CQA cycles if fully vectorized	5.38
Front-end cycles	10.75
P0 cycles	9.33
P1 cycles	9.33
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	9.33
P6 cycles	2.00
P7 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	8.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.72
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-409
Module	attention-clang-skl256

The loop is defined in /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-409.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	40
nb uops	39
loop length	273
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	9.33	9.33	4.00	4.00	4.00	9.33	2.00	4.00
cycles	9.33	9.33	4.00	4.00	4.00	9.33	2.00	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.75
Dispatch	9.33
Data deps.	1.00
Overall L1	10.75

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.75 cycles. At this rate:

18% of peak load performance is reached (23.81 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (11.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.75 to 9.33 cycles (1.15x speedup).

ASM code

In the binary file, the address of the loop is: 2f40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVDQA %YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VMOVDQU 0x3b8(%RSP,%RCX,8),%YMM2	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VMOVDQU 0x3d8(%RSP,%RCX,8),%YMM3	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VMOVDQU 0x3f8(%RSP,%RCX,8),%YMM4	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VMOVDQU 0x418(%RSP,%RCX,8),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM1,%YMM2,%YMM1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VALIGNQ $0x3,%YMM2,%YMM3,%YMM5	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VALIGNQ $0x3,%YMM3,%YMM4,%YMM6	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VALIGNQ $0x3,%YMM4,%YMM0,%YMM7	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPAND %YMM2,%YMM13,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPAND %YMM3,%YMM13,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPAND %YMM4,%YMM13,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPAND %YMM0,%YMM13,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM12,%YMM1,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM12,%YMM5,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM12,%YMM6,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM12,%YMM7,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM8,%YMM1	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM9,%YMM5	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM10,%YMM6	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM11,%YMM7	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (50.0%)
VPXOR 0x1018(%RSP,%RCX,8),%YMM1,%YMM1	1	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (50.0%)
VPXOR 0x1038(%RSP,%RCX,8),%YMM5,%YMM5	1	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (50.0%)
VPXOR 0x1058(%RSP,%RCX,8),%YMM6,%YMM6	1	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (50.0%)
VPXOR 0x1078(%RSP,%RCX,8),%YMM7,%YMM7	1	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (50.0%)
VPTESTMQ %YMM14,%YMM2,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPTESTMQ %YMM14,%YMM3,%K2	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPTESTMQ %YMM14,%YMM4,%K3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPTESTMQ %YMM14,%YMM0,%K4	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPXORQ %YMM15,%YMM1,%YMM1{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXORQ %YMM15,%YMM5,%YMM5{%K2}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXORQ %YMM15,%YMM6,%YMM6{%K3}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXORQ %YMM15,%YMM7,%YMM7{%K4}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VMOVDQU %YMM1,0x3b0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
VMOVDQU %YMM5,0x3d0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
VMOVDQU %YMM6,0x3f0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
VMOVDQU %YMM7,0x410(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
ADD $0x10,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP $0xe0,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 2f40 <main+0xa60>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	random.tcc:404-409
Module	attention-clang-skl256

The loop is defined in /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-409.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	40
nb uops	39
loop length	273
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	9.33	9.33	4.00	4.00	4.00	9.33	2.00	4.00
cycles	9.33	9.33	4.00	4.00	4.00	9.33	2.00	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.75
Dispatch	9.33
Data deps.	1.00
Overall L1	10.75

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.75 cycles. At this rate:

18% of peak load performance is reached (23.81 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (11.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 2f40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVDQA %YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VMOVDQU 0x3b8(%RSP,%RCX,8),%YMM2	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VMOVDQU 0x3d8(%RSP,%RCX,8),%YMM3	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VMOVDQU 0x3f8(%RSP,%RCX,8),%YMM4	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VMOVDQU 0x418(%RSP,%RCX,8),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM1,%YMM2,%YMM1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VALIGNQ $0x3,%YMM2,%YMM3,%YMM5	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VALIGNQ $0x3,%YMM3,%YMM4,%YMM6	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VALIGNQ $0x3,%YMM4,%YMM0,%YMM7	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPAND %YMM2,%YMM13,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPAND %YMM3,%YMM13,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPAND %YMM4,%YMM13,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPAND %YMM0,%YMM13,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM12,%YMM1,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM12,%YMM5,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM12,%YMM6,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM12,%YMM7,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM8,%YMM1	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM9,%YMM5	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM10,%YMM6	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM11,%YMM7	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (50.0%)
VPXOR 0x1018(%RSP,%RCX,8),%YMM1,%YMM1	1	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (50.0%)
VPXOR 0x1038(%RSP,%RCX,8),%YMM5,%YMM5	1	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (50.0%)
VPXOR 0x1058(%RSP,%RCX,8),%YMM6,%YMM6	1	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (50.0%)
VPXOR 0x1078(%RSP,%RCX,8),%YMM7,%YMM7	1	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (50.0%)
VPTESTMQ %YMM14,%YMM2,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPTESTMQ %YMM14,%YMM3,%K2	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPTESTMQ %YMM14,%YMM4,%K3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPTESTMQ %YMM14,%YMM0,%K4	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VPXORQ %YMM15,%YMM1,%YMM1{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXORQ %YMM15,%YMM5,%YMM5{%K2}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXORQ %YMM15,%YMM6,%YMM6{%K3}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXORQ %YMM15,%YMM7,%YMM7{%K4}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VMOVDQU %YMM1,0x3b0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
VMOVDQU %YMM5,0x3d0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
VMOVDQU %YMM6,0x3f0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
VMOVDQU %YMM7,0x410(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
ADD $0x10,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP $0xe0,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 2f40 <main+0xa60>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code