OV - attention-clang-skl256 - Loop 63 - attention-clang-skl256

	Loop Id: 63	Module: attention-clang-skl256	Source: attention_v2.cpp:27-33	Coverage: 0.56%

0x4060 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x4064 LEA	(%R15,%RSI,1),%EDI

0x4068 VMOVSS	%XMM0,(%RAX,%RDI,4)

0x406d INC	%RSI

0x4070 CMP	0x28(%RSP),%RSI

0x4075 JE	4030

0x4077 CMPL	$0x3,0xb8(%RSP)

0x407f JAE	4090

0x4081 VXORPS	%XMM0,%XMM0,%XMM0

0x4085 XOR	%EDI,%EDI

0x4087 JMP	4159

0x4090 VXORPS	%XMM0,%XMM0,%XMM0

0x4094 MOV	%RSI,%R8

0x4097 XOR	%EDI,%EDI

0x4099 MOV	0x140(%RSP),%R10

0x40a1 MOV	%R13,%RAX

0x40a4 LEA	(%R12,%R12,2),%R13

0x40a8 LEA	(%R12,%R12,1),%RDX

0x40ac NOPL	(%RAX)

  (32) 0x40b0 LEA	(%RCX,%RDI,1),%R9D

  (32) 0x40b4 VMOVSS	(%R14,%R9,4),%XMM1

  (32) 0x40ba VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (32) 0x40be MOV	%R8D,%R9D

  (32) 0x40c1 VMOVSS	(%R11,%R9,4),%XMM2

  (32) 0x40c7 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (32) 0x40cb LEA	0x1(%RCX,%RDI,1),%R9D

  (32) 0x40d0 VMOVSS	(%R14,%R9,4),%XMM3

  (32) 0x40d6 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (32) 0x40da LEA	(%R12,%R8,1),%R9D

  (32) 0x40de VMOVSS	(%R11,%R9,4),%XMM4

  (32) 0x40e4 VCVTSS2SD	%XMM4,%XMM4,%XMM4

  (32) 0x40e8 LEA	0x2(%RCX,%RDI,1),%R9D

  (32) 0x40ed VMOVSS	(%R14,%R9,4),%XMM5

  (32) 0x40f3 VFMADD213SD	%XMM0,%XMM1,%XMM2

  (32) 0x40f8 VCVTSS2SD	%XMM5,%XMM5,%XMM0

  (32) 0x40fc LEA	(%RDX,%R8,1),%R9D

  (32) 0x4100 VMOVSS	(%R11,%R9,4),%XMM1

  (32) 0x4106 VFMADD213SD	%XMM2,%XMM3,%XMM4

  (32) 0x410b VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (32) 0x410f LEA	0x3(%RCX,%RDI,1),%R9D

  (32) 0x4114 VMOVSS	(%R14,%R9,4),%XMM2

  (32) 0x411a VFMADD213SD	%XMM4,%XMM0,%XMM1

  (32) 0x411f VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (32) 0x4123 LEA	(%R13,%R8,1),%R9D

  (32) 0x4128 VMOVSS	(%R11,%R9,4),%XMM0

  (32) 0x412e VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (32) 0x4132 VFMADD213SD	%XMM1,%XMM2,%XMM0

  (32) 0x4137 ADD	$0x4,%RDI

  (32) 0x413b ADD	%RAX,%R8

  (32) 0x413e CMP	%RDI,%R10

  (32) 0x4141 JNE	40b0

0x4147 TEST	$0x3,%R12B

0x414b MOV	%RAX,%R13

0x414e MOV	0x30(%RSP),%RAX

0x4153 JE	4060

0x4159 MOV	%R12,%R8

0x415c IMUL	%RDI,%R8

0x4160 ADD	%RSI,%R8

0x4163 ADD	%ECX,%EDI

0x4165 MOV	0xb0(%RSP),%R9

0x416d NOPL	(%RAX)

  (64) 0x4170 MOV	%EDI,%R10D

  (64) 0x4173 VMOVSS	(%R14,%R10,4),%XMM1

  (64) 0x4179 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (64) 0x417d MOV	%R8D,%R10D

  (64) 0x4180 VMOVSS	(%R11,%R10,4),%XMM2

  (64) 0x4186 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (64) 0x418a VFMADD231SD	%XMM2,%XMM1,%XMM0

  (64) 0x418f ADD	%R12,%R8

  (64) 0x4192 INC	%EDI

  (64) 0x4194 DEC	%R9

  (64) 0x4197 JNE	4170

0x4199 JMP	4060

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.52
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.67
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	5.67
CQA cycles if fully vectorized	0.43
Front-end cycles	5.67
P0 cycles	3.42
P1 cycles	3.42
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.00
P5 cycles	3.42
P6 cycles	3.42
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.67
Nb uops	22.67
Nb loads	4.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.62
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.67
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	10.65
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	16.98
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.59
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.56

Metric	Value
CQA speedup if no scalar integer	2.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	0.38
Front-end cycles	4.75
P0 cycles	3.25
P1 cycles	3.25
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.00
P5 cycles	3.25
P6 cycles	3.25
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	19.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.05
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	11.11
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.75

Metric	Value
CQA speedup if no scalar integer	2.80
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	0.53
Front-end cycles	7.00
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	1.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	28.00
Nb loads	5.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.71
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	8.33
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	14.29
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.39

Metric	Value
CQA speedup if no scalar integer	2.63
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.25
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	5.25
CQA cycles if fully vectorized	0.38
Front-end cycles	5.25
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	21.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.10
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	12.50
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	16.67
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.54

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30,33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.67 to 0.43 cycles (13.16x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 28 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	21.67
nb uops	22.67
loop length	88.67
used x86 registers	10.33
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.42	3.42	2.00	2.00	1.00	3.42	3.42	1.00
cycles	3.42	3.42	2.00	2.00	1.00	3.42	3.42	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.67
Dispatch	3.42
Data deps.	0.00
Overall L1	5.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	10%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	11%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.67 cycles. At this rate:

3% of peak load performance is reached (4.90 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.73 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.75 to 2.25 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 20 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	18
nb uops	19
loop length	72
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.25	3.25	1.50	1.50	1.00	3.25	3.25	1.00
cycles	3.25	3.25	1.50	1.50	1.00	3.25	3.25	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.75
Dispatch	3.25
Data deps.	0.00
Overall L1	4.75

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	11%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	11%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles. At this rate:

3% of peak load performance is reached (4.21 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.84 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.75 to 3.25 cycles (1.46x speedup).

ASM code

In the binary file, the address of the loop is: 4077

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%R15,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS %XMM0,(%RAX,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x28(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 4030 <main+0x1b50>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMPL $0x3,0xb8(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
JAE 4090 <main+0x1bb0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4159 <main+0x1c79>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RSI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD %ECX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0xb0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4060 <main+0x1b80>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 2.50 cycles (2.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	27
nb uops	28
loop length	111
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.00	4.00	2.50	2.50	1.00	4.00	4.00	1.00
cycles	4.00	4.00	2.50	2.50	1.00	4.00	4.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	7.00
Dispatch	4.00
Data deps.	0.00
Overall L1	7.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	11%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

4% of peak load performance is reached (5.14 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.57 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4077

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%R15,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS %XMM0,(%RAX,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x28(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 4030 <main+0x1b50>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMPL $0x3,0xb8(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
JAE 4090 <main+0x1bb0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x140(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%R12,%R12,2),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA (%R12,%R12,1),%RDX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST $0x3,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x30(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JE 4060 <main+0x1b80>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RSI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD %ECX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0xb0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4060 <main+0x1b80>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.25 to 2.00 cycles (2.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 28 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	20
nb uops	21
loop length	83
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.00	3.00	2.00	2.00	1.00	3.00	3.00	1.00
cycles	3.00	3.00	2.00	2.00	1.00	3.00	3.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.25
Dispatch	3.00
Data deps.	0.00
Overall L1	5.25

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	11%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.25 cycles. At this rate:

4% of peak load performance is reached (5.33 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.76 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4077

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%R15,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS %XMM0,(%RAX,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x28(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 4030 <main+0x1b50>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMPL $0x3,0xb8(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
JAE 4090 <main+0x1bb0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x140(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%R12,%R12,2),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA (%R12,%R12,1),%RDX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST $0x3,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x30(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JE 4060 <main+0x1b80>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access