OV - attention-clang-skl256 - Loop 59 - attention-clang-skl256

0x41f0 MOV	(%RSP),%RDX

0x41f4 INC	%EDX

0x41f6 ADD	%R12,%RCX

0x41f9 CMP	0x40(%RSP),%EDX

0x41fd JE	4350

0x4203 MOV	%RDX,(%RSP)

0x4207 IMUL	%R12D,%EDX

0x420b XOR	%ESI,%ESI

0x420d JMP	4227

  (60) 0x4210 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (60) 0x4214 LEA	(%RDX,%RSI,1),%EDI

  (60) 0x4217 VMOVSS	%XMM0,(%R15,%RDI,4)

  (60) 0x421d INC	%RSI

  (60) 0x4220 CMP	0x28(%RSP),%RSI

  (60) 0x4225 JE	41f0

  (60) 0x4227 CMPL	$0x3,0xb8(%RSP)

  (60) 0x422f JAE	4240

  (60) 0x4231 VXORPS	%XMM0,%XMM0,%XMM0

  (60) 0x4235 XOR	%EDI,%EDI

  (60) 0x4237 JMP	4300

  (60) 0x4240 VXORPS	%XMM0,%XMM0,%XMM0

  (60) 0x4244 MOV	%RSI,%R8

  (60) 0x4247 XOR	%EDI,%EDI

  (60) 0x4249 MOV	0x140(%RSP),%R10

  (60) 0x4251 LEA	(%R12,%R12,2),%R11

  (60) 0x4255 LEA	(%R12,%R12,1),%RAX

  (60) 0x4259 NOPL	(%RAX)

    (33) 0x4260 LEA	(%RCX,%RDI,1),%R9D

    (33) 0x4264 VMOVSS	(%R14,%R9,4),%XMM1

    (33) 0x426a VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (33) 0x426e MOV	%R8D,%R9D

    (33) 0x4271 VMOVSS	(%RBX,%R9,4),%XMM2

    (33) 0x4277 VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (33) 0x427b LEA	0x1(%RCX,%RDI,1),%R9D

    (33) 0x4280 VMOVSS	(%R14,%R9,4),%XMM3

    (33) 0x4286 VCVTSS2SD	%XMM3,%XMM3,%XMM3

    (33) 0x428a LEA	(%R12,%R8,1),%R9D

    (33) 0x428e VMOVSS	(%RBX,%R9,4),%XMM4

    (33) 0x4294 VCVTSS2SD	%XMM4,%XMM4,%XMM4

    (33) 0x4298 LEA	0x2(%RCX,%RDI,1),%R9D

    (33) 0x429d VMOVSS	(%R14,%R9,4),%XMM5

    (33) 0x42a3 VFMADD213SD	%XMM0,%XMM1,%XMM2

    (33) 0x42a8 VCVTSS2SD	%XMM5,%XMM5,%XMM0

    (33) 0x42ac LEA	(%RAX,%R8,1),%R9D

    (33) 0x42b0 VMOVSS	(%RBX,%R9,4),%XMM1

    (33) 0x42b6 VFMADD213SD	%XMM2,%XMM3,%XMM4

    (33) 0x42bb VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (33) 0x42bf LEA	0x3(%RCX,%RDI,1),%R9D

    (33) 0x42c4 VMOVSS	(%R14,%R9,4),%XMM2

    (33) 0x42ca VFMADD213SD	%XMM4,%XMM0,%XMM1

    (33) 0x42cf VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (33) 0x42d3 LEA	(%R11,%R8,1),%R9D

    (33) 0x42d7 VMOVSS	(%RBX,%R9,4),%XMM0

    (33) 0x42dd VCVTSS2SD	%XMM0,%XMM0,%XMM0

    (33) 0x42e1 VFMADD213SD	%XMM1,%XMM2,%XMM0

    (33) 0x42e6 ADD	$0x4,%RDI

    (33) 0x42ea ADD	%R13,%R8

    (33) 0x42ed CMP	%RDI,%R10

    (33) 0x42f0 JNE	4260

  (60) 0x42f6 TEST	$0x3,%R12B

  (60) 0x42fa JE	4210

  (60) 0x4300 MOV	%R12,%R8

  (60) 0x4303 IMUL	%RDI,%R8

  (60) 0x4307 ADD	%RSI,%R8

  (60) 0x430a ADD	%ECX,%EDI

  (60) 0x430c MOV	0xb0(%RSP),%R9

  (60) 0x4314 NOPW	%CS:(%RAX,%RAX,1)

    (61) 0x4320 MOV	%EDI,%R10D

    (61) 0x4323 VMOVSS	(%R14,%R10,4),%XMM1

    (61) 0x4329 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (61) 0x432d MOV	%R8D,%R10D

    (61) 0x4330 VMOVSS	(%RBX,%R10,4),%XMM2

    (61) 0x4336 VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (61) 0x433a VFMADD231SD	%XMM2,%XMM1,%XMM0

    (61) 0x433f ADD	%R12,%R8

    (61) 0x4342 INC	%EDI

    (61) 0x4344 DEC	%R9

    (61) 0x4347 JNE	4320

  (60) 0x4349 JMP	4210

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 26 - 213

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

213:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:213-213
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.17
Front-end cycles	2.25
P0 cycles	1.50
P1 cycles	1.75
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.89
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	8.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:213-213
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.17
Front-end cycles	2.25
P0 cycles	1.50
P1 cycles	1.75
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.89
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	8.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-213
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,213.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,213.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.17 cycles (13.09x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	9
nb uops	9
loop length	31
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.50	1.50	1.00	1.00	1.00	1.50	1.50	1.00
cycles	1.50	1.75	1.00	1.00	1.00	1.50	1.50	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.25
Dispatch	1.75
Data deps.	0.00
Overall L1	2.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

4% of peak load performance is reached (5.33 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.56 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 1.75 cycles (1.29x speedup).

ASM code

In the binary file, the address of the loop is: 4203

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV (%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
INC %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD %R12,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP 0x40(%RSP),%EDX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4350 <main+0x1e70>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RDX,(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
IMUL %R12D,%EDX	1	0	1	0	0	0	0	0	0	3	1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4227 <main+0x1d47>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:26-213
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,213.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,213.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.17 cycles (13.09x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	9
nb uops	9
loop length	31
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.50	1.50	1.00	1.00	1.00	1.50	1.50	1.00
cycles	1.50	1.75	1.00	1.00	1.00	1.50	1.50	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.25
Dispatch	1.75
Data deps.	0.00
Overall L1	2.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

4% of peak load performance is reached (5.33 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.56 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 1.75 cycles (1.29x speedup).

ASM code

In the binary file, the address of the loop is: 4203

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV (%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
INC %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD %R12,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP 0x40(%RSP),%EDX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4350 <main+0x1e70>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RDX,(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
IMUL %R12D,%EDX	1	0	1	0	0	0	0	0	0	3	1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4227 <main+0x1d47>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code