OV - attention-clang-skl256 - Loop 53 - attention-clang-skl256

	Loop Id: 53	Module: attention-clang-skl256	Source: attention_v2.cpp:30-31	Coverage: 26.35%

0x4680 LEA	(%RCX,%R8,1),%EBX

0x4684 VMOVSS	(%RSI,%RBX,4),%XMM1    [1]

0x4689 VCVTSS2SD	%XMM1,%XMM1,%XMM1

0x468d MOV	%R11D,%EBX

0x4690 VMOVSS	(%R15,%RBX,4),%XMM2    [2]

0x4696 VCVTSS2SD	%XMM2,%XMM2,%XMM2

0x469a LEA	0x1(%RCX,%R8,1),%EBX

0x469f VMOVSS	(%RSI,%RBX,4),%XMM3    [1]

0x46a4 VCVTSS2SD	%XMM3,%XMM3,%XMM3

0x46a8 MOV	%R13D,%EBX

0x46ab VMOVSS	(%R15,%RBX,4),%XMM4    [2]

0x46b1 VCVTSS2SD	%XMM4,%XMM4,%XMM4

0x46b5 VFMADD213SD	%XMM0,%XMM1,%XMM2

0x46ba LEA	0x2(%RCX,%R8,1),%EBX

0x46bf VMOVSS	(%RSI,%RBX,4),%XMM0    [1]

0x46c4 VCVTSS2SD	%XMM0,%XMM0,%XMM0

0x46c8 VFMADD213SD	%XMM2,%XMM3,%XMM4

0x46cd MOV	%R10D,%EBX

0x46d0 VMOVSS	(%R15,%RBX,4),%XMM1    [2]

0x46d6 VCVTSS2SD	%XMM1,%XMM1,%XMM1

0x46da VFMADD213SD	%XMM4,%XMM0,%XMM1

0x46df LEA	0x3(%RCX,%R8,1),%EBX

0x46e4 VMOVSS	(%RSI,%RBX,4),%XMM0    [1]

0x46e9 VCVTSS2SD	%XMM0,%XMM0,%XMM2

0x46ed MOV	%R9D,%EBX

0x46f0 VMOVSS	(%R15,%RBX,4),%XMM0    [2]

0x46f6 VCVTSS2SD	%XMM0,%XMM0,%XMM0

0x46fa VFMADD213SD	%XMM1,%XMM2,%XMM0

0x46ff ADD	$0x4,%R8

0x4703 ADD	%RDX,%R9

0x4706 ADD	%RDX,%R10

0x4709 ADD	%RDX,%R11

0x470c ADD	%RDX,%R13

0x470f CMP	%R8,%RAX

0x4712 JNE	4680

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.60
CQA speedup if fully vectorized	13.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.52
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	1.23
Front-end cycles	10.50
P0 cycles	8.00
P1 cycles	8.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	8.00
P6 cycles	6.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	42.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.60
CQA speedup if fully vectorized	13.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.52
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	1.23
Front-end cycles	10.50
P0 cycles	8.00
P1 cycles	8.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	8.00
P6 cycles	6.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	42.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:30-31.

It is intermediate loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 4 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSS2SD: 8 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 8 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is loading 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	42
loop length	152
used x86 registers	11
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	8.00	8.00	4.00	4.00	0.00	8.00	6.00	0.00
cycles	8.00	8.00	4.00	4.00	0.00	8.00	6.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	10.50
Dispatch	8.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

1% of peak load performance is reached (2.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4680

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA (%RCX,%R8,1),%EBX	1	0	0.50	0	0	0.50	0	1	0.50	N/A
VMOVSS (%RSI,%RBX,4),%XMM1	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM1,%XMM1,%XMM1	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0.25	N/A
VMOVSS (%R15,%RBX,4),%XMM2	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM2,%XMM2,%XMM2	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
LEA 0x1(%RCX,%R8,1),%EBX	1	0	1	0	0	0	0	3	1	N/A
VMOVSS (%RSI,%RBX,4),%XMM3	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM3,%XMM3,%XMM3	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
MOV %R13D,%EBX	1	0	0	0	0	0	0	0	0.25	N/A
VMOVSS (%R15,%RBX,4),%XMM4	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM4,%XMM4,%XMM4	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
VFMADD213SD %XMM0,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x2(%RCX,%R8,1),%EBX	1	0	1	0	0	0	0	3	1	N/A
VMOVSS (%RSI,%RBX,4),%XMM0	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
VFMADD213SD %XMM2,%XMM3,%XMM4	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10D,%EBX	1	0	0	0	0	0	0	0	0.25	N/A
VMOVSS (%R15,%RBX,4),%XMM1	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM1,%XMM1,%XMM1	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
VFMADD213SD %XMM4,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x3(%RCX,%R8,1),%EBX	1	0	1	0	0	0	0	3	1	N/A
VMOVSS (%RSI,%RBX,4),%XMM0	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM0,%XMM0,%XMM2	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
MOV %R9D,%EBX	1	0	0	0	0	0	0	0	0.25	N/A
VMOVSS (%R15,%RBX,4),%XMM0	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
VFMADD213SD %XMM1,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x4,%R8	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
ADD %RDX,%R9	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
ADD %RDX,%R10	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
ADD %RDX,%R11	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
ADD %RDX,%R13	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP %R8,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JNE 4680 <main+0x21a0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:30-31.

It is intermediate loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 4 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSS2SD: 8 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 8 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is loading 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	42
loop length	152
used x86 registers	11
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	8.00	8.00	4.00	4.00	0.00	8.00	6.00	0.00
cycles	8.00	8.00	4.00	4.00	0.00	8.00	6.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	10.50
Dispatch	8.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

1% of peak load performance is reached (2.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4680

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA (%RCX,%R8,1),%EBX	1	0	0.50	0	0	0.50	0	1	0.50	N/A
VMOVSS (%RSI,%RBX,4),%XMM1	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM1,%XMM1,%XMM1	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0.25	N/A
VMOVSS (%R15,%RBX,4),%XMM2	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM2,%XMM2,%XMM2	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
LEA 0x1(%RCX,%R8,1),%EBX	1	0	1	0	0	0	0	3	1	N/A
VMOVSS (%RSI,%RBX,4),%XMM3	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM3,%XMM3,%XMM3	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
MOV %R13D,%EBX	1	0	0	0	0	0	0	0	0.25	N/A
VMOVSS (%R15,%RBX,4),%XMM4	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM4,%XMM4,%XMM4	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
VFMADD213SD %XMM0,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x2(%RCX,%R8,1),%EBX	1	0	1	0	0	0	0	3	1	N/A
VMOVSS (%RSI,%RBX,4),%XMM0	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
VFMADD213SD %XMM2,%XMM3,%XMM4	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10D,%EBX	1	0	0	0	0	0	0	0	0.25	N/A
VMOVSS (%R15,%RBX,4),%XMM1	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM1,%XMM1,%XMM1	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
VFMADD213SD %XMM4,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x3(%RCX,%R8,1),%EBX	1	0	1	0	0	0	0	3	1	N/A
VMOVSS (%RSI,%RBX,4),%XMM0	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM0,%XMM0,%XMM2	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
MOV %R9D,%EBX	1	0	0	0	0	0	0	0	0.25	N/A
VMOVSS (%R15,%RBX,4),%XMM0	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
VCVTSS2SD %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	1	0	5	1	scal (6.3%)
VFMADD213SD %XMM1,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x4,%R8	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
ADD %RDX,%R9	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
ADD %RDX,%R10	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
ADD %RDX,%R11	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
ADD %RDX,%R13	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP %R8,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JNE 4680 <main+0x21a0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code