OV - attention-clang-skl256 - Loop 52 - attention-clang-skl256

	Loop Id: 52	Module: attention-clang-skl256	Source: attention_v2.cpp:26-33	Coverage: 6.91%

0x4543 MOV	0x20(%RSP),%R15

0x4548 NOPL	(%RAX,%RAX,1)

0x4550 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x4554 VDIVSS	0x1c4(%RSP),%XMM0,%XMM0

0x455d MOV	(%RSP),%RAX

0x4561 LEA	(%RAX,%RDI,1),%R8D

0x4565 MOV	0x70(%RSP),%R13

0x456a VMOVSS	%XMM0,(%R13,%R8,4)

0x4571 INC	%RDI

0x4574 CMP	0x48(%RSP),%RDI

0x4579 MOV	0x40(%RSP),%RAX

0x457e MOV	%R15,%RBX

0x4581 MOV	0x138(%RSP),%R15

0x4589 JE	4500

0x458f VPXOR	%XMM0,%XMM0,%XMM0

0x4593 MOV	0x28(%RSP),%RAX

0x4598 CMP	$0x4,%EAX

0x459b JB	45ba

0x459d MOV	%EDI,%R8D

0x45a0 ADD	0xb8(%RSP),%R8D

0x45a8 SETB	%R8B

0x45ac OR	0xc0(%RSP),%R8B

0x45b4 JE	4720

0x45ba XOR	%R9D,%R9D

0x45bd TEST	$0x3,%R12B

0x45c1 JE	4620

0x45c3 MOV	0x40(%RSP),%R13

0x45c8 MOV	%R13,%R10

0x45cb IMUL	%R9,%R10

0x45cf ADD	%RDI,%R10

0x45d2 MOV	0xb0(%RSP),%R11

0x45da MOV	%R9,%R8

0x45dd MOV	0x18(%RSP),%RSI

0x45e2 MOV	0x20(%RSP),%R15

0x45e7 NOPW	(%RAX,%RAX,1)

  (54) 0x45f0 LEA	(%RCX,%R8,1),%EBX

  (54) 0x45f4 VMOVSS	(%RSI,%RBX,4),%XMM1

  (54) 0x45f9 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (54) 0x45fd MOV	%R10D,%EBX

  (54) 0x4600 VMOVSS	(%R15,%RBX,4),%XMM2

  (54) 0x4606 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (54) 0x460a VFMADD231SD	%XMM2,%XMM1,%XMM0

  (54) 0x460f INC	%R8

  (54) 0x4612 ADD	%R13,%R10

  (54) 0x4615 DEC	%R11

  (54) 0x4618 JNE	45f0

0x461a JMP	462d

0x4620 MOV	%R9,%R8

0x4623 MOV	0x18(%RSP),%RSI

0x4628 MOV	0x20(%RSP),%R15

0x462d MOV	0x28(%RSP),%RAX

0x4632 SUB	%RAX,%R9

0x4635 CMP	$-0x4,%R9

0x4639 MOV	0x290(%RSP),%RDX

0x4641 JA	4550

0x4647 LEA	0x3(%R8),%R9

0x464b MOV	0x40(%RSP),%RBX

0x4650 IMUL	%RBX,%R9

0x4654 ADD	%RDI,%R9

0x4657 LEA	0x2(%R8),%R10

0x465b IMUL	%RBX,%R10

0x465f ADD	%RDI,%R10

0x4662 MOV	%RBX,%R11

0x4665 IMUL	%R8,%R11

0x4669 ADD	%RDI,%R11

0x466c LEA	0x1(%R8),%R13

0x4670 IMUL	%RBX,%R13

0x4674 ADD	%RDI,%R13

0x4677 NOPW	(%RAX,%RAX,1)

  (53) 0x4680 LEA	(%RCX,%R8,1),%EBX

  (53) 0x4684 VMOVSS	(%RSI,%RBX,4),%XMM1

  (53) 0x4689 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (53) 0x468d MOV	%R11D,%EBX

  (53) 0x4690 VMOVSS	(%R15,%RBX,4),%XMM2

  (53) 0x4696 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (53) 0x469a LEA	0x1(%RCX,%R8,1),%EBX

  (53) 0x469f VMOVSS	(%RSI,%RBX,4),%XMM3

  (53) 0x46a4 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (53) 0x46a8 MOV	%R13D,%EBX

  (53) 0x46ab VMOVSS	(%R15,%RBX,4),%XMM4

  (53) 0x46b1 VCVTSS2SD	%XMM4,%XMM4,%XMM4

  (53) 0x46b5 VFMADD213SD	%XMM0,%XMM1,%XMM2

  (53) 0x46ba LEA	0x2(%RCX,%R8,1),%EBX

  (53) 0x46bf VMOVSS	(%RSI,%RBX,4),%XMM0

  (53) 0x46c4 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (53) 0x46c8 VFMADD213SD	%XMM2,%XMM3,%XMM4

  (53) 0x46cd MOV	%R10D,%EBX

  (53) 0x46d0 VMOVSS	(%R15,%RBX,4),%XMM1

  (53) 0x46d6 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (53) 0x46da VFMADD213SD	%XMM4,%XMM0,%XMM1

  (53) 0x46df LEA	0x3(%RCX,%R8,1),%EBX

  (53) 0x46e4 VMOVSS	(%RSI,%RBX,4),%XMM0

  (53) 0x46e9 VCVTSS2SD	%XMM0,%XMM0,%XMM2

  (53) 0x46ed MOV	%R9D,%EBX

  (53) 0x46f0 VMOVSS	(%R15,%RBX,4),%XMM0

  (53) 0x46f6 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (53) 0x46fa VFMADD213SD	%XMM1,%XMM2,%XMM0

  (53) 0x46ff ADD	$0x4,%R8

  (53) 0x4703 ADD	%RDX,%R9

  (53) 0x4706 ADD	%RDX,%R10

  (53) 0x4709 ADD	%RDX,%R11

  (53) 0x470c ADD	%RDX,%R13

  (53) 0x470f CMP	%R8,%RAX

  (53) 0x4712 JNE	4680

0x4718 JMP	4550

0x4720 CMP	$0x10,%EAX

0x4723 JAE	4735

0x4725 XOR	%R8D,%R8D

0x4728 MOV	0x18(%RSP),%RAX

0x472d MOV	%RBX,%R15

0x4730 JMP	47fd

0x4735 VPXOR	%XMM0,%XMM0,%XMM0

0x4739 XOR	%R8D,%R8D

0x473c VPXOR	%XMM1,%XMM1,%XMM1

0x4740 VXORPS	%XMM2,%XMM2,%XMM2

0x4744 VXORPS	%XMM3,%XMM3,%XMM3

0x4748 MOV	0x18(%RSP),%RSI

0x474d MOV	0x270(%RSP),%R10

0x4755 NOPW	%CS:(%RAX,%RAX,1)

  (55) 0x4760 LEA	(%RCX,%R8,1),%R9D

  (55) 0x4764 VCVTPS2PD	(%RSI,%R9,4),%YMM4

  (55) 0x476a VCVTPS2PD	0x10(%RSI,%R9,4),%YMM5

  (55) 0x4771 VCVTPS2PD	0x20(%RSI,%R9,4),%YMM6

  (55) 0x4778 VCVTPS2PD	0x30(%RSI,%R9,4),%YMM7

  (55) 0x477f LEA	(%RDI,%R8,1),%R9D

  (55) 0x4783 VCVTPS2PD	(%RBX,%R9,4),%YMM8

  (55) 0x4789 VFMADD231PD	%YMM8,%YMM4,%YMM0

  (55) 0x478e VCVTPS2PD	0x10(%RBX,%R9,4),%YMM4

  (55) 0x4795 VFMADD231PD	%YMM4,%YMM5,%YMM1

  (55) 0x479a VCVTPS2PD	0x20(%RBX,%R9,4),%YMM4

  (55) 0x47a1 VFMADD231PD	%YMM4,%YMM6,%YMM2

  (55) 0x47a6 VCVTPS2PD	0x30(%RBX,%R9,4),%YMM4

  (55) 0x47ad VFMADD231PD	%YMM4,%YMM7,%YMM3

  (55) 0x47b2 ADD	$0x10,%R8

  (55) 0x47b6 CMP	%R8,%R10

  (55) 0x47b9 JNE	4760

0x47bb VADDPD	%YMM0,%YMM1,%YMM0

0x47bf VADDPD	%YMM2,%YMM3,%YMM1

0x47c3 VADDPD	%YMM0,%YMM1,%YMM0

0x47c7 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x47cd VADDPD	%XMM1,%XMM0,%XMM0

0x47d1 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x47d6 VADDSD	%XMM1,%XMM0,%XMM0

0x47da CMP	%R10D,%EAX

0x47dd JE	4543

0x47e3 MOV	%R10,%R8

0x47e6 MOV	%R10,%R9

0x47e9 TEST	$0xc,%R12B

0x47ed MOV	0x18(%RSP),%RAX

0x47f2 MOV	0x20(%RSP),%R15

0x47f7 JE	45bd

0x47fd VMOVQ	%XMM0,%XMM0

0x4801 MOV	0x140(%RSP),%RSI

0x4809 NOPL	(%RAX)

  (56) 0x4810 LEA	(%RCX,%R8,1),%R9D

  (56) 0x4814 VCVTPS2PD	(%RAX,%R9,4),%YMM1

  (56) 0x481a LEA	(%RDI,%R8,1),%R9D

  (56) 0x481e VCVTPS2PD	(%R15,%R9,4),%YMM2

  (56) 0x4824 VFMADD231PD	%YMM2,%YMM1,%YMM0

  (56) 0x4829 ADD	$0x4,%R8

  (56) 0x482d CMP	%R8,%RSI

  (56) 0x4830 JNE	4810

0x4832 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x4838 VADDPD	%XMM1,%XMM0,%XMM0

0x483c VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x4841 VADDSD	%XMM1,%XMM0,%XMM0

0x4845 MOV	%RSI,%R9

0x4848 CMP	%ESI,0x28(%RSP)

0x484c JE	4550

0x4852 JMP	45bd

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.33
CQA speedup if FP arith vectorized	2.78
CQA speedup if fully vectorized	9.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.82
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.00
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	2.54
Front-end cycles	25.00
P0 cycles	13.75
P1 cycles	13.75
P2 cycles	13.00
P3 cycles	13.00
P4 cycles	1.00
P5 cycles	13.75
P6 cycles	13.75
P7 cycles	1.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	100.00
Nb loads	26.00
Nb stores	1.00
Nb stack references	15.00
FLOP/cycle	0.76
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.72
Bytes prefetched	0.00
Bytes loaded	189.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	28.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	41.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	39.13
Vector-efficiency ratio all	16.75
Vector-efficiency ratio load	11.93
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.96
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	16.30

Metric	Value
CQA speedup if no scalar integer	3.33
CQA speedup if FP arith vectorized	2.78
CQA speedup if fully vectorized	9.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.82
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.00
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	2.54
Front-end cycles	25.00
P0 cycles	13.75
P1 cycles	13.75
P2 cycles	13.00
P3 cycles	13.00
P4 cycles	1.00
P5 cycles	13.75
P6 cycles	13.75
P7 cycles	1.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	100.00
Nb loads	26.00
Nb stores	1.00
Nb stack references	15.00
FLOP/cycle	0.76
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.72
Bytes prefetched	0.00
Bytes loaded	189.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	28.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	41.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	39.13
Vector-efficiency ratio all	16.75
Vector-efficiency ratio load	11.93
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.96
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	16.30

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 7.50 cycles (3.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
41% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 19 FP arithmetical operations:

18: addition or subtraction
1: divide

The binary loop is loading 189 bytes (23 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	100
loop length	462
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.00 cycles
front end	25.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	13.75	13.75	13.00	13.00	1.00	13.75	13.75	1.00
cycles	13.75	13.75	13.00	13.00	1.00	13.75	13.75	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	25.00
Dispatch	13.75
DIV/SQRT	3.00
Overall L1	25.00

Vectorization ratios

INT

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	68%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	85%

INT+FP

all	28%
load	0%
store	0%
mul	0%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	39%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	25%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	23%

INT+FP

all	16%
load	11%
store	6%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.00 cycles. At this rate:

5% of peak load performance is reached (7.56 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.16 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.00 to 13.75 cycles (1.82x speedup).

ASM code

In the binary file, the address of the loop is: 458f

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x20(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
VDIVSS 0x1c4(%RSP),%XMM0,%XMM0	1	1	0	0.50	0.50	0	0	0	0	11	3	scal (6.3%)
MOV (%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RAX,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x70(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R13,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x48(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV 0x40(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R15,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x138(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 4500 <main+0x2020>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x28(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP $0x4,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JB 45ba <main+0x20da>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0xb8(%RSP),%R8D	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0xc0(%RSP),%R8B	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4720 <main+0x2240>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST $0x3,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4620 <main+0x2140>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x40(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xb0(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x18(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x20(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 462d <main+0x214d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x18(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x20(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x290(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JA 4550 <main+0x2070>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x3(%R8),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x40(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %RBX,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,%R11	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x1(%R8),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %RBX,%R13	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4550 <main+0x2070>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x10,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JAE 4735 <main+0x2255>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x18(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
JMP 47fd <main+0x231d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x18(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x270(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R10D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 4543 <main+0x2063>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0xc,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0x18(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x20(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 45bd <main+0x20dd>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	scal (12.5%)
MOV 0x140(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %ESI,0x28(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4550 <main+0x2070>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 45bd <main+0x20dd>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 7.50 cycles (3.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
41% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 19 FP arithmetical operations:

18: addition or subtraction
1: divide

The binary loop is loading 189 bytes (23 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	100
loop length	462
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.00 cycles
front end	25.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	13.75	13.75	13.00	13.00	1.00	13.75	13.75	1.00
cycles	13.75	13.75	13.00	13.00	1.00	13.75	13.75	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	25.00
Dispatch	13.75
DIV/SQRT	3.00
Overall L1	25.00

Vectorization ratios

INT

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	68%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	85%

INT+FP

all	28%
load	0%
store	0%
mul	0%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	39%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	25%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	23%

INT+FP

all	16%
load	11%
store	6%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.00 cycles. At this rate:

5% of peak load performance is reached (7.56 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.16 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 458f

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x20(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
VDIVSS 0x1c4(%RSP),%XMM0,%XMM0	1	1	0	0.50	0.50	0	0	0	0	11	3	scal (6.3%)
MOV (%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RAX,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x70(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R13,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x48(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV 0x40(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R15,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x138(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 4500 <main+0x2020>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x28(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP $0x4,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JB 45ba <main+0x20da>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0xb8(%RSP),%R8D	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0xc0(%RSP),%R8B	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4720 <main+0x2240>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST $0x3,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4620 <main+0x2140>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x40(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xb0(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x18(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x20(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 462d <main+0x214d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x18(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x20(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x290(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JA 4550 <main+0x2070>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x3(%R8),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x40(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
IMUL %RBX,%R9	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %RBX,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,%R11	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x1(%R8),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %RBX,%R13	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4550 <main+0x2070>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x10,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JAE 4735 <main+0x2255>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x18(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
JMP 47fd <main+0x231d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x18(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x270(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R10D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 4543 <main+0x2063>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0xc,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0x18(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x20(%RSP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 45bd <main+0x20dd>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	scal (12.5%)
MOV 0x140(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %ESI,0x28(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4550 <main+0x2070>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 45bd <main+0x20dd>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code