OV - attention-clang-skl256 - Loop 51 - attention-clang-skl256

0x4500 MOV	0xe0(%RSP),%RDX

0x4508 INC	%EDX

0x450a ADD	%R12,%RCX

0x450d CMP	%EAX,%EDX

0x450f JE	4860

0x4515 MOV	%EDX,%ESI

0x4517 IMUL	%R12D,%ESI

0x451b MOV	%RDX,0xe0(%RSP)

0x4523 IMUL	%EAX,%EDX

0x4526 MOV	%RDX,(%RSP)

0x452a ADD	0xb8(%RSP),%ESI

0x4531 SETB	%AL

0x4534 OR	0x17(%RSP),%AL

0x4538 MOV	%AL,0xc0(%RSP)

0x453f XOR	%EDI,%EDI

0x4541 JMP	458f

  (52) 0x4543 MOV	0x20(%RSP),%R15

  (52) 0x4548 NOPL	(%RAX,%RAX,1)

  (52) 0x4550 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (52) 0x4554 VDIVSS	0x1c4(%RSP),%XMM0,%XMM0

  (52) 0x455d MOV	(%RSP),%RAX

  (52) 0x4561 LEA	(%RAX,%RDI,1),%R8D

  (52) 0x4565 MOV	0x70(%RSP),%R13

  (52) 0x456a VMOVSS	%XMM0,(%R13,%R8,4)

  (52) 0x4571 INC	%RDI

  (52) 0x4574 CMP	0x48(%RSP),%RDI

  (52) 0x4579 MOV	0x40(%RSP),%RAX

  (52) 0x457e MOV	%R15,%RBX

  (52) 0x4581 MOV	0x138(%RSP),%R15

  (52) 0x4589 JE	4500

  (52) 0x458f VPXOR	%XMM0,%XMM0,%XMM0

  (52) 0x4593 MOV	0x28(%RSP),%RAX

  (52) 0x4598 CMP	$0x4,%EAX

  (52) 0x459b JB	45ba

  (52) 0x459d MOV	%EDI,%R8D

  (52) 0x45a0 ADD	0xb8(%RSP),%R8D

  (52) 0x45a8 SETB	%R8B

  (52) 0x45ac OR	0xc0(%RSP),%R8B

  (52) 0x45b4 JE	4720

  (52) 0x45ba XOR	%R9D,%R9D

  (52) 0x45bd TEST	$0x3,%R12B

  (52) 0x45c1 JE	4620

  (52) 0x45c3 MOV	0x40(%RSP),%R13

  (52) 0x45c8 MOV	%R13,%R10

  (52) 0x45cb IMUL	%R9,%R10

  (52) 0x45cf ADD	%RDI,%R10

  (52) 0x45d2 MOV	0xb0(%RSP),%R11

  (52) 0x45da MOV	%R9,%R8

  (52) 0x45dd MOV	0x18(%RSP),%RSI

  (52) 0x45e2 MOV	0x20(%RSP),%R15

  (52) 0x45e7 NOPW	(%RAX,%RAX,1)

    (54) 0x45f0 LEA	(%RCX,%R8,1),%EBX

    (54) 0x45f4 VMOVSS	(%RSI,%RBX,4),%XMM1

    (54) 0x45f9 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (54) 0x45fd MOV	%R10D,%EBX

    (54) 0x4600 VMOVSS	(%R15,%RBX,4),%XMM2

    (54) 0x4606 VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (54) 0x460a VFMADD231SD	%XMM2,%XMM1,%XMM0

    (54) 0x460f INC	%R8

    (54) 0x4612 ADD	%R13,%R10

    (54) 0x4615 DEC	%R11

    (54) 0x4618 JNE	45f0

  (52) 0x461a JMP	462d

  (52) 0x4620 MOV	%R9,%R8

  (52) 0x4623 MOV	0x18(%RSP),%RSI

  (52) 0x4628 MOV	0x20(%RSP),%R15

  (52) 0x462d MOV	0x28(%RSP),%RAX

  (52) 0x4632 SUB	%RAX,%R9

  (52) 0x4635 CMP	$-0x4,%R9

  (52) 0x4639 MOV	0x290(%RSP),%RDX

  (52) 0x4641 JA	4550

  (52) 0x4647 LEA	0x3(%R8),%R9

  (52) 0x464b MOV	0x40(%RSP),%RBX

  (52) 0x4650 IMUL	%RBX,%R9

  (52) 0x4654 ADD	%RDI,%R9

  (52) 0x4657 LEA	0x2(%R8),%R10

  (52) 0x465b IMUL	%RBX,%R10

  (52) 0x465f ADD	%RDI,%R10

  (52) 0x4662 MOV	%RBX,%R11

  (52) 0x4665 IMUL	%R8,%R11

  (52) 0x4669 ADD	%RDI,%R11

  (52) 0x466c LEA	0x1(%R8),%R13

  (52) 0x4670 IMUL	%RBX,%R13

  (52) 0x4674 ADD	%RDI,%R13

  (52) 0x4677 NOPW	(%RAX,%RAX,1)

    (53) 0x4680 LEA	(%RCX,%R8,1),%EBX

    (53) 0x4684 VMOVSS	(%RSI,%RBX,4),%XMM1

    (53) 0x4689 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (53) 0x468d MOV	%R11D,%EBX

    (53) 0x4690 VMOVSS	(%R15,%RBX,4),%XMM2

    (53) 0x4696 VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (53) 0x469a LEA	0x1(%RCX,%R8,1),%EBX

    (53) 0x469f VMOVSS	(%RSI,%RBX,4),%XMM3

    (53) 0x46a4 VCVTSS2SD	%XMM3,%XMM3,%XMM3

    (53) 0x46a8 MOV	%R13D,%EBX

    (53) 0x46ab VMOVSS	(%R15,%RBX,4),%XMM4

    (53) 0x46b1 VCVTSS2SD	%XMM4,%XMM4,%XMM4

    (53) 0x46b5 VFMADD213SD	%XMM0,%XMM1,%XMM2

    (53) 0x46ba LEA	0x2(%RCX,%R8,1),%EBX

    (53) 0x46bf VMOVSS	(%RSI,%RBX,4),%XMM0

    (53) 0x46c4 VCVTSS2SD	%XMM0,%XMM0,%XMM0

    (53) 0x46c8 VFMADD213SD	%XMM2,%XMM3,%XMM4

    (53) 0x46cd MOV	%R10D,%EBX

    (53) 0x46d0 VMOVSS	(%R15,%RBX,4),%XMM1

    (53) 0x46d6 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (53) 0x46da VFMADD213SD	%XMM4,%XMM0,%XMM1

    (53) 0x46df LEA	0x3(%RCX,%R8,1),%EBX

    (53) 0x46e4 VMOVSS	(%RSI,%RBX,4),%XMM0

    (53) 0x46e9 VCVTSS2SD	%XMM0,%XMM0,%XMM2

    (53) 0x46ed MOV	%R9D,%EBX

    (53) 0x46f0 VMOVSS	(%R15,%RBX,4),%XMM0

    (53) 0x46f6 VCVTSS2SD	%XMM0,%XMM0,%XMM0

    (53) 0x46fa VFMADD213SD	%XMM1,%XMM2,%XMM0

    (53) 0x46ff ADD	$0x4,%R8

    (53) 0x4703 ADD	%RDX,%R9

    (53) 0x4706 ADD	%RDX,%R10

    (53) 0x4709 ADD	%RDX,%R11

    (53) 0x470c ADD	%RDX,%R13

    (53) 0x470f CMP	%R8,%RAX

    (53) 0x4712 JNE	4680

  (52) 0x4718 JMP	4550

  (52) 0x4720 CMP	$0x10,%EAX

  (52) 0x4723 JAE	4735

  (52) 0x4725 XOR	%R8D,%R8D

  (52) 0x4728 MOV	0x18(%RSP),%RAX

  (52) 0x472d MOV	%RBX,%R15

  (52) 0x4730 JMP	47fd

  (52) 0x4735 VPXOR	%XMM0,%XMM0,%XMM0

  (52) 0x4739 XOR	%R8D,%R8D

  (52) 0x473c VPXOR	%XMM1,%XMM1,%XMM1

  (52) 0x4740 VXORPS	%XMM2,%XMM2,%XMM2

  (52) 0x4744 VXORPS	%XMM3,%XMM3,%XMM3

  (52) 0x4748 MOV	0x18(%RSP),%RSI

  (52) 0x474d MOV	0x270(%RSP),%R10

  (52) 0x4755 NOPW	%CS:(%RAX,%RAX,1)

    (55) 0x4760 LEA	(%RCX,%R8,1),%R9D

    (55) 0x4764 VCVTPS2PD	(%RSI,%R9,4),%YMM4

    (55) 0x476a VCVTPS2PD	0x10(%RSI,%R9,4),%YMM5

    (55) 0x4771 VCVTPS2PD	0x20(%RSI,%R9,4),%YMM6

    (55) 0x4778 VCVTPS2PD	0x30(%RSI,%R9,4),%YMM7

    (55) 0x477f LEA	(%RDI,%R8,1),%R9D

    (55) 0x4783 VCVTPS2PD	(%RBX,%R9,4),%YMM8

    (55) 0x4789 VFMADD231PD	%YMM8,%YMM4,%YMM0

    (55) 0x478e VCVTPS2PD	0x10(%RBX,%R9,4),%YMM4

    (55) 0x4795 VFMADD231PD	%YMM4,%YMM5,%YMM1

    (55) 0x479a VCVTPS2PD	0x20(%RBX,%R9,4),%YMM4

    (55) 0x47a1 VFMADD231PD	%YMM4,%YMM6,%YMM2

    (55) 0x47a6 VCVTPS2PD	0x30(%RBX,%R9,4),%YMM4

    (55) 0x47ad VFMADD231PD	%YMM4,%YMM7,%YMM3

    (55) 0x47b2 ADD	$0x10,%R8

    (55) 0x47b6 CMP	%R8,%R10

    (55) 0x47b9 JNE	4760

  (52) 0x47bb VADDPD	%YMM0,%YMM1,%YMM0

  (52) 0x47bf VADDPD	%YMM2,%YMM3,%YMM1

  (52) 0x47c3 VADDPD	%YMM0,%YMM1,%YMM0

  (52) 0x47c7 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (52) 0x47cd VADDPD	%XMM1,%XMM0,%XMM0

  (52) 0x47d1 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (52) 0x47d6 VADDSD	%XMM1,%XMM0,%XMM0

  (52) 0x47da CMP	%R10D,%EAX

  (52) 0x47dd JE	4543

  (52) 0x47e3 MOV	%R10,%R8

  (52) 0x47e6 MOV	%R10,%R9

  (52) 0x47e9 TEST	$0xc,%R12B

  (52) 0x47ed MOV	0x18(%RSP),%RAX

  (52) 0x47f2 MOV	0x20(%RSP),%R15

  (52) 0x47f7 JE	45bd

  (52) 0x47fd VMOVQ	%XMM0,%XMM0

  (52) 0x4801 MOV	0x140(%RSP),%RSI

  (52) 0x4809 NOPL	(%RAX)

    (56) 0x4810 LEA	(%RCX,%R8,1),%R9D

    (56) 0x4814 VCVTPS2PD	(%RAX,%R9,4),%YMM1

    (56) 0x481a LEA	(%RDI,%R8,1),%R9D

    (56) 0x481e VCVTPS2PD	(%R15,%R9,4),%YMM2

    (56) 0x4824 VFMADD231PD	%YMM2,%YMM1,%YMM0

    (56) 0x4829 ADD	$0x4,%R8

    (56) 0x482d CMP	%R8,%RSI

    (56) 0x4830 JNE	4810

  (52) 0x4832 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (52) 0x4838 VADDPD	%XMM1,%XMM0,%XMM0

  (52) 0x483c VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (52) 0x4841 VADDSD	%XMM1,%XMM0,%XMM0

  (52) 0x4845 MOV	%RSI,%R9

  (52) 0x4848 CMP	%ESI,0x28(%RSP)

  (52) 0x484c JE	4550

  (52) 0x4852 JMP	45bd

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 26 - 254

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

254:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:254-254
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.31
Front-end cycles	4.00
P0 cycles	2.50
P1 cycles	3.25
P2 cycles	2.17
P3 cycles	1.83
P4 cycles	3.00
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	3.00
Nb stores	3.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.50
Bytes prefetched	0.00
Bytes loaded	13.00
Bytes stored	17.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:254-254
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.31
Front-end cycles	4.00
P0 cycles	2.50
P1 cycles	3.25
P2 cycles	2.17
P3 cycles	1.83
P4 cycles	3.00
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	3.00
Nb stores	3.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.50
Bytes prefetched	0.00
Bytes loaded	13.00
Bytes stored	17.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-254
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,254.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,254.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.31 cycles (12.80x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 13 bytes. The binary loop is storing 17 bytes.

General properties

nb instructions	16
nb uops	16
loop length	67
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	2.17	1.83	3.00	2.50	2.50	2.00
cycles	2.50	3.25	2.17	1.83	3.00	2.50	2.50	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.00
Dispatch	3.25
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	12%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

2% of peak load performance is reached (3.25 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.25 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 3.25 cycles (1.23x speedup).

ASM code

In the binary file, the address of the loop is: 4515

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xe0(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
ADD %R12,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP %EAX,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 4860 <main+0x2380>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
IMUL %R12D,%ESI	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV %RDX,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
IMUL %EAX,%EDX	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %RDX,(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
ADD 0xb8(%RSP),%ESI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %AL	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0x17(%RSP),%AL	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
MOV %AL,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 458f <main+0x20af>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:26-254
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,254.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,254.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.31 cycles (12.80x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 13 bytes. The binary loop is storing 17 bytes.

General properties

nb instructions	16
nb uops	16
loop length	67
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	2.17	1.83	3.00	2.50	2.50	2.00
cycles	2.50	3.25	2.17	1.83	3.00	2.50	2.50	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.00
Dispatch	3.25
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	12%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

2% of peak load performance is reached (3.25 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.25 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 3.25 cycles (1.23x speedup).

ASM code

In the binary file, the address of the loop is: 4515

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xe0(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
ADD %R12,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP %EAX,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 4860 <main+0x2380>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
IMUL %R12D,%ESI	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV %RDX,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
IMUL %EAX,%EDX	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %RDX,(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
ADD 0xb8(%RSP),%ESI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %AL	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0x17(%RSP),%AL	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
MOV %AL,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 458f <main+0x20af>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code