OV - attention-clang-skl256 - Loop 46 - attention-clang-skl256

	Loop Id: 46	Module: attention-clang-skl256	Source: attention_v2.cpp:43-61	Coverage: 0.26%

0x48c0 MOV	0xa0(%RSP),%RAX

0x48c8 VMOVSS	%XMM1,(%RAX,%R13,4)

0x48ce MOV	0x130(%RSP),%RCX

0x48d6 INC	%RCX

0x48d9 MOV	0x128(%RSP),%RAX

0x48e1 MOV	0x1d0(%RSP),%RDX

0x48e9 ADD	%RAX,%RDX

0x48ec ADD	%RAX,%RDI

0x48ef MOV	0x1b8(%RSP),%RSI

0x48f7 ADD	%RAX,%RSI

0x48fa MOV	%RSI,%RAX

0x48fd MOV	%RBX,%RSI

0x4900 CMP	0x48(%RSP),%RBX

0x4905 MOV	%RCX,%RBX

0x4908 MOV	0x250(%RSP),%R12

0x4910 JE	4ef0

0x4916 MOV	%RAX,0x1b8(%RSP)

0x491e MOV	%RBX,%R8

0x4921 AND	$-0x4,%R8

0x4925 MOV	%RBX,%R9

0x4928 AND	$-0x20,%R9

0x492c CMP	$0x4,%RBX

0x4930 JAE	4950

0x4932 XOR	%EAX,%EAX

0x4934 VMOVSS	0x16c8(%RIP),%XMM1

0x493c JMP	4a40

0x4950 CMP	$0x20,%RBX

0x4954 JAE	4970

0x4956 XOR	%EAX,%EAX

0x4958 VMOVSS	0x16a4(%RIP),%XMM1

0x4960 JMP	49f1

0x4970 MOV	%RBX,%RAX

0x4973 MOV	$0x7fffffffffffffe0,%RCX

0x497d AND	%RCX,%RAX

0x4980 XOR	%ECX,%ECX

0x4982 VBROADCASTSS	0x1679(%RIP),%YMM3

0x498b VMOVAPS	%YMM3,%YMM0

0x498f VMOVAPS	%YMM3,%YMM1

0x4993 VMOVAPS	%YMM3,%YMM2

0x4997 NOPW	(%RAX,%RAX,1)

  (35) 0x49a0 VMAXPS	-0x60(%RDX,%RCX,4),%YMM0,%YMM0

  (35) 0x49a6 VMAXPS	-0x40(%RDX,%RCX,4),%YMM1,%YMM1

  (35) 0x49ac VMAXPS	-0x20(%RDX,%RCX,4),%YMM2,%YMM2

  (35) 0x49b2 VMAXPS	(%RDX,%RCX,4),%YMM3,%YMM3

  (35) 0x49b7 ADD	$0x20,%RCX

  (35) 0x49bb CMP	%RCX,%R9

  (35) 0x49be JNE	49a0

0x49c0 VMAXPS	%YMM1,%YMM0,%YMM0

0x49c4 VMAXPS	%YMM3,%YMM2,%YMM1

0x49c8 VMAXPS	%YMM1,%YMM0,%YMM0

0x49cc VEXTRACTF128	$0x1,%YMM0,%XMM1

0x49d2 VMAXPS	%XMM1,%XMM0,%XMM0

0x49d6 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x49db VMAXPS	%XMM1,%XMM0,%XMM0

0x49df VMOVSHDUP	%XMM0,%XMM1

0x49e3 VMAXSS	%XMM1,%XMM0,%XMM1

0x49e7 CMP	%RAX,%RBX

0x49ea JE	4a4d

0x49ec TEST	$0x1c,%BL

0x49ef JE	4a40

0x49f1 MOV	%RAX,%RCX

0x49f4 MOV	$0x7fffffffffffffe0,%RAX

0x49fe ADD	$0x1c,%RAX

0x4a02 AND	%RBX,%RAX

0x4a05 VBROADCASTSS	%XMM1,%XMM0

0x4a0a NOPW	(%RAX,%RAX,1)

  (50) 0x4a10 VMAXPS	(%RDI,%RCX,4),%XMM0,%XMM0

  (50) 0x4a15 ADD	$0x4,%RCX

  (50) 0x4a19 CMP	%RCX,%R8

  (50) 0x4a1c JNE	4a10

0x4a1e VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x4a23 VMAXPS	%XMM1,%XMM0,%XMM0

0x4a27 VMOVSHDUP	%XMM0,%XMM1

0x4a2b VMAXSS	%XMM1,%XMM0,%XMM1

0x4a2f JMP	4a48

  (49) 0x4a40 VMAXSS	(%RDI,%RAX,4),%XMM1,%XMM1

  (49) 0x4a45 INC	%RAX

  (49) 0x4a48 CMP	%RAX,%RBX

  (49) 0x4a4b JNE	4a40

0x4a4d CMP	$0x4,%RBX

0x4a51 MOV	%RBX,0x130(%RSP)

0x4a59 MOV	%RDI,(%RSP)

0x4a5d VMOVAPS	%XMM1,0xe0(%RSP)

0x4a66 MOV	%RDX,0x1d0(%RSP)

0x4a6e MOV	%RSI,0x260(%RSP)

0x4a76 JAE	4a90

0x4a78 VXORPS	%XMM2,%XMM2,%XMM2

0x4a7c XOR	%R13D,%R13D

0x4a7f JMP	4d10

0x4a90 CMP	$0x20,%RBX

0x4a94 MOV	%R8,0x288(%RSP)

0x4a9c JAE	4ab0

0x4a9e VXORPS	%XMM2,%XMM2,%XMM2

0x4aa2 XOR	%R13D,%R13D

0x4aa5 JMP	4c65

0x4ab0 MOV	%RBX,%R13

0x4ab3 MOV	$0x7fffffffffffffe0,%RAX

0x4abd AND	%RAX,%R13

0x4ac0 VBROADCASTSS	%XMM1,%YMM0

0x4ac5 VMOVAPS	%YMM0,0x340(%RSP)

0x4ace VXORPS	%XMM1,%XMM1,%XMM1

0x4ad2 XOR	%EBX,%EBX

0x4ad4 VXORPS	%XMM2,%XMM2,%XMM2

0x4ad8 VXORPS	%XMM3,%XMM3,%XMM3

0x4adc VXORPD	%XMM4,%XMM4,%XMM4

0x4ae0 MOV	%R9,0x280(%RSP)

0x4ae8 NOPL	(%RAX,%RAX,1)

  (36) 0x4af0 VMOVAPD	%YMM4,0x2e0(%RSP)

  (36) 0x4af9 VMOVAPS	%YMM3,0x300(%RSP)

  (36) 0x4b02 VMOVAPS	%YMM2,0x1e0(%RSP)

  (36) 0x4b0b VMOVAPS	%YMM1,0xc0(%RSP)

  (36) 0x4b14 VMOVUPS	-0x60(%RDX,%RBX,4),%YMM0

  (36) 0x4b1a VMOVUPS	-0x40(%RDX,%RBX,4),%YMM1

  (36) 0x4b20 VMOVUPS	-0x20(%RDX,%RBX,4),%YMM2

  (36) 0x4b26 VMOVUPS	(%RDX,%RBX,4),%YMM3

  (36) 0x4b2b VMOVAPS	0x340(%RSP),%YMM4

  (36) 0x4b34 VSUBPS	%YMM4,%YMM0,%YMM0

  (36) 0x4b38 VSUBPS	%YMM4,%YMM1,%YMM1

  (36) 0x4b3c VMOVAPS	%YMM1,0x2a0(%RSP)

  (36) 0x4b45 VSUBPS	%YMM4,%YMM2,%YMM1

  (36) 0x4b49 VMOVAPS	%YMM1,0x2c0(%RSP)

  (36) 0x4b52 VSUBPS	%YMM4,%YMM3,%YMM1

  (36) 0x4b56 VMOVAPS	%YMM1,0x380(%RSP)

  (36) 0x4b5f CALL	10d0 <_ZGVdN8v_expf@plt>

  (36) 0x4b64 VMOVAPS	%YMM0,0x360(%RSP)

  (36) 0x4b6d VMOVAPS	0x2a0(%RSP),%YMM0

  (36) 0x4b76 CALL	10d0 <_ZGVdN8v_expf@plt>

  (36) 0x4b7b VMOVAPS	%YMM0,0x2a0(%RSP)

  (36) 0x4b84 VMOVAPS	0x2c0(%RSP),%YMM0

  (36) 0x4b8d CALL	10d0 <_ZGVdN8v_expf@plt>

  (36) 0x4b92 VMOVAPS	%YMM0,0x2c0(%RSP)

  (36) 0x4b9b VMOVAPS	0x380(%RSP),%YMM0

  (36) 0x4ba4 CALL	10d0 <_ZGVdN8v_expf@plt>

  (36) 0x4ba9 VMOVAPS	0x2e0(%RSP),%YMM4

  (36) 0x4bb2 VMOVAPS	0x300(%RSP),%YMM3

  (36) 0x4bbb VMOVAPS	0x1e0(%RSP),%YMM2

  (36) 0x4bc4 VMOVAPS	0xc0(%RSP),%YMM1

  (36) 0x4bcd MOV	0x280(%RSP),%R9

  (36) 0x4bd5 MOV	0x1d0(%RSP),%RDX

  (36) 0x4bdd VADDPS	0x360(%RSP),%YMM1,%YMM1

  (36) 0x4be6 VADDPS	0x2a0(%RSP),%YMM2,%YMM2

  (36) 0x4bef VADDPS	0x2c0(%RSP),%YMM3,%YMM3

  (36) 0x4bf8 VADDPS	%YMM4,%YMM0,%YMM4

  (36) 0x4bfc ADD	$0x20,%RBX

  (36) 0x4c00 CMP	%RBX,%R9

  (36) 0x4c03 JNE	4af0

0x4c09 VADDPS	%YMM1,%YMM2,%YMM0

0x4c0d VADDPS	%YMM0,%YMM3,%YMM0

0x4c11 VADDPS	%YMM0,%YMM4,%YMM0

0x4c15 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x4c1b VADDPS	%XMM1,%XMM0,%XMM0

0x4c1f VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x4c24 VADDPS	%XMM1,%XMM0,%XMM0

0x4c28 VMOVSHDUP	%XMM0,%XMM1

0x4c2c VADDSS	%XMM1,%XMM0,%XMM2

0x4c30 MOV	0x130(%RSP),%RBX

0x4c38 CMP	%R13,%RBX

0x4c3b JNE	4c4f

0x4c3d MOV	(%RSP),%RDI

0x4c41 VMOVAPS	0xe0(%RSP),%XMM1

0x4c4a JMP	4d4d

0x4c4f TEST	$0x1c,%BL

0x4c52 MOV	(%RSP),%RDI

0x4c56 VMOVAPS	0xe0(%RSP),%XMM1

0x4c5f JE	4d10

0x4c65 MOV	%RBX,%RCX

0x4c68 MOV	%R13,%RBX

0x4c6b VXORPS	%XMM0,%XMM0,%XMM0

0x4c6f VBLENDPS	$0x1,%XMM2,%XMM0,%XMM2

0x4c75 MOV	$0x7fffffffffffffe0,%RAX

0x4c7f LEA	0x1c(%RAX),%R13

0x4c83 AND	%RCX,%R13

0x4c86 VBROADCASTSS	%XMM1,%XMM0

0x4c8b VMOVAPS	%XMM0,0x1e0(%RSP)

0x4c94 NOPW	%CS:(%RAX,%RAX,1)

  (48) 0x4ca0 VMOVAPS	%XMM2,0xc0(%RSP)

  (48) 0x4ca9 VMOVUPS	(%RDI,%RBX,4),%XMM0

  (48) 0x4cae VSUBPS	0x1e0(%RSP),%XMM0,%XMM0

  (48) 0x4cb7 VZEROUPPER

  (48) 0x4cba CALL	1080 <_ZGVbN4v_expf@plt>

  (48) 0x4cbf VMOVAPS	0xc0(%RSP),%XMM2

  (48) 0x4cc8 MOV	0x288(%RSP),%R8

  (48) 0x4cd0 MOV	(%RSP),%RDI

  (48) 0x4cd4 VADDPS	%XMM2,%XMM0,%XMM2

  (48) 0x4cd8 ADD	$0x4,%RBX

  (48) 0x4cdc CMP	%RBX,%R8

  (48) 0x4cdf JNE	4ca0

0x4ce1 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM0

0x4ce6 VADDPS	%XMM0,%XMM2,%XMM0

0x4cea VMOVSHDUP	%XMM0,%XMM1

0x4cee VADDSS	%XMM1,%XMM0,%XMM2

0x4cf2 MOV	0x130(%RSP),%RBX

0x4cfa CMP	%R13,%RBX

0x4cfd VMOVAPS	0xe0(%RSP),%XMM1

0x4d06 JE	4d4d

0x4d08 NOPL	(%RAX,%RAX,1)

  (37) 0x4d10 VMOVAPS	%XMM2,0xc0(%RSP)

  (37) 0x4d19 VMOVSS	(%RDI,%R13,4),%XMM0

  (37) 0x4d1f VSUBSS	%XMM1,%XMM0,%XMM0

  (37) 0x4d23 VZEROUPPER

  (37) 0x4d26 CALL	1130 <expf@plt>

  (37) 0x4d2b VMOVAPS	0xc0(%RSP),%XMM2

  (37) 0x4d34 VMOVAPS	0xe0(%RSP),%XMM1

  (37) 0x4d3d MOV	(%RSP),%RDI

  (37) 0x4d41 VADDSS	%XMM2,%XMM0,%XMM2

  (37) 0x4d45 INC	%R13

  (37) 0x4d48 CMP	%R13,%RBX

  (37) 0x4d4b JNE	4d10

0x4d4d CMP	$0x8,%RBX

0x4d51 VMOVAPS	%XMM2,0xc0(%RSP)

0x4d5a JAE	4d80

0x4d5c MOV	%RBX,%RCX

0x4d5f XOR	%EBX,%EBX

0x4d61 MOV	0x1b8(%RSP),%R12

0x4d69 VMOVAPS	%XMM1,%XMM2

0x4d6d JMP	4e30

0x4d80 MOV	%RBX,%RAX

0x4d83 AND	$-0x8,%RAX

0x4d87 MOV	%RAX,0x1e0(%RSP)

0x4d8f MOV	$0x7fffffffffffffe0,%RAX

0x4d99 MOV	%RBX,%RCX

0x4d9c LEA	0x18(%RAX),%RBX

0x4da0 AND	%RCX,%RBX

0x4da3 VBROADCASTSS	%XMM2,%YMM0

0x4da8 VMOVAPS	%YMM0,0x300(%RSP)

0x4db1 VBROADCASTSS	%XMM1,%YMM0

0x4db6 VMOVAPS	%YMM0,0x2e0(%RSP)

0x4dbf XOR	%R13D,%R13D

0x4dc2 MOV	0x1b8(%RSP),%R12

0x4dca NOPW	(%RAX,%RAX,1)

  (38) 0x4dd0 VMOVUPS	(%RDI,%R13,4),%YMM0

  (38) 0x4dd6 VSUBPS	0x2e0(%RSP),%YMM0,%YMM0

  (38) 0x4ddf CALL	10d0 <_ZGVdN8v_expf@plt>

  (38) 0x4de4 MOV	(%RSP),%RDI

  (38) 0x4de8 VDIVPS	0x300(%RSP),%YMM0,%YMM0

  (38) 0x4df1 VMOVUPS	%YMM0,(%R12,%R13,4)

  (38) 0x4df7 ADD	$0x8,%R13

  (38) 0x4dfb CMP	%R13,0x1e0(%RSP)

  (38) 0x4e03 JNE	4dd0

0x4e05 MOV	0x130(%RSP),%RCX

0x4e0d CMP	%RBX,%RCX

0x4e10 VMOVAPS	0xe0(%RSP),%XMM2

0x4e19 VMOVAPS	0xc0(%RSP),%XMM1

0x4e22 JE	4e76

0x4e24 NOPW	%CS:(%RAX,%RAX,1)

  (47) 0x4e30 VMOVSS	(%RDI,%RBX,4),%XMM0

  (47) 0x4e35 VSUBSS	%XMM2,%XMM0,%XMM0

  (47) 0x4e39 MOV	%R12,%R13

  (47) 0x4e3c MOV	%RCX,%R12

  (47) 0x4e3f VZEROUPPER

  (47) 0x4e42 CALL	1130 <expf@plt>

  (47) 0x4e47 VMOVAPS	0xe0(%RSP),%XMM2

  (47) 0x4e50 MOV	%R12,%RCX

  (47) 0x4e53 MOV	%R13,%R12

  (47) 0x4e56 VMOVAPS	0xc0(%RSP),%XMM1

  (47) 0x4e5f MOV	(%RSP),%RDI

  (47) 0x4e63 VDIVSS	%XMM1,%XMM0,%XMM0

  (47) 0x4e67 VMOVSS	%XMM0,(%R13,%RBX,4)

  (47) 0x4e6e INC	%RBX

  (47) 0x4e71 CMP	%RBX,%RCX

  (47) 0x4e74 JNE	4e30

0x4e76 MOV	0x260(%RSP),%R13

0x4e7e LEA	0x1(%R13),%RBX

0x4e82 CMP	0x48(%RSP),%RBX

0x4e87 JAE	48c0

0x4e8d MOV	0x240(%RSP),%RDX

0x4e95 SUB	%R13D,%EDX

0x4e98 SAL	$0x2,%RDX

0x4e9c MOV	$0x3fffffffc,%RAX

0x4ea6 AND	%RAX,%RDX

0x4ea9 ADD	$0x4,%RDX

0x4ead MOV	0x238(%RSP),%RDI

0x4eb5 IMUL	%R13,%RDI

0x4eb9 ADD	$0x4,%RDI

0x4ebd AND	%RAX,%RDI

0x4ec0 ADD	0x8(%RSP),%RDI

0x4ec5 XOR	%ESI,%ESI

0x4ec7 VZEROUPPER

0x4eca CALL	1070 <memset@plt>

0x4ecf VMOVAPS	0xc0(%RSP),%XMM1

0x4ed8 MOV	(%RSP),%RDI

0x4edc JMP	48c0

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.15
CQA speedup if FP arith vectorized	2.12
CQA speedup if fully vectorized	8.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.88
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	45.75
CQA cycles if no scalar integer	21.25
CQA cycles if FP arith vectorized	21.55
CQA cycles if fully vectorized	5.57
Front-end cycles	45.75
P0 cycles	24.17
P1 cycles	24.33
P2 cycles	15.17
P3 cycles	14.83
P4 cycles	16.00
P5 cycles	24.25
P6 cycles	24.25
P7 cycles	15.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	179.00
Nb uops	183.00
Nb loads	29.00
Nb stores	15.00
Nb stack references	20.00
FLOP/cycle	0.83
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.49
Bytes prefetched	0.00
Bytes loaded	268.00
Bytes stored	212.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	41.59
Vectorization ratio load	28.57
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	46.15
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	43.28
Vector-efficiency ratio all	18.92
Vector-efficiency ratio load	15.18
Vector-efficiency ratio store	22.08
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.60
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.28

Metric	Value
CQA speedup if no scalar integer	2.15
CQA speedup if FP arith vectorized	2.12
CQA speedup if fully vectorized	8.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.88
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	45.75
CQA cycles if no scalar integer	21.25
CQA cycles if FP arith vectorized	21.55
CQA cycles if fully vectorized	5.57
Front-end cycles	45.75
P0 cycles	24.17
P1 cycles	24.33
P2 cycles	15.17
P3 cycles	14.83
P4 cycles	16.00
P5 cycles	24.25
P6 cycles	24.25
P7 cycles	15.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	179.00
Nb uops	183.00
Nb loads	29.00
Nb stores	15.00
Nb stack references	20.00
FLOP/cycle	0.83
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.49
Bytes prefetched	0.00
Bytes loaded	268.00
Bytes stored	212.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	41.59
Vectorization ratio load	28.57
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	46.15
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	43.28
Vector-efficiency ratio all	18.92
Vector-efficiency ratio load	15.18
Vector-efficiency ratio store	22.08
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.60
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.28

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:43-61
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43-44,47,52,55,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 210 paths individually, rerun with max-paths=210
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 210 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 45.75 to 21.25 cycles (2.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions).

Details

41% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
46% of SSE/AVX addition or subtraction instructions are used in vector version.
43% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

memset@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:52

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 6 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 268 bytes (67 single precision FP elements). The binary loop is storing 212 bytes (53 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	179
nb uops	183
loop length	907
used x86 registers	11
used mmx registers	0
used xmm registers	5
used ymm registers	5
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	45.75 cycles
front end	45.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	24.17	24.33	15.17	14.83	16.00	24.25	24.25	15.00
cycles	24.17	24.33	15.17	14.83	16.00	24.25	24.25	15.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	45.75
Dispatch	24.33
Overall L1	45.75

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	77%
load	66%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	77%

INT+FP

all	41%
load	28%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	46%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	18%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	29%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	18%
load	15%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 45.75 cycles. At this rate:

4% of peak load performance is reached (5.86 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.63 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 45.75 to 24.33 cycles (1.88x speedup).

ASM code

In the binary file, the address of the loop is: 4916

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xa0(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%RAX,%R13,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x130(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x128(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x1d0(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RAX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD %RAX,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0x1b8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RAX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP 0x48(%RSP),%RBX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x250(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 4ef0 <main+0x2a10>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x1b8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $-0x4,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $-0x20,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $0x4,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4950 <main+0x2470>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS 0x16c8(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
JMP 4a40 <main+0x2560>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4970 <main+0x2490>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS 0x16a4(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
JMP 49f1 <main+0x2511>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x7fffffffffffffe0,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
AND %RCX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VBROADCASTSS 0x1679(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
VMOVAPS %YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VMOVAPS %YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VMOVAPS %YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMAXPS %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPS %YMM3,%YMM2,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPS %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %RAX,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 4a4d <main+0x256d>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x1c,%BL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4a40 <main+0x2560>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV $0x7fffffffffffffe0,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD $0x1c,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RBX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
JMP 4a48 <main+0x2568>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x4,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,0x130(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
VMOVAPS %XMM1,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
MOV %RDX,0x1d0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RSI,0x260(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
JAE 4a90 <main+0x25b0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4d10 <main+0x2830>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R8,0x288(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
JAE 4ab0 <main+0x25d0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4c65 <main+0x2785>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x7fffffffffffffe0,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x340(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %R9,0x280(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPS %YMM1,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM3,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM4,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x130(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %R13,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JNE 4c4f <main+0x276f>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV (%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JMP 4d4d <main+0x286d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
TEST $0x1c,%BL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV (%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4d10 <main+0x2830>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VBLENDPS $0x1,%XMM2,%XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
MOV $0x7fffffffffffffe0,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
LEA 0x1c(%RAX),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND %RCX,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1e0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VSHUFPD $0x1,%XMM2,%XMM2,%XMM0	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDPS %XMM0,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x130(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %R13,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4d4d <main+0x286d>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x8,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS %XMM2,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
JAE 4d80 <main+0x28a0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x1b8(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VMOVAPS %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 4e30 <main+0x2950>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $-0x8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,0x1e0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0x7fffffffffffffe0,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
LEA 0x18(%RAX),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND %RCX,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VBROADCASTSS %XMM2,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x300(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x2e0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1b8(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x130(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %RBX,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS 0xe0(%RSP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4e76 <main+0x2996>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x260(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%R13),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x48(%RSP),%RBX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JAE 48c0 <main+0x23e0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x240(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
SUB %R13D,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV $0x3fffffffc,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x4,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x238(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
IMUL %R13,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD $0x4,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD 0x8(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1070 <memset@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
MOV (%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JMP 48c0 <main+0x23e0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:43-61
Module	attention-clang-skl256

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 210 paths individually, rerun with max-paths=210
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions).

Details

41% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
46% of SSE/AVX addition or subtraction instructions are used in vector version.
43% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

memset@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:52

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 268 bytes (67 single precision FP elements). The binary loop is storing 212 bytes (53 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	179
nb uops	183
loop length	907
used x86 registers	11
used mmx registers	0
used xmm registers	5
used ymm registers	5
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	45.75 cycles
front end	45.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	24.17	24.33	15.17	14.83	16.00	24.25	24.25	15.00
cycles	24.17	24.33	15.17	14.83	16.00	24.25	24.25	15.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	45.75
Dispatch	24.33
Overall L1	45.75

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	3%

all	77%
load	66%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	77%

INT+FP

all	41%
load	28%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	46%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	18%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	29%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	18%
load	15%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 45.75 cycles. At this rate:

4% of peak load performance is reached (5.86 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.63 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4916

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xa0(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%RAX,%R13,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x130(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x128(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x1d0(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RAX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD %RAX,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0x1b8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RAX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP 0x48(%RSP),%RBX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x250(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 4ef0 <main+0x2a10>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x1b8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $-0x4,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $-0x20,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $0x4,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4950 <main+0x2470>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS 0x16c8(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
JMP 4a40 <main+0x2560>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JAE 4970 <main+0x2490>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS 0x16a4(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
JMP 49f1 <main+0x2511>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x7fffffffffffffe0,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
AND %RCX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VBROADCASTSS 0x1679(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
VMOVAPS %YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VMOVAPS %YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VMOVAPS %YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMAXPS %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPS %YMM3,%YMM2,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMAXPS %YMM1,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %RAX,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 4a4d <main+0x256d>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x1c,%BL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4a40 <main+0x2560>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV $0x7fffffffffffffe0,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD $0x1c,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RBX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
JMP 4a48 <main+0x2568>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x4,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RBX,0x130(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
VMOVAPS %XMM1,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
MOV %RDX,0x1d0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RSI,0x260(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
JAE 4a90 <main+0x25b0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4d10 <main+0x2830>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x20,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R8,0x288(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
JAE 4ab0 <main+0x25d0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4c65 <main+0x2785>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x7fffffffffffffe0,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x340(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %R9,0x280(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPS %YMM1,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM3,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM0,%YMM4,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x130(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %R13,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JNE 4c4f <main+0x276f>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV (%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JMP 4d4d <main+0x286d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
TEST $0x1c,%BL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV (%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4d10 <main+0x2830>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VBLENDPS $0x1,%XMM2,%XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
MOV $0x7fffffffffffffe0,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
LEA 0x1c(%RAX),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND %RCX,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VBROADCASTSS %XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1e0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VSHUFPD $0x1,%XMM2,%XMM2,%XMM0	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDPS %XMM0,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x130(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %R13,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4d4d <main+0x286d>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x8,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS %XMM2,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
JAE 4d80 <main+0x28a0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x1b8(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VMOVAPS %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 4e30 <main+0x2950>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $-0x8,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,0x1e0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0x7fffffffffffffe0,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
LEA 0x18(%RAX),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND %RCX,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VBROADCASTSS %XMM2,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x300(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	3	1	scal (6.3%)
VMOVAPS %YMM0,0x2e0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1b8(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x130(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
CMP %RBX,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVAPS 0xe0(%RSP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
JE 4e76 <main+0x2996>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x260(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%R13),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x48(%RSP),%RBX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JAE 48c0 <main+0x23e0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x240(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
SUB %R13D,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV $0x3fffffffc,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x4,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x238(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
IMUL %R13,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD $0x4,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RAX,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD 0x8(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1070 <memset@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
MOV (%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JMP 48c0 <main+0x23e0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code