OV - attention-clang-skl256 - Loop 41 - attention-clang-skl256

	Loop Id: 41	Module: attention-clang-skl256	Source: attention_v2.cpp:27-33	Coverage: 0.81%

0x4f90 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x4f94 MOV	(%RSP),%RAX

0x4f98 LEA	(%RAX,%RDI,1),%R8D

0x4f9c MOV	0x68(%RSP),%R13

0x4fa1 VMOVSS	%XMM0,(%R13,%R8,4)

0x4fa8 INC	%RDI

0x4fab CMP	0x28(%RSP),%RDI

0x4fb0 MOV	0x38(%RSP),%RBX

0x4fb5 JE	4f40

0x4fb7 VXORPS	%XMM0,%XMM0,%XMM0

0x4fbb MOV	0x48(%RSP),%RAX

0x4fc0 CMP	$0x4,%EAX

0x4fc3 JB	4fe2

0x4fc5 MOV	%EDI,%R8D

0x4fc8 ADD	0x1d8(%RSP),%R8D

0x4fd0 SETB	%R8B

0x4fd4 OR	0xc0(%RSP),%R8B

0x4fdc JE	5150

0x4fe2 XOR	%R9D,%R9D

0x4fe5 MOV	0x298(%RSP),%R11

0x4fed TEST	%R11,%R11

0x4ff0 JE	5060

0x4ff2 MOV	%R12,%R10

0x4ff5 IMUL	%R9,%R10

0x4ff9 ADD	%RDI,%R10

0x4ffc MOV	%R9,%R8

0x4fff MOV	0x48(%RSP),%RAX

0x5004 MOV	0x8(%RSP),%RDX

0x5009 NOPL	(%RAX)

  (43) 0x5010 LEA	(%RCX,%R8,1),%EBX

  (43) 0x5014 VMOVSS	(%RDX,%RBX,4),%XMM1

  (43) 0x5019 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (43) 0x501d MOV	%R10D,%EBX

  (43) 0x5020 VMOVSS	(%R15,%RBX,4),%XMM2

  (43) 0x5026 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (43) 0x502a VFMADD231SD	%XMM2,%XMM1,%XMM0

  (43) 0x502f INC	%R8

  (43) 0x5032 ADD	%R12,%R10

  (43) 0x5035 DEC	%R11

  (43) 0x5038 JNE	5010

0x503a SUB	%RAX,%R9

0x503d CMP	$-0x4,%R9

0x5041 LEA	(,%R12,4),%RSI

0x5049 JA	4f90

0x504f JMP	5082

0x5060 MOV	%R9,%R8

0x5063 MOV	0x48(%RSP),%RAX

0x5068 MOV	0x8(%RSP),%RDX

0x506d SUB	%RAX,%R9

0x5070 CMP	$-0x4,%R9

0x5074 LEA	(,%R12,4),%RSI

0x507c JA	4f90

0x5082 LEA	0x3(%R8),%R9

0x5086 IMUL	%R12,%R9

0x508a ADD	%RDI,%R9

0x508d LEA	0x2(%R8),%R10

0x5091 IMUL	%R12,%R10

0x5095 ADD	%RDI,%R10

0x5098 MOV	%R12,%R11

0x509b IMUL	%R8,%R11

0x509f ADD	%RDI,%R11

0x50a2 LEA	0x1(%R8),%R13

0x50a6 IMUL	%R12,%R13

0x50aa ADD	%RDI,%R13

0x50ad NOPL	(%RAX)

  (42) 0x50b0 LEA	(%RCX,%R8,1),%EBX

  (42) 0x50b4 VMOVSS	(%RDX,%RBX,4),%XMM1

  (42) 0x50b9 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (42) 0x50bd MOV	%R11D,%EBX

  (42) 0x50c0 VMOVSS	(%R15,%RBX,4),%XMM2

  (42) 0x50c6 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (42) 0x50ca LEA	0x1(%RCX,%R8,1),%EBX

  (42) 0x50cf VMOVSS	(%RDX,%RBX,4),%XMM3

  (42) 0x50d4 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (42) 0x50d8 MOV	%R13D,%EBX

  (42) 0x50db VMOVSS	(%R15,%RBX,4),%XMM4

  (42) 0x50e1 VCVTSS2SD	%XMM4,%XMM4,%XMM4

  (42) 0x50e5 VFMADD213SD	%XMM0,%XMM1,%XMM2

  (42) 0x50ea LEA	0x2(%RCX,%R8,1),%EBX

  (42) 0x50ef VMOVSS	(%RDX,%RBX,4),%XMM0

  (42) 0x50f4 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (42) 0x50f8 VFMADD213SD	%XMM2,%XMM3,%XMM4

  (42) 0x50fd MOV	%R10D,%EBX

  (42) 0x5100 VMOVSS	(%R15,%RBX,4),%XMM1

  (42) 0x5106 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (42) 0x510a VFMADD213SD	%XMM4,%XMM0,%XMM1

  (42) 0x510f LEA	0x3(%RCX,%R8,1),%EBX

  (42) 0x5114 VMOVSS	(%RDX,%RBX,4),%XMM0

  (42) 0x5119 VCVTSS2SD	%XMM0,%XMM0,%XMM2

  (42) 0x511d MOV	%R9D,%EBX

  (42) 0x5120 VMOVSS	(%R15,%RBX,4),%XMM0

  (42) 0x5126 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (42) 0x512a VFMADD213SD	%XMM1,%XMM2,%XMM0

  (42) 0x512f ADD	$0x4,%R8

  (42) 0x5133 ADD	%RSI,%R9

  (42) 0x5136 ADD	%RSI,%R10

  (42) 0x5139 ADD	%RSI,%R11

  (42) 0x513c ADD	%RSI,%R13

  (42) 0x513f CMP	%R8,%RAX

  (42) 0x5142 JNE	50b0

0x5148 JMP	4f90

0x5150 CMP	$0x10,%EAX

0x5153 JAE	5162

0x5155 XOR	%R8D,%R8D

0x5158 MOV	0x8(%RSP),%RDX

0x515d JMP	5229

0x5162 VXORPS	%XMM0,%XMM0,%XMM0

0x5166 XOR	%R8D,%R8D

0x5169 VXORPS	%XMM1,%XMM1,%XMM1

0x516d VXORPS	%XMM2,%XMM2,%XMM2

0x5171 VXORPS	%XMM3,%XMM3,%XMM3

0x5175 MOV	0x268(%RSP),%R10

0x517d MOV	0x8(%RSP),%RDX

0x5182 NOPW	%CS:(%RAX,%RAX,1)

  (44) 0x5190 LEA	(%RCX,%R8,1),%R9D

  (44) 0x5194 VCVTPS2PD	(%RDX,%R9,4),%YMM4

  (44) 0x519a VCVTPS2PD	0x10(%RDX,%R9,4),%YMM5

  (44) 0x51a1 VCVTPS2PD	0x20(%RDX,%R9,4),%YMM6

  (44) 0x51a8 VCVTPS2PD	0x30(%RDX,%R9,4),%YMM7

  (44) 0x51af LEA	(%RDI,%R8,1),%R9D

  (44) 0x51b3 VCVTPS2PD	(%R15,%R9,4),%YMM8

  (44) 0x51b9 VFMADD231PD	%YMM8,%YMM4,%YMM0

  (44) 0x51be VCVTPS2PD	0x10(%R15,%R9,4),%YMM4

  (44) 0x51c5 VFMADD231PD	%YMM4,%YMM5,%YMM1

  (44) 0x51ca VCVTPS2PD	0x20(%R15,%R9,4),%YMM4

  (44) 0x51d1 VFMADD231PD	%YMM4,%YMM6,%YMM2

  (44) 0x51d6 VCVTPS2PD	0x30(%R15,%R9,4),%YMM4

  (44) 0x51dd VFMADD231PD	%YMM4,%YMM7,%YMM3

  (44) 0x51e2 ADD	$0x10,%R8

  (44) 0x51e6 CMP	%R8,%R10

  (44) 0x51e9 JNE	5190

0x51eb VADDPD	%YMM0,%YMM1,%YMM0

0x51ef VADDPD	%YMM2,%YMM3,%YMM1

0x51f3 VADDPD	%YMM0,%YMM1,%YMM0

0x51f7 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x51fd VADDPD	%XMM1,%XMM0,%XMM0

0x5201 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5206 VADDSD	%XMM1,%XMM0,%XMM0

0x520a CMP	%R10D,%EAX

0x520d JE	4f90

0x5213 MOV	%R10,%R8

0x5216 MOV	%R10,%R9

0x5219 TESTB	$0xc,0x40(%RSP)

0x521e MOV	0x8(%RSP),%RDX

0x5223 JE	4fe5

0x5229 VMOVQ	%XMM0,%XMM0

0x522d MOV	0x278(%RSP),%RAX

0x5235 NOPW	%CS:(%RAX,%RAX,1)

  (45) 0x5240 LEA	(%RCX,%R8,1),%R9D

  (45) 0x5244 VCVTPS2PD	(%RDX,%R9,4),%YMM1

  (45) 0x524a LEA	(%RDI,%R8,1),%R9D

  (45) 0x524e VCVTPS2PD	(%R15,%R9,4),%YMM2

  (45) 0x5254 VFMADD231PD	%YMM2,%YMM1,%YMM0

  (45) 0x5259 ADD	$0x4,%R8

  (45) 0x525d CMP	%R8,%RAX

  (45) 0x5260 JNE	5240

0x5262 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x5268 VADDPD	%XMM1,%XMM0,%XMM0

0x526c VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5271 VADDSD	%XMM1,%XMM0,%XMM0

0x5275 MOV	%RAX,%R9

0x5278 CMP	%EAX,0x48(%RSP)

0x527c JE	4f90

0x5282 JMP	4fe5

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.13
CQA speedup if FP arith vectorized	2.27
CQA speedup if fully vectorized	12.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	10.36
CQA cycles if fully vectorized	1.83
Front-end cycles	23.50
P0 cycles	14.75
P1 cycles	14.75
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	1.00
P5 cycles	14.75
P6 cycles	14.75
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	94.00
Nb loads	19.00
Nb stores	1.00
Nb stack references	12.00
FLOP/cycle	0.77
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.70
Bytes prefetched	0.00
Bytes loaded	130.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	28.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	38.46
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	37.50
Vector-efficiency ratio all	16.66
Vector-efficiency ratio load	11.41
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.08
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.69

Metric	Value
CQA speedup if no scalar integer	3.13
CQA speedup if FP arith vectorized	2.27
CQA speedup if fully vectorized	12.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	10.36
CQA cycles if fully vectorized	1.83
Front-end cycles	23.50
P0 cycles	14.75
P1 cycles	14.75
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	1.00
P5 cycles	14.75
P6 cycles	14.75
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	94.00
Nb loads	19.00
Nb stores	1.00
Nb stack references	12.00
FLOP/cycle	0.77
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.70
Bytes prefetched	0.00
Bytes loaded	130.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	28.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	38.46
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	37.50
Vector-efficiency ratio all	16.66
Vector-efficiency ratio load	11.41
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.08
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.69

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.50 to 7.50 cycles (3.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
38% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
37% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

18: addition or subtraction

The binary loop is loading 130 bytes (16 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	94
loop length	422
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.50 cycles
front end	23.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	14.75	14.75	9.50	9.50	1.00	14.75	14.75	1.00
cycles	14.75	14.75	9.50	9.50	1.00	14.75	14.75	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.50
Dispatch	14.75
Overall L1	23.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	28%
load	0%
store	0%
mul	0%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Vector efficiency ratios

INT

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	16%
load	11%
store	6%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.50 cycles. At this rate:

4% of peak load performance is reached (5.53 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.17 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.50 to 14.75 cycles (1.59x speedup).

ASM code

In the binary file, the address of the loop is: 4fb7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
MOV (%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RAX,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x68(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R13,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x28(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV 0x38(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 4f40 <main+0x2a60>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x48(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP $0x4,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JB 4fe2 <main+0x2b02>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0x1d8(%RSP),%R8D	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0xc0(%RSP),%R8B	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 5150 <main+0x2c70>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x298(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
TEST %R11,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 5060 <main+0x2b80>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x48(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA (,%R12,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
JA 4f90 <main+0x2ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 5082 <main+0x2ba2>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x48(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA (,%R12,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
JA 4f90 <main+0x2ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x3(%R8),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R12,%R11	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x1(%R8),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R13	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4f90 <main+0x2ab0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x10,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JAE 5162 <main+0x2c82>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JMP 5229 <main+0x2d49>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x268(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R10D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 4f90 <main+0x2ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TESTB $0xc,0x40(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (1.6%)
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 4fe5 <main+0x2b05>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	scal (12.5%)
MOV 0x278(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %EAX,0x48(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4f90 <main+0x2ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 4fe5 <main+0x2b05>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.50 to 7.50 cycles (3.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
38% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
37% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

18: addition or subtraction

The binary loop is loading 130 bytes (16 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	94
loop length	422
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.50 cycles
front end	23.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	14.75	14.75	9.50	9.50	1.00	14.75	14.75	1.00
cycles	14.75	14.75	9.50	9.50	1.00	14.75	14.75	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.50
Dispatch	14.75
Overall L1	23.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	28%
load	0%
store	0%
mul	0%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Vector efficiency ratios

INT

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	16%
load	11%
store	6%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.50 cycles. At this rate:

4% of peak load performance is reached (5.53 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.17 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4fb7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
MOV (%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RAX,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x68(%RSP),%R13	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R13,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x28(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV 0x38(%RSP),%RBX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 4f40 <main+0x2a60>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x48(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP $0x4,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JB 4fe2 <main+0x2b02>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0x1d8(%RSP),%R8D	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0xc0(%RSP),%R8B	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 5150 <main+0x2c70>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x298(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
TEST %R11,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 5060 <main+0x2b80>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R12,%R10	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x48(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA (,%R12,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
JA 4f90 <main+0x2ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 5082 <main+0x2ba2>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x48(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
SUB %RAX,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP $-0x4,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA (,%R12,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
JA 4f90 <main+0x2ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x3(%R8),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R9	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %R12,%R11	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
LEA 0x1(%R8),%R13	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
IMUL %R12,%R13	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4f90 <main+0x2ab0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
CMP $0x10,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JAE 5162 <main+0x2c82>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JMP 5229 <main+0x2d49>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x268(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R10D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 4f90 <main+0x2ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TESTB $0xc,0x40(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (1.6%)
MOV 0x8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JE 4fe5 <main+0x2b05>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	scal (12.5%)
MOV 0x278(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %EAX,0x48(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 4f90 <main+0x2ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 4fe5 <main+0x2b05>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code