OV - attention-clang-skl256 - Loop 40 - attention-clang-skl256

0x4f40 MOV	0xe0(%RSP),%RAX

0x4f48 INC	%EAX

0x4f4a MOV	0x40(%RSP),%RDX

0x4f4f ADD	%RDX,%RCX

0x4f52 CMP	%EDX,%EAX

0x4f54 JE	5290

0x4f5a MOV	%EAX,%ESI

0x4f5c IMUL	%EDX,%ESI

0x4f5f MOV	%RAX,0xe0(%RSP)

0x4f67 IMUL	%R12D,%EAX

0x4f6b MOV	%RAX,(%RSP)

0x4f6f ADD	0x1d8(%RSP),%ESI

0x4f76 SETB	%AL

0x4f79 OR	0x16(%RSP),%AL

0x4f7d MOV	%AL,0xc0(%RSP)

0x4f84 XOR	%EDI,%EDI

0x4f86 JMP	4fb7

  (41) 0x4f90 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (41) 0x4f94 MOV	(%RSP),%RAX

  (41) 0x4f98 LEA	(%RAX,%RDI,1),%R8D

  (41) 0x4f9c MOV	0x68(%RSP),%R13

  (41) 0x4fa1 VMOVSS	%XMM0,(%R13,%R8,4)

  (41) 0x4fa8 INC	%RDI

  (41) 0x4fab CMP	0x28(%RSP),%RDI

  (41) 0x4fb0 MOV	0x38(%RSP),%RBX

  (41) 0x4fb5 JE	4f40

  (41) 0x4fb7 VXORPS	%XMM0,%XMM0,%XMM0

  (41) 0x4fbb MOV	0x48(%RSP),%RAX

  (41) 0x4fc0 CMP	$0x4,%EAX

  (41) 0x4fc3 JB	4fe2

  (41) 0x4fc5 MOV	%EDI,%R8D

  (41) 0x4fc8 ADD	0x1d8(%RSP),%R8D

  (41) 0x4fd0 SETB	%R8B

  (41) 0x4fd4 OR	0xc0(%RSP),%R8B

  (41) 0x4fdc JE	5150

  (41) 0x4fe2 XOR	%R9D,%R9D

  (41) 0x4fe5 MOV	0x298(%RSP),%R11

  (41) 0x4fed TEST	%R11,%R11

  (41) 0x4ff0 JE	5060

  (41) 0x4ff2 MOV	%R12,%R10

  (41) 0x4ff5 IMUL	%R9,%R10

  (41) 0x4ff9 ADD	%RDI,%R10

  (41) 0x4ffc MOV	%R9,%R8

  (41) 0x4fff MOV	0x48(%RSP),%RAX

  (41) 0x5004 MOV	0x8(%RSP),%RDX

  (41) 0x5009 NOPL	(%RAX)

    (43) 0x5010 LEA	(%RCX,%R8,1),%EBX

    (43) 0x5014 VMOVSS	(%RDX,%RBX,4),%XMM1

    (43) 0x5019 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (43) 0x501d MOV	%R10D,%EBX

    (43) 0x5020 VMOVSS	(%R15,%RBX,4),%XMM2

    (43) 0x5026 VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (43) 0x502a VFMADD231SD	%XMM2,%XMM1,%XMM0

    (43) 0x502f INC	%R8

    (43) 0x5032 ADD	%R12,%R10

    (43) 0x5035 DEC	%R11

    (43) 0x5038 JNE	5010

  (41) 0x503a SUB	%RAX,%R9

  (41) 0x503d CMP	$-0x4,%R9

  (41) 0x5041 LEA	(,%R12,4),%RSI

  (41) 0x5049 JA	4f90

  (41) 0x504f JMP	5082

  (41) 0x5060 MOV	%R9,%R8

  (41) 0x5063 MOV	0x48(%RSP),%RAX

  (41) 0x5068 MOV	0x8(%RSP),%RDX

  (41) 0x506d SUB	%RAX,%R9

  (41) 0x5070 CMP	$-0x4,%R9

  (41) 0x5074 LEA	(,%R12,4),%RSI

  (41) 0x507c JA	4f90

  (41) 0x5082 LEA	0x3(%R8),%R9

  (41) 0x5086 IMUL	%R12,%R9

  (41) 0x508a ADD	%RDI,%R9

  (41) 0x508d LEA	0x2(%R8),%R10

  (41) 0x5091 IMUL	%R12,%R10

  (41) 0x5095 ADD	%RDI,%R10

  (41) 0x5098 MOV	%R12,%R11

  (41) 0x509b IMUL	%R8,%R11

  (41) 0x509f ADD	%RDI,%R11

  (41) 0x50a2 LEA	0x1(%R8),%R13

  (41) 0x50a6 IMUL	%R12,%R13

  (41) 0x50aa ADD	%RDI,%R13

  (41) 0x50ad NOPL	(%RAX)

    (42) 0x50b0 LEA	(%RCX,%R8,1),%EBX

    (42) 0x50b4 VMOVSS	(%RDX,%RBX,4),%XMM1

    (42) 0x50b9 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (42) 0x50bd MOV	%R11D,%EBX

    (42) 0x50c0 VMOVSS	(%R15,%RBX,4),%XMM2

    (42) 0x50c6 VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (42) 0x50ca LEA	0x1(%RCX,%R8,1),%EBX

    (42) 0x50cf VMOVSS	(%RDX,%RBX,4),%XMM3

    (42) 0x50d4 VCVTSS2SD	%XMM3,%XMM3,%XMM3

    (42) 0x50d8 MOV	%R13D,%EBX

    (42) 0x50db VMOVSS	(%R15,%RBX,4),%XMM4

    (42) 0x50e1 VCVTSS2SD	%XMM4,%XMM4,%XMM4

    (42) 0x50e5 VFMADD213SD	%XMM0,%XMM1,%XMM2

    (42) 0x50ea LEA	0x2(%RCX,%R8,1),%EBX

    (42) 0x50ef VMOVSS	(%RDX,%RBX,4),%XMM0

    (42) 0x50f4 VCVTSS2SD	%XMM0,%XMM0,%XMM0

    (42) 0x50f8 VFMADD213SD	%XMM2,%XMM3,%XMM4

    (42) 0x50fd MOV	%R10D,%EBX

    (42) 0x5100 VMOVSS	(%R15,%RBX,4),%XMM1

    (42) 0x5106 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (42) 0x510a VFMADD213SD	%XMM4,%XMM0,%XMM1

    (42) 0x510f LEA	0x3(%RCX,%R8,1),%EBX

    (42) 0x5114 VMOVSS	(%RDX,%RBX,4),%XMM0

    (42) 0x5119 VCVTSS2SD	%XMM0,%XMM0,%XMM2

    (42) 0x511d MOV	%R9D,%EBX

    (42) 0x5120 VMOVSS	(%R15,%RBX,4),%XMM0

    (42) 0x5126 VCVTSS2SD	%XMM0,%XMM0,%XMM0

    (42) 0x512a VFMADD213SD	%XMM1,%XMM2,%XMM0

    (42) 0x512f ADD	$0x4,%R8

    (42) 0x5133 ADD	%RSI,%R9

    (42) 0x5136 ADD	%RSI,%R10

    (42) 0x5139 ADD	%RSI,%R11

    (42) 0x513c ADD	%RSI,%R13

    (42) 0x513f CMP	%R8,%RAX

    (42) 0x5142 JNE	50b0

  (41) 0x5148 JMP	4f90

  (41) 0x5150 CMP	$0x10,%EAX

  (41) 0x5153 JAE	5162

  (41) 0x5155 XOR	%R8D,%R8D

  (41) 0x5158 MOV	0x8(%RSP),%RDX

  (41) 0x515d JMP	5229

  (41) 0x5162 VXORPS	%XMM0,%XMM0,%XMM0

  (41) 0x5166 XOR	%R8D,%R8D

  (41) 0x5169 VXORPS	%XMM1,%XMM1,%XMM1

  (41) 0x516d VXORPS	%XMM2,%XMM2,%XMM2

  (41) 0x5171 VXORPS	%XMM3,%XMM3,%XMM3

  (41) 0x5175 MOV	0x268(%RSP),%R10

  (41) 0x517d MOV	0x8(%RSP),%RDX

  (41) 0x5182 NOPW	%CS:(%RAX,%RAX,1)

    (44) 0x5190 LEA	(%RCX,%R8,1),%R9D

    (44) 0x5194 VCVTPS2PD	(%RDX,%R9,4),%YMM4

    (44) 0x519a VCVTPS2PD	0x10(%RDX,%R9,4),%YMM5

    (44) 0x51a1 VCVTPS2PD	0x20(%RDX,%R9,4),%YMM6

    (44) 0x51a8 VCVTPS2PD	0x30(%RDX,%R9,4),%YMM7

    (44) 0x51af LEA	(%RDI,%R8,1),%R9D

    (44) 0x51b3 VCVTPS2PD	(%R15,%R9,4),%YMM8

    (44) 0x51b9 VFMADD231PD	%YMM8,%YMM4,%YMM0

    (44) 0x51be VCVTPS2PD	0x10(%R15,%R9,4),%YMM4

    (44) 0x51c5 VFMADD231PD	%YMM4,%YMM5,%YMM1

    (44) 0x51ca VCVTPS2PD	0x20(%R15,%R9,4),%YMM4

    (44) 0x51d1 VFMADD231PD	%YMM4,%YMM6,%YMM2

    (44) 0x51d6 VCVTPS2PD	0x30(%R15,%R9,4),%YMM4

    (44) 0x51dd VFMADD231PD	%YMM4,%YMM7,%YMM3

    (44) 0x51e2 ADD	$0x10,%R8

    (44) 0x51e6 CMP	%R8,%R10

    (44) 0x51e9 JNE	5190

  (41) 0x51eb VADDPD	%YMM0,%YMM1,%YMM0

  (41) 0x51ef VADDPD	%YMM2,%YMM3,%YMM1

  (41) 0x51f3 VADDPD	%YMM0,%YMM1,%YMM0

  (41) 0x51f7 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (41) 0x51fd VADDPD	%XMM1,%XMM0,%XMM0

  (41) 0x5201 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (41) 0x5206 VADDSD	%XMM1,%XMM0,%XMM0

  (41) 0x520a CMP	%R10D,%EAX

  (41) 0x520d JE	4f90

  (41) 0x5213 MOV	%R10,%R8

  (41) 0x5216 MOV	%R10,%R9

  (41) 0x5219 TESTB	$0xc,0x40(%RSP)

  (41) 0x521e MOV	0x8(%RSP),%RDX

  (41) 0x5223 JE	4fe5

  (41) 0x5229 VMOVQ	%XMM0,%XMM0

  (41) 0x522d MOV	0x278(%RSP),%RAX

  (41) 0x5235 NOPW	%CS:(%RAX,%RAX,1)

    (45) 0x5240 LEA	(%RCX,%R8,1),%R9D

    (45) 0x5244 VCVTPS2PD	(%RDX,%R9,4),%YMM1

    (45) 0x524a LEA	(%RDI,%R8,1),%R9D

    (45) 0x524e VCVTPS2PD	(%R15,%R9,4),%YMM2

    (45) 0x5254 VFMADD231PD	%YMM2,%YMM1,%YMM0

    (45) 0x5259 ADD	$0x4,%R8

    (45) 0x525d CMP	%R8,%RAX

    (45) 0x5260 JNE	5240

  (41) 0x5262 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (41) 0x5268 VADDPD	%XMM1,%XMM0,%XMM0

  (41) 0x526c VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (41) 0x5271 VADDSD	%XMM1,%XMM0,%XMM0

  (41) 0x5275 MOV	%RAX,%R9

  (41) 0x5278 CMP	%EAX,0x48(%RSP)

  (41) 0x527c JE	4f90

  (41) 0x5282 JMP	4fe5

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 26 - 292

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

292:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:292-292
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.25
CQA cycles if no scalar integer	4.25
CQA cycles if FP arith vectorized	4.25
CQA cycles if fully vectorized	0.34
Front-end cycles	4.25
P0 cycles	2.50
P1 cycles	3.25
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	3.00
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	4.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.94
Bytes prefetched	0.00
Bytes loaded	21.00
Bytes stored	17.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.72
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:292-292
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.25
CQA cycles if no scalar integer	4.25
CQA cycles if FP arith vectorized	4.25
CQA cycles if fully vectorized	0.34
Front-end cycles	4.25
P0 cycles	2.50
P1 cycles	3.25
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	3.00
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	4.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.94
Bytes prefetched	0.00
Bytes loaded	21.00
Bytes stored	17.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.72
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-292
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,292.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,292.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.25 to 0.34 cycles (12.36x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 21 bytes. The binary loop is storing 17 bytes.

General properties

nb instructions	17
nb uops	17
loop length	72
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	2.33	2.33	3.00	2.50	2.50	2.33
cycles	2.50	3.25	2.33	2.33	3.00	2.50	2.50	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.25
Dispatch	3.25
Overall L1	4.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	12%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.25 cycles. At this rate:

3% of peak load performance is reached (4.94 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.25 to 3.25 cycles (1.31x speedup).

ASM code

In the binary file, the address of the loop is: 4f5a

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xe0(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV 0x40(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP %EDX,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 5290 <main+0x2db0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
IMUL %EDX,%ESI	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
IMUL %R12D,%EAX	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %RAX,(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
ADD 0x1d8(%RSP),%ESI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %AL	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0x16(%RSP),%AL	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
MOV %AL,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4fb7 <main+0x2ad7>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:26-292
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,292.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,292.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.25 to 0.34 cycles (12.36x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 21 bytes. The binary loop is storing 17 bytes.

General properties

nb instructions	17
nb uops	17
loop length	72
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	2.33	2.33	3.00	2.50	2.50	2.33
cycles	2.50	3.25	2.33	2.33	3.00	2.50	2.50	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.25
Dispatch	3.25
Overall L1	4.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	12%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.25 cycles. At this rate:

3% of peak load performance is reached (4.94 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.25 to 3.25 cycles (1.31x speedup).

ASM code

In the binary file, the address of the loop is: 4f5a

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xe0(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV 0x40(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
CMP %EDX,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 5290 <main+0x2db0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
IMUL %EDX,%ESI	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
IMUL %R12D,%EAX	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %RAX,(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
ADD 0x1d8(%RSP),%ESI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
SETB %AL	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
OR 0x16(%RSP),%AL	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
MOV %AL,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4fb7 <main+0x2ad7>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code