OV - attention-clang-skl256 - Loop 34 - attention-clang-skl256

	Loop Id: 34	Module: attention-clang-skl256	Source: attention_v2.cpp:237-238	Coverage: 0.16%

0x4420 VPMULLQ	%YMM5,%YMM0,%YMM2

0x4426 VMOVUPS	(%RCX,%RDI,4),%XMM3    [2]

0x442b VMOVUPS	0x10(%RCX,%RDI,4),%XMM4    [2]

0x4431 KXNORW	%K0,%K0,%K1

0x4435 VSCATTERQPS	%XMM3,(%RSI,%YMM2,4){%K1}    [1]

0x443c VPMULLQ	%YMM5,%YMM1,%YMM2

0x4442 KXNORW	%K0,%K0,%K1

0x4446 VSCATTERQPS	%XMM4,(%RSI,%YMM2,4){%K1}    [1]

0x444d ADD	$0x8,%RDI

0x4451 VPADDQ	%YMM6,%YMM0,%YMM0

0x4455 VPADDQ	%YMM6,%YMM1,%YMM1

0x4459 CMP	%RDI,%R8

0x445c JNE	4420

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 237 - 238

--------------------------------------------------------------------------------

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.04
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:237-238
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	13.00
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	13.00
CQA cycles if fully vectorized	4.25
Front-end cycles	13.00
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	8.00
P5 cycles	4.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	52.00
Nb loads	2.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.38
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	37.50
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.04
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:237-238
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	13.00
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	13.00
CQA cycles if fully vectorized	4.25
Front-end cycles	13.00
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	8.00
P5 cycles	4.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	52.00
Nb loads	2.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.38
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	37.50
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:237-238.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 37% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238
VSCATTERQPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERQPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	13
nb uops	52
loop length	62
used x86 registers	4
used mmx registers	0
used xmm registers	2
used ymm registers	5
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.00	4.00	5.00	5.00	8.00	4.00	2.00	0.00
cycles	4.00	4.00	5.00	5.00	8.00	4.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.00
Dispatch	8.00
Data deps.	1.00
Overall L1	13.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	37%
load	25%
store	25%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.00 cycles. At this rate:

1% of peak load performance is reached (2.46 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.92 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.00 to 8.00 cycles (1.63x speedup).

ASM code

In the binary file, the address of the loop is: 4420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	Latency	Recip. throughput	Vectorization
VPMULLQ %YMM5,%YMM0,%YMM2	3	1.50	1.50	0	0	0	0	0	15	1.50	vect (50.0%)
VMOVUPS (%RCX,%RDI,4),%XMM3	1	0	0	0.50	0.50	0	0	0	4-5	0.50	vect (25.0%)
VMOVUPS 0x10(%RCX,%RDI,4),%XMM4	1	0	0	0.50	0.50	0	0	0	4-5	0.50	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM3,(%RSI,%YMM2,4){%K1}	19	0	0	2	2	4	1	0	13	9	vect (25.0%)
VPMULLQ %YMM5,%YMM1,%YMM2	3	1.50	1.50	0	0	0	0	0	15	1.50	vect (50.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM4,(%RSI,%YMM2,4){%K1}	19	0	0	2	2	4	1	0	13	9	vect (25.0%)
ADD $0x8,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	1	0.25	N/A
VPADDQ %YMM6,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	1	0.33	vect (50.0%)
VPADDQ %YMM6,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	1	0.33	vect (50.0%)
CMP %RDI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	1	0.25	N/A
JNE 4420 <main+0x1f40>	1	0.50	0	0	0	0	0	0.50	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-clang-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:237-238.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 37% register length (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238
VSCATTERQPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERQPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:238

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	13
nb uops	52
loop length	62
used x86 registers	4
used mmx registers	0
used xmm registers	2
used ymm registers	5
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.00	4.00	5.00	5.00	8.00	4.00	2.00	0.00
cycles	4.00	4.00	5.00	5.00	8.00	4.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.00
Dispatch	8.00
Data deps.	1.00
Overall L1	13.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	37%
load	25%
store	25%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.00 cycles. At this rate:

1% of peak load performance is reached (2.46 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.92 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	Latency	Recip. throughput	Vectorization
VPMULLQ %YMM5,%YMM0,%YMM2	3	1.50	1.50	0	0	0	0	0	15	1.50	vect (50.0%)
VMOVUPS (%RCX,%RDI,4),%XMM3	1	0	0	0.50	0.50	0	0	0	4-5	0.50	vect (25.0%)
VMOVUPS 0x10(%RCX,%RDI,4),%XMM4	1	0	0	0.50	0.50	0	0	0	4-5	0.50	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM3,(%RSI,%YMM2,4){%K1}	19	0	0	2	2	4	1	0	13	9	vect (25.0%)
VPMULLQ %YMM5,%YMM1,%YMM2	3	1.50	1.50	0	0	0	0	0	15	1.50	vect (50.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM4,(%RSI,%YMM2,4){%K1}	19	0	0	2	2	4	1	0	13	9	vect (25.0%)
ADD $0x8,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	1	0.25	N/A
VPADDQ %YMM6,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	1	0.33	vect (50.0%)
VPADDQ %YMM6,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	1	0.33	vect (50.0%)
CMP %RDI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	1	0.25	N/A
JNE 4420 <main+0x1f40>	1	0.50	0	0	0	0	0	0.50	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code