| Loop Id: 33 | Module: attention-clang-skl256 | Source: attention_v2.cpp:30-31 | Coverage: 6.21% |
|---|
| Loop Id: 33 | Module: attention-clang-skl256 | Source: attention_v2.cpp:30-31 | Coverage: 6.21% |
|---|
0x4260 LEA (%RCX,%RDI,1),%R9D |
0x4264 VMOVSS (%R14,%R9,4),%XMM1 [1] |
0x426a VCVTSS2SD %XMM1,%XMM1,%XMM1 |
0x426e MOV %R8D,%R9D |
0x4271 VMOVSS (%RBX,%R9,4),%XMM2 [2] |
0x4277 VCVTSS2SD %XMM2,%XMM2,%XMM2 |
0x427b LEA 0x1(%RCX,%RDI,1),%R9D |
0x4280 VMOVSS (%R14,%R9,4),%XMM3 [1] |
0x4286 VCVTSS2SD %XMM3,%XMM3,%XMM3 |
0x428a LEA (%R12,%R8,1),%R9D |
0x428e VMOVSS (%RBX,%R9,4),%XMM4 [2] |
0x4294 VCVTSS2SD %XMM4,%XMM4,%XMM4 |
0x4298 LEA 0x2(%RCX,%RDI,1),%R9D |
0x429d VMOVSS (%R14,%R9,4),%XMM5 [1] |
0x42a3 VFMADD213SD %XMM0,%XMM1,%XMM2 |
0x42a8 VCVTSS2SD %XMM5,%XMM5,%XMM0 |
0x42ac LEA (%RAX,%R8,1),%R9D |
0x42b0 VMOVSS (%RBX,%R9,4),%XMM1 [2] |
0x42b6 VFMADD213SD %XMM2,%XMM3,%XMM4 |
0x42bb VCVTSS2SD %XMM1,%XMM1,%XMM1 |
0x42bf LEA 0x3(%RCX,%RDI,1),%R9D |
0x42c4 VMOVSS (%R14,%R9,4),%XMM2 [1] |
0x42ca VFMADD213SD %XMM4,%XMM0,%XMM1 |
0x42cf VCVTSS2SD %XMM2,%XMM2,%XMM2 |
0x42d3 LEA (%R11,%R8,1),%R9D |
0x42d7 VMOVSS (%RBX,%R9,4),%XMM0 [2] |
0x42dd VCVTSS2SD %XMM0,%XMM0,%XMM0 |
0x42e1 VFMADD213SD %XMM1,%XMM2,%XMM0 |
0x42e6 ADD $0x4,%RDI |
0x42ea ADD %R13,%R8 |
0x42ed CMP %RDI,%R10 |
0x42f0 JNE 4260 |
/home/eoseret/Applications/llm-attention/attention_v2.cpp: 30 - 31 |
-------------------------------------------------------------------------------- |
30: for (unsigned int k = 0; k < K; ++k) { //vectorized |
31: sum += (double)A[i * K + k] * (double)B[k * N + j]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-clang-skl256 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.78 |
| CQA speedup if fully vectorized | 14.22 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.64 |
| Bottlenecks | |
| Function | main |
| Source | attention_v2.cpp:30-31 |
| Source loop unroll info | unrolled by 16 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | intermediate |
| Unroll factor | 4 |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 9.00 |
| CQA cycles if fully vectorized | 1.13 |
| Front-end cycles | 9.75 |
| P0 cycles | 9.50 |
| P1 cycles | 9.00 |
| P2 cycles | 4.00 |
| P3 cycles | 4.00 |
| P4 cycles | 0.00 |
| P5 cycles | 8.50 |
| P6 cycles | 3.00 |
| P7 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 16 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 32.00 |
| Nb uops | 39.00 |
| Nb loads | 8.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.50 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 2.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 32.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 1.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 7.50 |
| Vector-efficiency ratio load | 6.25 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 6.25 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.78 |
| CQA speedup if fully vectorized | 14.22 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.64 |
| Bottlenecks | |
| Function | main |
| Source | attention_v2.cpp:30-31 |
| Source loop unroll info | unrolled by 16 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | intermediate |
| Unroll factor | 4 |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 9.00 |
| CQA cycles if fully vectorized | 1.13 |
| Front-end cycles | 9.75 |
| P0 cycles | 9.50 |
| P1 cycles | 9.00 |
| P2 cycles | 4.00 |
| P3 cycles | 4.00 |
| P4 cycles | 0.00 |
| P5 cycles | 8.50 |
| P6 cycles | 3.00 |
| P7 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 16 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 32.00 |
| Nb uops | 39.00 |
| Nb loads | 8.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.50 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 2.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 32.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 1.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 7.50 |
| Vector-efficiency ratio load | 6.25 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 6.25 |
| Path / |
| Function | main |
| Source file and lines | attention_v2.cpp:30-31 |
| Module | attention-clang-skl256 |
| nb instructions | 32 |
| nb uops | 39 |
| loop length | 150 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 6 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 9.75 cycles |
| front end | 9.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 9.50 | 9.00 | 4.00 | 4.00 | 0.00 | 8.50 | 3.00 | 0.00 |
| cycles | 9.50 | 9.00 | 4.00 | 4.00 | 0.00 | 8.50 | 3.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 16.00 |
| Front-end | 9.75 |
| Dispatch | 9.50 |
| Data deps. | 16.00 |
| Overall L1 | 16.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 7% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LEA (%RCX,%RDI,1),%R9D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VMOVSS (%R14,%R9,4),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM1,%XMM1,%XMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| MOV %R8D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| VMOVSS (%RBX,%R9,4),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM2,%XMM2,%XMM2 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA 0x1(%RCX,%RDI,1),%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS (%R14,%R9,4),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM3,%XMM3,%XMM3 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA (%R12,%R8,1),%R9D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VMOVSS (%RBX,%R9,4),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM4,%XMM4,%XMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA 0x2(%RCX,%RDI,1),%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS (%R14,%R9,4),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM0,%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM5,%XMM5,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA (%RAX,%R8,1),%R9D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VMOVSS (%RBX,%R9,4),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM2,%XMM3,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM1,%XMM1,%XMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA 0x3(%RCX,%RDI,1),%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS (%R14,%R9,4),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM4,%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM2,%XMM2,%XMM2 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA (%R11,%R8,1),%R9D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VMOVSS (%RBX,%R9,4),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM0,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| VFMADD213SD %XMM1,%XMM2,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| ADD $0x4,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| ADD %R13,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| CMP %RDI,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JNE 4260 <main+0x1d80> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| Function | main |
| Source file and lines | attention_v2.cpp:30-31 |
| Module | attention-clang-skl256 |
| nb instructions | 32 |
| nb uops | 39 |
| loop length | 150 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 6 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 9.75 cycles |
| front end | 9.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 9.50 | 9.00 | 4.00 | 4.00 | 0.00 | 8.50 | 3.00 | 0.00 |
| cycles | 9.50 | 9.00 | 4.00 | 4.00 | 0.00 | 8.50 | 3.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 16.00 |
| Front-end | 9.75 |
| Dispatch | 9.50 |
| Data deps. | 16.00 |
| Overall L1 | 16.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 7% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LEA (%RCX,%RDI,1),%R9D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VMOVSS (%R14,%R9,4),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM1,%XMM1,%XMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| MOV %R8D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| VMOVSS (%RBX,%R9,4),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM2,%XMM2,%XMM2 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA 0x1(%RCX,%RDI,1),%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS (%R14,%R9,4),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM3,%XMM3,%XMM3 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA (%R12,%R8,1),%R9D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VMOVSS (%RBX,%R9,4),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM4,%XMM4,%XMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA 0x2(%RCX,%RDI,1),%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS (%R14,%R9,4),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM0,%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM5,%XMM5,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA (%RAX,%R8,1),%R9D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VMOVSS (%RBX,%R9,4),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM2,%XMM3,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM1,%XMM1,%XMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA 0x3(%RCX,%RDI,1),%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS (%R14,%R9,4),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM4,%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM2,%XMM2,%XMM2 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| LEA (%R11,%R8,1),%R9D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VMOVSS (%RBX,%R9,4),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM0,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (6.3%) |
| VFMADD213SD %XMM1,%XMM2,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| ADD $0x4,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| ADD %R13,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| CMP %RDI,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JNE 4260 <main+0x1d80> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
