OV - attention-gcc-skl512 - Loop 36

    (34) 0x2ea0 MOV	-0x40(%RBP),%EDI

    (34) 0x2ea3 MOV	-0x40(%RBP),%R8D

    (34) 0x2ea7 MOV	%R14,%RAX

    (34) 0x2eaa SHR	$0x4,%EDI

    (34) 0x2ead MOV	%EDI,%ESI

    (34) 0x2eaf SAL	$0x6,%RSI

    (34) 0x2eb3 ADD	%R14,%RSI

    (34) 0x2eb6 NOPW	%CS:(%RAX,%RAX,1)

      (33) 0x2ec0 VMAXPS	(%RAX),%ZMM0,%ZMM0

      (33) 0x2ec6 ADD	$0x40,%RAX

      (33) 0x2eca CMP	%RAX,%RSI

      (33) 0x2ecd JNE	2ec0

    (34) 0x2ecf VEXTRACTF32X8	$0x1,%ZMM0,%YMM3

    (34) 0x2ed6 VMOVAPS	%YMM0,%YMM1

    (34) 0x2eda MOV	%EDI,%EAX

    (34) 0x2edc VMAXPS	%YMM0,%YMM3,%YMM2

    (34) 0x2ee0 SAL	$0x4,%EAX

    (34) 0x2ee3 VEXTRACTF32X4	$0x1,%YMM2,%XMM0

    (34) 0x2eea VMAXPS	%XMM2,%XMM0,%XMM0

    (34) 0x2eee VMOVHLPS	%XMM0,%XMM0,%XMM2

    (34) 0x2ef2 VMAXPS	%XMM0,%XMM2,%XMM2

    (34) 0x2ef6 VSHUFPS	$0x55,%XMM2,%XMM2,%XMM0

    (34) 0x2efb VMAXPS	%XMM2,%XMM0,%XMM0

    (34) 0x2eff CMP	%R8D,%EAX

    (34) 0x2f02 JE	2fb2

  (35) 0x2f08 VMAXPS	%YMM3,%YMM1,%YMM1

  (35) 0x2f0c MOV	%EAX,%ESI

  (35) 0x2f0e MOV	%R15D,%EDI

  (35) 0x2f11 SUB	%EAX,%EDI

  (35) 0x2f13 CMP	$0x6,%EDI

  (35) 0x2f16 JBE	2f52

  (35) 0x2f18 MOV	-0x88(%RBP),%RDX

  (35) 0x2f1f ADD	-0x48(%RBP),%RAX

  (35) 0x2f23 INC	%EDI

  (35) 0x2f25 VMAXPS	(%RDX,%RAX,4),%YMM1,%YMM1

  (35) 0x2f2a MOV	%EDI,%EAX

  (35) 0x2f2c AND	$-0x8,%EAX

  (35) 0x2f2f AND	$0x7,%EDI

  (35) 0x2f32 VEXTRACTF32X4	$0x1,%YMM1,%XMM0

  (35) 0x2f39 VMAXPS	%XMM1,%XMM0,%XMM0

  (35) 0x2f3d VMOVHLPS	%XMM0,%XMM0,%XMM1

  (35) 0x2f41 VMAXPS	%XMM0,%XMM1,%XMM1

  (35) 0x2f45 VSHUFPS	$0x55,%XMM1,%XMM1,%XMM0

  (35) 0x2f4a VMAXPS	%XMM1,%XMM0,%XMM0

  (35) 0x2f4e JE	2fb2

  (35) 0x2f50 ADD	%EAX,%ESI

  (35) 0x2f52 MOVSXD	%ESI,%RAX

  (35) 0x2f55 VMAXSS	(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f5b CMP	%ESI,%R15D

  (35) 0x2f5e JLE	2fb2

  (35) 0x2f60 LEA	0x2(%RSI),%EDI

  (35) 0x2f63 VMAXSS	0x4(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f6a CMP	%EDI,%R15D

  (35) 0x2f6d JL	2fb2

  (35) 0x2f6f LEA	0x3(%RSI),%EDI

  (35) 0x2f72 VMAXSS	0x8(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f79 CMP	%EDI,%R15D

  (35) 0x2f7c JL	2fb2

  (35) 0x2f7e LEA	0x4(%RSI),%EDI

  (35) 0x2f81 VMAXSS	0xc(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f88 CMP	%EDI,%R15D

  (35) 0x2f8b JL	2fb2

  (35) 0x2f8d LEA	0x5(%RSI),%EDI

  (35) 0x2f90 VMAXSS	0x10(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f97 CMP	%R15D,%EDI

  (35) 0x2f9a JG	2fb2

  (35) 0x2f9c ADD	$0x6,%ESI

  (35) 0x2f9f VMAXSS	0x14(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2fa6 CMP	%ESI,%R15D

  (35) 0x2fa9 JL	2fb2

  (35) 0x2fab VMAXSS	0x18(%R14,%RAX,4),%XMM0,%XMM0

    (34) 0x2fb2 MOVL	$0,-0x34(%RBP)

    (34) 0x2fb9 MOV	%R14,%R12

    (34) 0x2fbc VMOVSS	%XMM0,-0x38(%RBP)

    (34) 0x2fc1 VZEROUPPER

    (34) 0x2fc4 NOPL	(%RAX)

      (31) 0x2fc8 VMOVSS	(%R12),%XMM1

      (31) 0x2fce ADD	$0x4,%R12

      (31) 0x2fd2 VSUBSS	-0x38(%RBP),%XMM1,%XMM0

      (31) 0x2fd7 CALL	1110 <expf@plt>

      (31) 0x2fdc VADDSS	-0x34(%RBP),%XMM0,%XMM5

      (31) 0x2fe1 VMOVSS	%XMM5,-0x34(%RBP)

      (31) 0x2fe6 CMP	%R12,%RBX

      (31) 0x2fe9 JNE	2fc8

    (34) 0x2feb MOV	-0x60(%RBP),%RAX

    (34) 0x2fef MOV	-0x48(%RBP),%RCX

    (34) 0x2ff3 MOV	%R14,%R13

    (34) 0x2ff6 LEA	(%RAX,%RCX,4),%R12

    (34) 0x2ffa NOPW	(%RAX,%RAX,1)

      (32) 0x3000 VMOVSS	(%R13),%XMM1

      (32) 0x3006 ADD	$0x4,%R13

      (32) 0x300a ADD	$0x4,%R12

      (32) 0x300e VSUBSS	-0x38(%RBP),%XMM1,%XMM0

      (32) 0x3013 CALL	1110 <expf@plt>

      (32) 0x3018 VDIVSS	-0x34(%RBP),%XMM0,%XMM0

      (32) 0x301d VMOVSS	%XMM0,-0x4(%R12)

      (32) 0x3024 CMP	%R13,%RBX

      (32) 0x3027 JNE	3000

    (34) 0x3029 MOV	-0x54(%RBP),%EDX

    (34) 0x302c LEA	0x1(%R15),%R8D

    (34) 0x3030 CMP	%R8D,%EDX

    (34) 0x3033 JE	30c0

    (34) 0x3039 INCQ	-0x40(%RBP)

    (34) 0x303d MOV	-0x80(%RBP),%RSI

    (34) 0x3041 MOV	%EDX,%EAX

    (34) 0x3043 MOV	-0x50(%RBP),%R13

    (34) 0x3047 MOV	-0x78(%RBP),%R12

    (34) 0x304b MOV	%R8D,-0x38(%RBP)

    (34) 0x304f ADD	%RSI,-0x48(%RBP)

    (34) 0x3053 XOR	%ESI,%ESI

    (34) 0x3055 ADD	-0x70(%RBP),%R14

    (34) 0x3059 MOV	%R13,%RDI

    (34) 0x305c ADD	%R12,%R13

    (34) 0x305f ADD	%R12,%RBX

    (34) 0x3062 MOV	-0x40(%RBP),%R15

    (34) 0x3066 SUB	%R15D,%EAX

    (34) 0x3069 LEA	0x4(,%RAX,4),%RDX

    (34) 0x3071 CALL	1050 <memset@plt>

    (34) 0x3076 MOV	-0x68(%RBP),%RAX

    (34) 0x307a VMOVSS	-0x34(%RBP),%XMM2

    (34) 0x307f MOV	%R13,-0x50(%RBP)

    (34) 0x3083 VBROADCASTSS	0xf77(%RIP),%ZMM0

    (34) 0x308d VMOVSS	%XMM2,-0x8(%RAX,%R15,4)

    (34) 0x3094 MOV	-0x38(%RBP),%R15D

    (34) 0x3098 CMP	$0xe,%R15D

    (34) 0x309c JG	2ea0

0x30a2 VMOVAPS	%YMM0,%YMM1

0x30a6 XOR	%EAX,%EAX

0x30a8 VMOVSS	0xf54(%RIP),%XMM0

0x30b0 XOR	%ESI,%ESI

0x30b2 JMP	2f0e

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Source Location	Module
►100.00+	main	attention_v2.cpp:283	attention-gcc-skl512
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:183	attention-gcc-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:43-43,attention_v2.cpp:46-47
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.25
CQA cycles if no scalar integer	0.50
CQA cycles if FP arith vectorized	1.25
CQA cycles if fully vectorized	0.08
Front-end cycles	1.25
P0 cycles	0.00
P1 cycles	0.00
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.20
Bytes prefetched	0.00
Bytes loaded	4.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	17.19
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:43-43,attention_v2.cpp:46-47
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.25
CQA cycles if no scalar integer	0.50
CQA cycles if FP arith vectorized	1.25
CQA cycles if fully vectorized	0.08
Front-end cycles	1.25
P0 cycles	0.00
P1 cycles	0.00
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.20
Bytes prefetched	0.00
Bytes loaded	4.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	17.19
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43,46-47.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.25 to 0.50 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 4 bytes.

General properties

nb instructions	5
nb uops	5
loop length	21
used x86 registers	2
used mmx registers	0
used xmm registers	1
used ymm registers	2
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.25 cycles
front end	1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	0.00	0.00	0.50	0.50	0.00	0.00	1.00	0.00
cycles	0.00	0.00	0.50	0.50	0.00	0.00	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.25
Dispatch	1.00
Overall L1	1.25

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

FP

all	28%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	17%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles. At this rate:

2% of peak load performance is reached (3.20 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.25 to 1.00 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 30a2

Instruction	Nb FU	P2	P3	P6	Latency	Recip. throughput	Vectorization
VMOVAPS %YMM0,%YMM1	1	0	0	0	0	0.25	vect (50.0%)
XOR %EAX,%EAX	1	0	0	0	0	0.25	scal (6.3%)
VMOVSS 0xf54(%RIP),%XMM0	1	0.50	0.50	0	4-5	0.50	scal (6.3%)
XOR %ESI,%ESI	1	0	0	0	0	0.25	scal (6.3%)
JMP 2f0e <_Z7softmaxPKfPfS1_i+0xfe>	1	0	0	1	0	1-2	N/A

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43,46-47.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.25 to 0.50 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 4 bytes.

General properties

nb instructions	5
nb uops	5
loop length	21
used x86 registers	2
used mmx registers	0
used xmm registers	1
used ymm registers	2
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.25 cycles
front end	1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	0.00	0.00	0.50	0.50	0.00	0.00	1.00	0.00
cycles	0.00	0.00	0.50	0.50	0.00	0.00	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.25
Dispatch	1.00
Overall L1	1.25

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

FP

all	28%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	17%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles. At this rate:

2% of peak load performance is reached (3.20 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.25 to 1.00 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 30a2

Instruction	Nb FU	P2	P3	P6	Latency	Recip. throughput	Vectorization
VMOVAPS %YMM0,%YMM1	1	0	0	0	0	0.25	vect (50.0%)
XOR %EAX,%EAX	1	0	0	0	0	0.25	scal (6.3%)
VMOVSS 0xf54(%RIP),%XMM0	1	0.50	0.50	0	4-5	0.50	scal (6.3%)
XOR %ESI,%ESI	1	0	0	0	0	0.25	scal (6.3%)
JMP 2f0e <_Z7softmaxPKfPfS1_i+0xfe>	1	0	0	1	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code