OV - attention-gcc-skl512 - Loop 3 - attention-gcc-skl512

	Loop Id: 3	Module: attention-gcc-skl512	Source: random.tcc:404-3558 [...]	Coverage: 0.29%

0x1ad0 LEA	0x1(%RDX),%RAX

0x1ad4 MOV	-0x2770(%RBP,%RDX,8),%RDX

0x1adc MOV	%RAX,-0x13f0(%RBP)

0x1ae3 MOV	%RDX,%RSI

0x1ae6 SHR	$0xb,%RSI

0x1aea MOV	%ESI,%ESI

0x1aec XOR	%RSI,%RDX

0x1aef MOV	%RDX,%RSI

0x1af2 SAL	$0x7,%RSI

0x1af6 AND	$-0x62d3a980,%ESI

0x1afc XOR	%RSI,%RDX

0x1aff MOV	%RDX,%RSI

0x1b02 SAL	$0xf,%RSI

0x1b06 AND	$-0x103a0000,%ESI

0x1b0c XOR	%RSI,%RDX

0x1b0f MOV	%RDX,%RSI

0x1b12 SHR	$0x12,%RSI

0x1b16 XOR	%RSI,%RDX

0x1b19 VCVTUSI2SS	%EDX,%XMM1,%XMM0

0x1b1f VMULSS	0x24e1(%RIP),%XMM0,%XMM0

0x1b27 VCOMISS	%XMM0,%XMM3

0x1b2b JA	1b9f

0x1b2d MOV	%RAX,%RDX

0x1b30 CMP	$0x26f,%RAX

0x1b36 JBE	1ad0

0x1b38 MOV	%R8,-0x2830(%RBP)

0x1b3f LEA	-0x2770(%RBP),%RDI

0x1b46 MOV	%R9,-0x2820(%RBP)

0x1b4d MOV	%RCX,-0x2810(%RBP)

0x1b54 VMOVAPS	%XMM1,-0x2800(%RBP)

0x1b5c VZEROUPPER

0x1b5f CALL	36c0 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

0x1b64 MOV	-0x13f0(%RBP),%RDX

0x1b6b MOV	-0x2830(%RBP),%R8

0x1b72 MOV	-0x2820(%RBP),%R9

0x1b79 MOV	-0x2810(%RBP),%RCX

0x1b80 VMOVAPS	-0x2800(%RBP),%XMM1

0x1b88 VMOVSS	0x247c(%RIP),%XMM3

0x1b90 VMOVDQA64	0x26a6(%RIP),%ZMM7

0x1b9a JMP	1ad0

0x1b9f MOV	-0x2850(%RBP),%RDI

0x1ba6 MOV	%RCX,-0x2810(%RBP)

0x1bad MOV	%R9,-0x2820(%RBP)

0x1bb4 MOV	%R8,-0x2830(%RBP)

0x1bbb VMOVSS	%XMM0,(%RDI)

0x1bbf JMP	1c25

  (26) 0x1bc8 LEA	0x1(%RDX),%RAX

  (26) 0x1bcc MOV	-0x2770(%RBP,%RDX,8),%RDX

  (26) 0x1bd4 MOV	%RAX,-0x13f0(%RBP)

  (26) 0x1bdb MOV	%RDX,%RCX

  (26) 0x1bde SHR	$0xb,%RCX

  (26) 0x1be2 MOV	%ECX,%ECX

  (26) 0x1be4 XOR	%RCX,%RDX

  (26) 0x1be7 MOV	%RDX,%RCX

  (26) 0x1bea SAL	$0x7,%RCX

  (26) 0x1bee AND	$-0x62d3a980,%ECX

  (26) 0x1bf4 XOR	%RCX,%RDX

  (26) 0x1bf7 MOV	%RDX,%RCX

  (26) 0x1bfa SAL	$0xf,%RCX

  (26) 0x1bfe AND	$-0x103a0000,%ECX

  (26) 0x1c04 XOR	%RCX,%RDX

  (26) 0x1c07 MOV	%RDX,%RCX

  (26) 0x1c0a SHR	$0x12,%RCX

  (26) 0x1c0e XOR	%RCX,%RDX

  (26) 0x1c11 VCVTUSI2SS	%EDX,%XMM1,%XMM0

  (26) 0x1c17 VMULSS	0x23e9(%RIP),%XMM0,%XMM0

  (26) 0x1c1f VCOMISS	%XMM0,%XMM3

  (26) 0x1c23 JA	1c6d

  (26) 0x1c25 MOV	%RAX,%RDX

  (26) 0x1c28 CMP	$0x26f,%RAX

  (26) 0x1c2e JBE	1bc8

  (26) 0x1c30 VMOVAPS	%XMM1,-0x2800(%RBP)

  (26) 0x1c38 LEA	-0x2770(%RBP),%RDI

  (26) 0x1c3f VZEROUPPER

  (26) 0x1c42 CALL	36c0 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

  (26) 0x1c47 MOV	-0x13f0(%RBP),%RDX

  (26) 0x1c4e VMOVAPS	-0x2800(%RBP),%XMM1

  (26) 0x1c56 VMOVSS	0x23ae(%RIP),%XMM3

  (26) 0x1c5e VMOVDQA64	0x25d8(%RIP),%ZMM7

  (26) 0x1c68 JMP	1bc8

0x1c6d MOV	$0x1,%EDX

0x1c72 MOV	-0x2840(%RBP),%RDI

0x1c79 MOV	-0x2810(%RBP),%RCX

0x1c80 VPBROADCASTQ	%RDX,%ZMM8

0x1c86 MOV	$-0x80000000,%RDX

0x1c8d MOV	-0x2820(%RBP),%R9

0x1c94 MOV	-0x2830(%RBP),%R8

0x1c9b VPBROADCASTQ	%RDX,%ZMM9

0x1ca1 MOV	$0x7fffffff,%EDX

0x1ca6 VMOVSS	%XMM0,(%RDI)

0x1caa VMOVDQA64	%ZMM8,%ZMM4

0x1cb0 VPBROADCASTQ	%RDX,%ZMM10

0x1cb6 VMOVDQA64	%ZMM9,%ZMM5

0x1cbc VMOVDQA64	%ZMM10,%ZMM6

0x1cc2 VMOVDQA	%XMM10,%XMM11

0x1cc7 JMP	1d29

  (23) 0x1cd0 MOV	-0x2770(%RBP,%RAX,8),%RSI

  (23) 0x1cd8 INC	%RAX

  (23) 0x1cdb MOV	%RSI,%RDX

  (23) 0x1cde SHR	$0xb,%RDX

  (23) 0x1ce2 MOV	%EDX,%EDX

  (23) 0x1ce4 XOR	%RSI,%RDX

  (23) 0x1ce7 MOV	%RDX,%RSI

  (23) 0x1cea SAL	$0x7,%RSI

  (23) 0x1cee AND	$-0x62d3a980,%ESI

  (23) 0x1cf4 XOR	%RSI,%RDX

  (23) 0x1cf7 MOV	%RDX,%RSI

  (23) 0x1cfa SAL	$0xf,%RSI

  (23) 0x1cfe AND	$-0x103a0000,%ESI

  (23) 0x1d04 XOR	%RSI,%RDX

  (23) 0x1d07 MOV	%RDX,%RSI

  (23) 0x1d0a SHR	$0x12,%RSI

  (23) 0x1d0e XOR	%RSI,%RDX

  (23) 0x1d11 VCVTUSI2SS	%EDX,%XMM1,%XMM0

  (23) 0x1d17 VMULSS	0x22e9(%RIP),%XMM0,%XMM0

  (23) 0x1d1f VCOMISS	%XMM0,%XMM3

  (23) 0x1d23 JA	1eea

  (23) 0x1d29 CMP	$0x26f,%RAX

  (23) 0x1d2f JBE	1cd0

  (23) 0x1d31 LEA	-0x2770(%RBP),%RAX

  (23) 0x1d38 NOPL	(%RAX,%RAX,1)

    (24) 0x1d40 VPANDQ	(%RAX),%ZMM5,%ZMM2

    (24) 0x1d46 VMOVDQA64	%ZMM6,%ZMM0

    (24) 0x1d4c ADD	$0x40,%RAX

    (24) 0x1d50 VPTERNLOGQ	$-0x14,-0x38(%RAX),%ZMM2,%ZMM0

    (24) 0x1d5b VPSRLQ	$0x1,%ZMM0,%ZMM2

    (24) 0x1d62 VPANDQ	%ZMM4,%ZMM0,%ZMM0

    (24) 0x1d68 VPMULLQ	%ZMM7,%ZMM0,%ZMM0

    (24) 0x1d6e VPTERNLOGQ	$-0x6a,0xc28(%RAX),%ZMM0,%ZMM2

    (24) 0x1d79 VMOVDQA64	%ZMM2,-0x40(%RAX)

    (24) 0x1d80 CMP	%RAX,%RBX

    (24) 0x1d83 JNE	1d40

  (23) 0x1d85 MOV	-0x2060(%RBP),%RDX

  (23) 0x1d8c MOV	-0x2058(%RBP),%RAX

  (23) 0x1d93 VMOVDQA	%XMM11,%XMM0

  (23) 0x1d97 VPANDQ	-0x2070(%RBP),%XMM9,%XMM2

  (23) 0x1da1 AND	$-0x80000000,%RDX

  (23) 0x1da8 AND	$0x7fffffff,%EAX

  (23) 0x1dad OR	%RDX,%RAX

  (23) 0x1db0 VPTERNLOGQ	$-0x14,-0x2068(%RBP),%XMM2,%XMM0

  (23) 0x1dbb MOV	%RAX,%RDX

  (23) 0x1dbe VPSRLQ	$0x1,%XMM0,%XMM2

  (23) 0x1dc3 VPANDQ	%XMM8,%XMM0,%XMM0

  (23) 0x1dc9 AND	$0x1,%EAX

  (23) 0x1dcc SHR	$0x1,%RDX

  (23) 0x1dcf NEG	%RAX

  (23) 0x1dd2 VPMULLQ	-0x27f0(%RBP),%XMM0,%XMM0

  (23) 0x1ddc VPTERNLOGQ	$-0x6a,-0x1408(%RBP),%XMM0,%XMM2

  (23) 0x1de7 XOR	-0x13f8(%RBP),%RDX

  (23) 0x1dee AND	$-0x66f74f21,%EAX

  (23) 0x1df3 VMOVDQA	%XMM2,-0x2070(%RBP)

  (23) 0x1dfb XOR	%RDX,%RAX

  (23) 0x1dfe LEA	-0x1418(%RBP),%RDX

  (23) 0x1e05 MOV	%RAX,-0x2060(%RBP)

  (23) 0x1e0c LEA	-0x2058(%RBP),%RAX

  (23) 0x1e13 NOPL	(%RAX,%RAX,1)

    (25) 0x1e18 VPANDQ	(%RAX),%ZMM5,%ZMM2

    (25) 0x1e1e VMOVDQA64	%ZMM6,%ZMM0

    (25) 0x1e24 ADD	$0x40,%RAX

    (25) 0x1e28 VPTERNLOGQ	$-0x14,-0x38(%RAX),%ZMM2,%ZMM0

    (25) 0x1e33 VPSRLQ	$0x1,%ZMM0,%ZMM2

    (25) 0x1e3a VPANDQ	%ZMM4,%ZMM0,%ZMM0

    (25) 0x1e40 VPMULLQ	%ZMM7,%ZMM0,%ZMM0

    (25) 0x1e46 VPTERNLOGQ	$-0x6a,-0x758(%RAX),%ZMM0,%ZMM2

    (25) 0x1e51 VMOVDQU64	%ZMM2,-0x40(%RAX)

    (25) 0x1e58 CMP	%RAX,%RDX

    (25) 0x1e5b JNE	1e18

  (23) 0x1e5d MOV	-0x2770(%RBP),%RSI

  (23) 0x1e64 MOV	-0x13f8(%RBP),%RAX

  (23) 0x1e6b VMOVDQA	%YMM10,%YMM0

  (23) 0x1e6f VPANDQ	-0x1418(%RBP),%YMM9,%YMM2

  (23) 0x1e79 MOV	%RSI,%RDX

  (23) 0x1e7c AND	$-0x80000000,%RAX

  (23) 0x1e82 AND	$0x7fffffff,%EDX

  (23) 0x1e88 VPTERNLOGQ	$-0x14,-0x1410(%RBP),%YMM2,%YMM0

  (23) 0x1e93 OR	%RDX,%RAX

  (23) 0x1e96 VPSRLQ	$0x1,%YMM0,%YMM2

  (23) 0x1e9b VPANDQ	%YMM8,%YMM0,%YMM0

  (23) 0x1ea1 MOV	%RAX,%RDX

  (23) 0x1ea4 AND	$0x1,%EAX

  (23) 0x1ea7 VPMULLQ	-0x27f0(%RBP),%YMM0,%YMM0

  (23) 0x1eb1 VPTERNLOGQ	$-0x6a,-0x1b30(%RBP),%YMM0,%YMM2

  (23) 0x1ebc SHR	$0x1,%RDX

  (23) 0x1ebf NEG	%RAX

  (23) 0x1ec2 VMOVDQU	%YMM2,-0x1418(%RBP)

  (23) 0x1eca XOR	-0x1b10(%RBP),%RDX

  (23) 0x1ed1 AND	$-0x66f74f21,%EAX

  (23) 0x1ed6 XOR	%RDX,%RAX

  (23) 0x1ed9 MOV	%RAX,-0x13f8(%RBP)

  (23) 0x1ee0 MOV	$0x1,%EAX

  (23) 0x1ee5 JMP	1cdb

0x1eea MOV	-0x2858(%RBP),%RDI

0x1ef1 ADDQ	$0x4,-0x2840(%RBP)

0x1ef9 ADDQ	$0x4,-0x2850(%RBP)

0x1f01 VMOVSS	%XMM0,(%RDI)

0x1f05 ADD	$0x4,%RDI

0x1f09 MOV	%RAX,-0x13f0(%RBP)

0x1f10 MOV	%RDI,-0x2858(%RBP)

0x1f17 CMP	%RDI,-0x2890(%RBP)

0x1f1e JNE	1b2d

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

/usr/include/c++/16.1.1/bits/random.tcc: 404 - 3558

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3519:     __generate_canonical_pow2(_Urbg& __urng)

[...]

3557: 	  const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd);

3558: 	  if (__ret < _RealT(1.0))

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:183	attention-gcc-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.57
CQA speedup if FP arith vectorized	1.28
CQA speedup if fully vectorized	1.85
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:164-167,random.tcc:406-409,random.tcc:458-459,random.tcc:462-466,random.tcc:3519-3519,random.tcc:3557-3558
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.25
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	15.06
CQA cycles if fully vectorized	10.42
Front-end cycles	19.25
P0 cycles	8.25
P1 cycles	8.25
P2 cycles	11.33
P3 cycles	11.33
P4 cycles	16.00
P5 cycles	8.25
P6 cycles	8.25
P7 cycles	11.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	77.00
Nb loads	18.00
Nb stores	15.00
Nb stack references	10.00
FLOP/cycle	0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.42
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	116.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	17.02
Vectorization ratio load	16.67
Vectorization ratio store	6.67
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	22.73
Vector-efficiency ratio all	19.68
Vector-efficiency ratio load	19.79
Vector-efficiency ratio store	12.08
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	24.15

Metric	Value
CQA speedup if no scalar integer	2.57
CQA speedup if FP arith vectorized	1.28
CQA speedup if fully vectorized	1.85
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:164-167,random.tcc:406-409,random.tcc:458-459,random.tcc:462-466,random.tcc:3519-3519,random.tcc:3557-3558
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.25
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	15.06
CQA cycles if fully vectorized	10.42
Front-end cycles	19.25
P0 cycles	8.25
P1 cycles	8.25
P2 cycles	11.33
P3 cycles	11.33
P4 cycles	16.00
P5 cycles	8.25
P6 cycles	8.25
P7 cycles	11.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	77.00
Nb loads	18.00
Nb stores	15.00
Nb stack references	10.00
FLOP/cycle	0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.42
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	116.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	17.02
Vectorization ratio load	16.67
Vectorization ratio store	6.67
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	22.73
Vector-efficiency ratio all	19.68
Vector-efficiency ratio load	19.79
Vector-efficiency ratio store	12.08
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	24.15

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-gcc-skl512

The loop is defined in:

/home/eoseret/Applications/llm-attention/attention_v2.cpp:164-167
/usr/include/c++/16.1.1/bits/random.tcc:404-423,458-466,3519,3557-3558

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.25 to 7.50 cycles (2.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 19.25 to 10.42 cycles (1.85x speedup).

Details

17% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
6% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
22% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

std::mersenne_twister_engine
::_M_gen_rand(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:164
VCVTUSI2SS: 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557
VZEROUPPER: 1 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 200 bytes (50 single precision FP elements). The binary loop is storing 116 bytes (29 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	71
nb uops	77
loop length	391
used x86 registers	8
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	7
nb stack references	10

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	19.25 cycles
front end	19.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	8.25	8.25	11.33	11.33	16.00	8.25	8.25	11.33
cycles	8.25	8.25	11.33	11.33	16.00	8.25	8.25	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.25
Dispatch	16.00
Overall L1	19.25

Vectorization ratios

INT

all	15%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	33%
store	25%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	17%
load	16%
store	6%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	21%
load	22%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	10%
load	12%
store	10%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	19%
load	19%
store	12%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.25 cycles. At this rate:

8% of peak load performance is reached (10.39 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (6.03 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.25 to 16.00 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 1b2d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV -0x2770(%RBP,%RDX,8),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RAX,-0x13f0(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0x7,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x62d3a980,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0xf,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x103a0000,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VCVTUSI2SS %EDX,%XMM1,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS 0x24e1(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM0,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (6.3%)
JA 1b9f <main+0x85f>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x26f,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JBE 1ad0 <main+0x790>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R8,-0x2830(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA -0x2770(%RBP),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %R9,-0x2820(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,-0x2810(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
VMOVAPS %XMM1,-0x2800(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 36c0 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV -0x13f0(%RBP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x2830(%RBP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x2820(%RBP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x2810(%RBP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VMOVAPS -0x2800(%RBP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VMOVSS 0x247c(%RIP),%XMM3	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVDQA64 0x26a6(%RIP),%ZMM7	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
JMP 1ad0 <main+0x790>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV -0x2850(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RCX,-0x2810(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %R9,-0x2820(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %R8,-0x2830(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
VMOVSS %XMM0,(%RDI)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
JMP 1c25 <main+0x8e5>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV -0x2840(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x2810(%RBP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%ZMM8	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
MOV $-0x80000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV -0x2820(%RBP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x2830(%RBP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%ZMM9	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
MOV $0x7fffffff,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVSS %XMM0,(%RDI)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VMOVDQA64 %ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VPBROADCASTQ %RDX,%ZMM10	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VMOVDQA64 %ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVDQA64 %ZMM10,%ZMM6	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVDQA %XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 1d29 <main+0x9e9>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV -0x2858(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADDQ $0x4,-0x2840(%RBP)	2	0.25	0.25	0.83	0.83	1	0.25	0.25	0.33	5	1	scal (12.5%)
ADDQ $0x4,-0x2850(%RBP)	2	0.25	0.25	0.83	0.83	1	0.25	0.25	0.33	5	1	scal (12.5%)
VMOVSS %XMM0,(%RDI)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD $0x4,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,-0x13f0(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,-0x2858(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
CMP %RDI,-0x2890(%RBP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 1b2d <main+0x7ed>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-gcc-skl512

The loop is defined in:

/home/eoseret/Applications/llm-attention/attention_v2.cpp:164-167
/usr/include/c++/16.1.1/bits/random.tcc:404-423,458-466,3519,3557-3558

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.25 to 7.50 cycles (2.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

17% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
6% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
22% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

std::mersenne_twister_engine
::_M_gen_rand(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:164
VCVTUSI2SS: 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557
VZEROUPPER: 1 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 200 bytes (50 single precision FP elements). The binary loop is storing 116 bytes (29 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	71
nb uops	77
loop length	391
used x86 registers	8
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	7
nb stack references	10

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	19.25 cycles
front end	19.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	8.25	8.25	11.33	11.33	16.00	8.25	8.25	11.33
cycles	8.25	8.25	11.33	11.33	16.00	8.25	8.25	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.25
Dispatch	16.00
Overall L1	19.25

Vectorization ratios

INT

all	15%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	33%
store	25%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	17%
load	16%
store	6%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	21%
load	22%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	10%
load	12%
store	10%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	19%
load	19%
store	12%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.25 cycles. At this rate:

8% of peak load performance is reached (10.39 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (6.03 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 1b2d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV -0x2770(%RBP,%RDX,8),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RAX,-0x13f0(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0x7,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x62d3a980,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0xf,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x103a0000,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VCVTUSI2SS %EDX,%XMM1,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS 0x24e1(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM0,%XMM3	1	1	0	0	0	0	0	0	0	3	1	scal (6.3%)
JA 1b9f <main+0x85f>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x26f,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JBE 1ad0 <main+0x790>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R8,-0x2830(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA -0x2770(%RBP),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %R9,-0x2820(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,-0x2810(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
VMOVAPS %XMM1,-0x2800(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 36c0 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV -0x13f0(%RBP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x2830(%RBP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x2820(%RBP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x2810(%RBP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VMOVAPS -0x2800(%RBP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VMOVSS 0x247c(%RIP),%XMM3	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVDQA64 0x26a6(%RIP),%ZMM7	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
JMP 1ad0 <main+0x790>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV -0x2850(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RCX,-0x2810(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %R9,-0x2820(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %R8,-0x2830(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
VMOVSS %XMM0,(%RDI)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
JMP 1c25 <main+0x8e5>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV -0x2840(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x2810(%RBP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%ZMM8	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
MOV $-0x80000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV -0x2820(%RBP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x2830(%RBP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%ZMM9	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
MOV $0x7fffffff,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVSS %XMM0,(%RDI)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VMOVDQA64 %ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VPBROADCASTQ %RDX,%ZMM10	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VMOVDQA64 %ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVDQA64 %ZMM10,%ZMM6	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVDQA %XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 1d29 <main+0x9e9>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV -0x2858(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADDQ $0x4,-0x2840(%RBP)	2	0.25	0.25	0.83	0.83	1	0.25	0.25	0.33	5	1	scal (12.5%)
ADDQ $0x4,-0x2850(%RBP)	2	0.25	0.25	0.83	0.83	1	0.25	0.25	0.33	5	1	scal (12.5%)
VMOVSS %XMM0,(%RDI)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD $0x4,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,-0x13f0(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,-0x2858(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
CMP %RDI,-0x2890(%RBP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 1b2d <main+0x7ed>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

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Matching between your loop (in the source code) and the binary loop

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Vectorization

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Execution units bottlenecks

CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code