| Loop Id: 23 | Module: attention-gcc-skl512 | Source: random.tcc:404-3558 [...] | Coverage: 0.09% |
|---|
| Loop Id: 23 | Module: attention-gcc-skl512 | Source: random.tcc:404-3558 [...] | Coverage: 0.09% |
|---|
0x1cd0 MOV -0x2770(%RBP,%RAX,8),%RSI |
0x1cd8 INC %RAX |
0x1cdb MOV %RSI,%RDX |
0x1cde SHR $0xb,%RDX |
0x1ce2 MOV %EDX,%EDX |
0x1ce4 XOR %RSI,%RDX |
0x1ce7 MOV %RDX,%RSI |
0x1cea SAL $0x7,%RSI |
0x1cee AND $-0x62d3a980,%ESI |
0x1cf4 XOR %RSI,%RDX |
0x1cf7 MOV %RDX,%RSI |
0x1cfa SAL $0xf,%RSI |
0x1cfe AND $-0x103a0000,%ESI |
0x1d04 XOR %RSI,%RDX |
0x1d07 MOV %RDX,%RSI |
0x1d0a SHR $0x12,%RSI |
0x1d0e XOR %RSI,%RDX |
0x1d11 VCVTUSI2SS %EDX,%XMM1,%XMM0 |
0x1d17 VMULSS 0x22e9(%RIP),%XMM0,%XMM0 |
0x1d1f VCOMISS %XMM0,%XMM3 |
0x1d23 JA 1eea |
0x1d29 CMP $0x26f,%RAX |
0x1d2f JBE 1cd0 |
0x1d31 LEA -0x2770(%RBP),%RAX |
0x1d38 NOPL (%RAX,%RAX,1) |
(24) 0x1d40 VPANDQ (%RAX),%ZMM5,%ZMM2 |
(24) 0x1d46 VMOVDQA64 %ZMM6,%ZMM0 |
(24) 0x1d4c ADD $0x40,%RAX |
(24) 0x1d50 VPTERNLOGQ $-0x14,-0x38(%RAX),%ZMM2,%ZMM0 |
(24) 0x1d5b VPSRLQ $0x1,%ZMM0,%ZMM2 |
(24) 0x1d62 VPANDQ %ZMM4,%ZMM0,%ZMM0 |
(24) 0x1d68 VPMULLQ %ZMM7,%ZMM0,%ZMM0 |
(24) 0x1d6e VPTERNLOGQ $-0x6a,0xc28(%RAX),%ZMM0,%ZMM2 |
(24) 0x1d79 VMOVDQA64 %ZMM2,-0x40(%RAX) |
(24) 0x1d80 CMP %RAX,%RBX |
(24) 0x1d83 JNE 1d40 |
0x1d85 MOV -0x2060(%RBP),%RDX |
0x1d8c MOV -0x2058(%RBP),%RAX |
0x1d93 VMOVDQA %XMM11,%XMM0 |
0x1d97 VPANDQ -0x2070(%RBP),%XMM9,%XMM2 |
0x1da1 AND $-0x80000000,%RDX |
0x1da8 AND $0x7fffffff,%EAX |
0x1dad OR %RDX,%RAX |
0x1db0 VPTERNLOGQ $-0x14,-0x2068(%RBP),%XMM2,%XMM0 |
0x1dbb MOV %RAX,%RDX |
0x1dbe VPSRLQ $0x1,%XMM0,%XMM2 |
0x1dc3 VPANDQ %XMM8,%XMM0,%XMM0 |
0x1dc9 AND $0x1,%EAX |
0x1dcc SHR $0x1,%RDX |
0x1dcf NEG %RAX |
0x1dd2 VPMULLQ -0x27f0(%RBP),%XMM0,%XMM0 |
0x1ddc VPTERNLOGQ $-0x6a,-0x1408(%RBP),%XMM0,%XMM2 |
0x1de7 XOR -0x13f8(%RBP),%RDX |
0x1dee AND $-0x66f74f21,%EAX |
0x1df3 VMOVDQA %XMM2,-0x2070(%RBP) |
0x1dfb XOR %RDX,%RAX |
0x1dfe LEA -0x1418(%RBP),%RDX |
0x1e05 MOV %RAX,-0x2060(%RBP) |
0x1e0c LEA -0x2058(%RBP),%RAX |
0x1e13 NOPL (%RAX,%RAX,1) |
(25) 0x1e18 VPANDQ (%RAX),%ZMM5,%ZMM2 |
(25) 0x1e1e VMOVDQA64 %ZMM6,%ZMM0 |
(25) 0x1e24 ADD $0x40,%RAX |
(25) 0x1e28 VPTERNLOGQ $-0x14,-0x38(%RAX),%ZMM2,%ZMM0 |
(25) 0x1e33 VPSRLQ $0x1,%ZMM0,%ZMM2 |
(25) 0x1e3a VPANDQ %ZMM4,%ZMM0,%ZMM0 |
(25) 0x1e40 VPMULLQ %ZMM7,%ZMM0,%ZMM0 |
(25) 0x1e46 VPTERNLOGQ $-0x6a,-0x758(%RAX),%ZMM0,%ZMM2 |
(25) 0x1e51 VMOVDQU64 %ZMM2,-0x40(%RAX) |
(25) 0x1e58 CMP %RAX,%RDX |
(25) 0x1e5b JNE 1e18 |
0x1e5d MOV -0x2770(%RBP),%RSI |
0x1e64 MOV -0x13f8(%RBP),%RAX |
0x1e6b VMOVDQA %YMM10,%YMM0 |
0x1e6f VPANDQ -0x1418(%RBP),%YMM9,%YMM2 |
0x1e79 MOV %RSI,%RDX |
0x1e7c AND $-0x80000000,%RAX |
0x1e82 AND $0x7fffffff,%EDX |
0x1e88 VPTERNLOGQ $-0x14,-0x1410(%RBP),%YMM2,%YMM0 |
0x1e93 OR %RDX,%RAX |
0x1e96 VPSRLQ $0x1,%YMM0,%YMM2 |
0x1e9b VPANDQ %YMM8,%YMM0,%YMM0 |
0x1ea1 MOV %RAX,%RDX |
0x1ea4 AND $0x1,%EAX |
0x1ea7 VPMULLQ -0x27f0(%RBP),%YMM0,%YMM0 |
0x1eb1 VPTERNLOGQ $-0x6a,-0x1b30(%RBP),%YMM0,%YMM2 |
0x1ebc SHR $0x1,%RDX |
0x1ebf NEG %RAX |
0x1ec2 VMOVDQU %YMM2,-0x1418(%RBP) |
0x1eca XOR -0x1b10(%RBP),%RDX |
0x1ed1 AND $-0x66f74f21,%EAX |
0x1ed6 XOR %RDX,%RAX |
0x1ed9 MOV %RAX,-0x13f8(%RBP) |
0x1ee0 MOV $0x1,%EAX |
0x1ee5 JMP 1cdb |
/usr/include/c++/16.1.1/bits/random.tcc: 404 - 3558 |
-------------------------------------------------------------------------------- |
404: for (size_t __k = 0; __k < (__n - __m); ++__k) |
405: { |
406: _UIntType __y = ((_M_x[__k] & __upper_mask) |
407: | (_M_x[__k + 1] & __lower_mask)); |
408: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
409: ^ ((__y & 0x01) ? __a : 0)); |
410: } |
411: |
412: for (size_t __k = (__n - __m); __k < (__n - 1); ++__k) |
413: { |
414: _UIntType __y = ((_M_x[__k] & __upper_mask) |
415: | (_M_x[__k + 1] & __lower_mask)); |
416: _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1) |
417: ^ ((__y & 0x01) ? __a : 0)); |
418: } |
419: |
420: _UIntType __y = ((_M_x[__n - 1] & __upper_mask) |
421: | (_M_x[0] & __lower_mask)); |
422: _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1) |
423: ^ ((__y & 0x01) ? __a : 0)); |
[...] |
458: if (_M_p >= state_size) |
459: _M_gen_rand(); |
460: |
461: // Calculate o(x(i)). |
462: result_type __z = _M_x[_M_p++]; |
463: __z ^= (__z >> __u) & __d; |
464: __z ^= (__z << __s) & __b; |
465: __z ^= (__z << __t) & __c; |
466: __z ^= (__z >> __l); |
[...] |
3557: const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd); |
3558: if (__ret < _RealT(1.0)) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | new_allocator.h:183 | attention-gcc-skl512 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.02 |
| CQA speedup if FP arith vectorized | 2.07 |
| CQA speedup if fully vectorized | 8.16 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.43 |
| Bottlenecks | |
| Function | main |
| Source | random.tcc:404-409,random.tcc:414-417,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 13.13 |
| CQA cycles if no scalar integer | 6.50 |
| CQA cycles if FP arith vectorized | 6.33 |
| CQA cycles if fully vectorized | 1.61 |
| Front-end cycles | 13.13 |
| P0 cycles | 9.17 |
| P1 cycles | 9.08 |
| P2 cycles | 4.25 |
| P3 cycles | 4.25 |
| P4 cycles | 2.00 |
| P5 cycles | 9.13 |
| P6 cycles | 9.13 |
| P7 cycles | 2.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 47.00 |
| Nb uops | 52.50 |
| Nb loads | 8.50 |
| Nb stores | 2.00 |
| Nb stack references | 6.00 |
| FLOP/cycle | 0.08 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 8.56 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 32.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 17.02 |
| Vectorization ratio load | 30.77 |
| Vectorization ratio store | 50.00 |
| Vectorization ratio mul | 33.33 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 15.79 |
| Vector-efficiency ratio all | 15.30 |
| Vector-efficiency ratio load | 18.39 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | 16.67 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 15.03 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.86 |
| CQA speedup if FP arith vectorized | 2.03 |
| CQA speedup if fully vectorized | 7.38 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.46 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | random.tcc:404-409,random.tcc:414-417,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 20.50 |
| CQA cycles if no scalar integer | 11.00 |
| CQA cycles if FP arith vectorized | 10.08 |
| CQA cycles if fully vectorized | 2.78 |
| Front-end cycles | 20.50 |
| P0 cycles | 14.08 |
| P1 cycles | 13.92 |
| P2 cycles | 7.50 |
| P3 cycles | 7.50 |
| P4 cycles | 4.00 |
| P5 cycles | 14.00 |
| P6 cycles | 14.00 |
| P7 cycles | 4.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 71.00 |
| Nb uops | 82.00 |
| Nb loads | 15.00 |
| Nb stores | 4.00 |
| Nb stack references | 12.00 |
| FLOP/cycle | 0.05 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 15.02 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 244.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 34.04 |
| Vectorization ratio load | 61.54 |
| Vectorization ratio store | 50.00 |
| Vectorization ratio mul | 66.67 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 31.58 |
| Vector-efficiency ratio all | 20.08 |
| Vector-efficiency ratio load | 27.40 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | 27.08 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 19.41 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.88 |
| CQA speedup if FP arith vectorized | 2.22 |
| CQA speedup if fully vectorized | 13.14 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.35 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | random.tcc:404-409,random.tcc:414-417,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.75 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 2.59 |
| CQA cycles if fully vectorized | 0.44 |
| Front-end cycles | 5.75 |
| P0 cycles | 4.25 |
| P1 cycles | 4.25 |
| P2 cycles | 1.00 |
| P3 cycles | 1.00 |
| P4 cycles | 0.00 |
| P5 cycles | 4.25 |
| P6 cycles | 4.25 |
| P7 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 23.00 |
| Nb uops | 23.00 |
| Nb loads | 2.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.17 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 2.09 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 12.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 10.53 |
| Vector-efficiency ratio load | 9.38 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 10.66 |
| Path / |
| Function | main |
| Source file and lines | random.tcc:404-3558 |
| Module | attention-gcc-skl512 |
| nb instructions | 47 |
| nb uops | 52.50 |
| loop length | 243 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 5 |
| used ymm registers | 2.50 |
| used zmm registers | 0 |
| nb stack references | 6 |
| micro-operation queue | 13.13 cycles |
| front end | 13.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 9.17 | 9.08 | 4.25 | 4.25 | 2.00 | 9.13 | 9.13 | 2.00 |
| cycles | 9.17 | 9.08 | 4.25 | 4.25 | 2.00 | 9.13 | 9.13 | 2.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 13.13 |
| Dispatch | 9.17 |
| Data deps. | 0.00 |
| Overall L1 | 13.13 |
| all | 17% |
| load | 33% |
| store | 50% |
| mul | 100% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 16% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 17% |
| load | 30% |
| store | 50% |
| mul | 33% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 15% |
| all | 15% |
| load | 20% |
| store | 25% |
| mul | 37% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 15% |
| all | 6% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| all | 15% |
| load | 18% |
| store | 25% |
| mul | 16% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 15% |
| Function | main |
| Source file and lines | random.tcc:404-3558 |
| Module | attention-gcc-skl512 |
| nb instructions | 71 |
| nb uops | 82 |
| loop length | 389 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 7 |
| used ymm registers | 5 |
| used zmm registers | 0 |
| nb stack references | 12 |
| micro-operation queue | 20.50 cycles |
| front end | 20.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 14.08 | 13.92 | 7.50 | 7.50 | 4.00 | 14.00 | 14.00 | 4.00 |
| cycles | 14.08 | 13.92 | 7.50 | 7.50 | 4.00 | 14.00 | 14.00 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 20.50 |
| Dispatch | 14.08 |
| Data deps. | 0.00 |
| Overall L1 | 20.50 |
| all | 35% |
| load | 66% |
| store | 50% |
| mul | 100% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 32% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 34% |
| load | 61% |
| store | 50% |
| mul | 66% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 31% |
| all | 20% |
| load | 29% |
| store | 25% |
| mul | 37% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 19% |
| all | 6% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| all | 20% |
| load | 27% |
| store | 25% |
| mul | 27% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 19% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0xb,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SAL $0x7,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x62d3a980,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SAL $0xf,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x103a0000,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0x12,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| VCVTUSI2SS %EDX,%XMM1,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 | scal (6.3%) |
| VMULSS 0x22e9(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VCOMISS %XMM0,%XMM3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| JA 1eea <main+0xbaa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| CMP $0x26f,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JBE 1cd0 <main+0x990> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| LEA -0x2770(%RBP),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| MOV -0x2060(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| MOV -0x2058(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVDQA %XMM11,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| VPANDQ -0x2070(%RBP),%XMM9,%XMM2 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| AND $-0x80000000,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| AND $0x7fffffff,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| OR %RDX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VPTERNLOGQ $-0x14,-0x2068(%RBP),%XMM2,%XMM0 | 2 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| VPSRLQ $0x1,%XMM0,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VPANDQ %XMM8,%XMM0,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (25.0%) |
| AND $0x1,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| SHR $0x1,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| NEG %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VPMULLQ -0x27f0(%RBP),%XMM0,%XMM0 | 4 | 1.50 | 1.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (25.0%) |
| VPTERNLOGQ $-0x6a,-0x1408(%RBP),%XMM0,%XMM2 | 2 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| XOR -0x13f8(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x66f74f21,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VMOVDQA %XMM2,-0x2070(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 | vect (25.0%) |
| XOR %RDX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| LEA -0x1418(%RBP),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| MOV %RAX,-0x2060(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| LEA -0x2058(%RBP),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| MOV -0x2770(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| MOV -0x13f8(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVDQA %YMM10,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| VPANDQ -0x1418(%RBP),%YMM9,%YMM2 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| AND $-0x80000000,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| AND $0x7fffffff,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| VPTERNLOGQ $-0x14,-0x1410(%RBP),%YMM2,%YMM0 | 2 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| OR %RDX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VPSRLQ $0x1,%YMM0,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VPANDQ %YMM8,%YMM0,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| AND $0x1,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VPMULLQ -0x27f0(%RBP),%YMM0,%YMM0 | 4 | 1.50 | 1.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (50.0%) |
| VPTERNLOGQ $-0x6a,-0x1b30(%RBP),%YMM0,%YMM2 | 2 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| SHR $0x1,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| NEG %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VMOVDQU %YMM2,-0x1418(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 | vect (50.0%) |
| XOR -0x1b10(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x66f74f21,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| XOR %RDX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RAX,-0x13f8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV $0x1,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JMP 1cdb <main+0x99b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| Function | main |
| Source file and lines | random.tcc:404-3558 |
| Module | attention-gcc-skl512 |
| nb instructions | 23 |
| nb uops | 23 |
| loop length | 97 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 5.75 cycles |
| front end | 5.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 4.25 | 4.25 | 1.00 | 1.00 | 0.00 | 4.25 | 4.25 | 0.00 |
| cycles | 4.25 | 4.25 | 1.00 | 1.00 | 0.00 | 4.25 | 4.25 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 5.75 |
| Dispatch | 4.25 |
| Data deps. | 0.00 |
| Overall L1 | 5.75 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 11% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 6% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| all | 10% |
| load | 9% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 10% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV -0x2770(%RBP,%RAX,8),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| INC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0xb,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SAL $0x7,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x62d3a980,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SAL $0xf,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x103a0000,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0x12,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| VCVTUSI2SS %EDX,%XMM1,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 | scal (6.3%) |
| VMULSS 0x22e9(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VCOMISS %XMM0,%XMM3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| JA 1eea <main+0xbaa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| CMP $0x26f,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JBE 1cd0 <main+0x990> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
