OV - attention-gcc-skl512 - Loop 20

0x244c XOR	%R11D,%R11D

0x244f NOP

  (19) 0x2450 MOV	%R11D,%ESI

  (19) 0x2453 VXORPD	%XMM4,%XMM4,%XMM4

  (19) 0x2457 XOR	%EAX,%EAX

  (19) 0x2459 NOPL	(%RAX)

    (18) 0x2460 LEA	(%RAX,%RCX,1),%R10D

    (18) 0x2464 INC	%EAX

    (18) 0x2466 VCVTSS2SD	(%R15,%R10,4),%XMM1,%XMM0

    (18) 0x246c MOV	%ESI,%R10D

    (18) 0x246f VMOVAPD	%XMM0,%XMM2

    (18) 0x2473 ADD	%R8D,%ESI

    (18) 0x2476 VCVTSS2SD	(%R13,%R10,4),%XMM1,%XMM0

    (18) 0x247d VFMADD231SD	%XMM0,%XMM2,%XMM4

    (18) 0x2482 CMP	%R9D,%EAX

    (18) 0x2485 JB	2460

  (19) 0x2487 LEA	(%R11,%RDI,1),%EAX

  (19) 0x248b INC	%R11D

  (19) 0x248e VCVTSD2SS	%XMM4,%XMM4,%XMM4

  (19) 0x2492 VMOVSS	%XMM4,(%R14,%RAX,4)

  (19) 0x2498 CMP	%R8D,%R11D

  (19) 0x249b JB	2450

0x249d INC	%EDX

0x249f ADD	%R8D,%EDI

0x24a2 ADD	%R9D,%ECX

0x24a5 CMP	%R9D,%EDX

0x24a8 JB	244c

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:183	attention-gcc-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.09
Front-end cycles	1.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	6.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.09
Front-end cycles	1.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	6.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-gcc-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-27.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.09 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	7
nb uops	6
loop length	17
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	1.00	0.00	0.00	0.00	1.00	1.00	0.00
cycles	1.00	1.00	0.00	0.00	0.00	1.00	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.50
Dispatch	1.00
Data deps.	1.00
Overall L1	1.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.50 to 1.00 cycles (1.50x speedup).

ASM code

In the binary file, the address of the loop is: 244c

Instruction	Nb FU	P0	P1	P5	P6	Latency	Recip. throughput	Vectorization
XOR %R11D,%R11D	1	0	0	0	0	0	0.25	scal (6.3%)
NOP	1	0	0	0	0	0	0.25	N/A
INC %EDX	1	0.25	0.25	0.25	0.25	1	0.25	N/A
ADD %R8D,%EDI	1	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
ADD %R9D,%ECX	1	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
CMP %R9D,%EDX	1	0.25	0.25	0.25	0.25	1	0.25	N/A
JB 244c <main+0x110c>	1	0.50	0	0	0.50	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-gcc-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-27.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.09 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	7
nb uops	6
loop length	17
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	1.00	0.00	0.00	0.00	1.00	1.00	0.00
cycles	1.00	1.00	0.00	0.00	0.00	1.00	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.50
Dispatch	1.00
Data deps.	1.00
Overall L1	1.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.50 to 1.00 cycles (1.50x speedup).

ASM code

In the binary file, the address of the loop is: 244c

Instruction	Nb FU	P0	P1	P5	P6	Latency	Recip. throughput	Vectorization
XOR %R11D,%R11D	1	0	0	0	0	0	0.25	scal (6.3%)
NOP	1	0	0	0	0	0	0.25	N/A
INC %EDX	1	0.25	0.25	0.25	0.25	1	0.25	N/A
ADD %R8D,%EDI	1	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
ADD %R9D,%ECX	1	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
CMP %R9D,%EDX	1	0.25	0.25	0.25	0.25	1	0.25	N/A
JB 244c <main+0x110c>	1	0.50	0	0	0.50	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code