OV - attention-gcc-skl512 - Function softmax(float const*, float*, float*, int)

	Function: softmax(float const, float, float*, int)	Module: attention-gcc-skl512	Source: attention_v2.cpp:42-63	Coverage (incl. loops): 5.29% \| (excl. loops): 0.00%

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 42 - 63

--------------------------------------------------------------------------------

42: {

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

62:    }

63: }

0x2e10 TEST	%ECX,%ECX

0x2e12 JLE	30e6

0x2e18 LEA	0x8(%RSP),%R10

0x2e1d AND	$-0x40,%RSP

0x2e21 MOV	%ECX,%R9D

0x2e24 PUSHQ	-0x8(%R10)

0x2e28 LEA	0x4(,%R9,4),%RAX

0x2e30 PUSH	%RBP

0x2e31 MOV	%RSP,%RBP

0x2e34 PUSH	%R15

0x2e36 XOR	%R15D,%R15D

0x2e39 PUSH	%R14

0x2e3b MOV	%RDI,%R14

0x2e3e PUSH	%R13

0x2e40 PUSH	%R12

0x2e42 PUSH	%R10

0x2e44 PUSH	%RBX

0x2e45 LEA	0x4(%RDI),%RBX

0x2e49 ADD	$-0x80,%RSP

0x2e4d MOV	%RAX,-0x78(%RBP)

0x2e51 LEA	0x4(%RDX),%RAX

0x2e55 MOV	%RAX,-0x50(%RBP)

0x2e59 LEA	(,%R9,4),%RAX

0x2e61 VBROADCASTSS	0x1199(%RIP),%ZMM0

0x2e6b MOV	%ECX,-0x54(%RBP)

0x2e6e MOV	%RSI,-0x68(%RBP)

0x2e72 MOV	%RAX,-0x70(%RBP)

0x2e76 MOVQ	$0,-0x48(%RBP)

0x2e7e MOVQ	$0x1,-0x40(%RBP)

0x2e86 MOV	%R9,-0x80(%RBP)

0x2e8a MOV	%RDI,-0x88(%RBP)

0x2e91 MOV	%RDX,-0x60(%RBP)

0x2e95 CMP	$0xe,%R15D

0x2e99 JLE	30a2

0x2e9f NOP

    (34) 0x2ea0 MOV	-0x40(%RBP),%EDI

    (34) 0x2ea3 MOV	-0x40(%RBP),%R8D

    (34) 0x2ea7 MOV	%R14,%RAX

    (34) 0x2eaa SHR	$0x4,%EDI

    (34) 0x2ead MOV	%EDI,%ESI

    (34) 0x2eaf SAL	$0x6,%RSI

    (34) 0x2eb3 ADD	%R14,%RSI

    (34) 0x2eb6 NOPW	%CS:(%RAX,%RAX,1)

      (33) 0x2ec0 VMAXPS	(%RAX),%ZMM0,%ZMM0

      (33) 0x2ec6 ADD	$0x40,%RAX

      (33) 0x2eca CMP	%RAX,%RSI

      (33) 0x2ecd JNE	2ec0

    (34) 0x2ecf VEXTRACTF32X8	$0x1,%ZMM0,%YMM3

    (34) 0x2ed6 VMOVAPS	%YMM0,%YMM1

    (34) 0x2eda MOV	%EDI,%EAX

    (34) 0x2edc VMAXPS	%YMM0,%YMM3,%YMM2

    (34) 0x2ee0 SAL	$0x4,%EAX

    (34) 0x2ee3 VEXTRACTF32X4	$0x1,%YMM2,%XMM0

    (34) 0x2eea VMAXPS	%XMM2,%XMM0,%XMM0

    (34) 0x2eee VMOVHLPS	%XMM0,%XMM0,%XMM2

    (34) 0x2ef2 VMAXPS	%XMM0,%XMM2,%XMM2

    (34) 0x2ef6 VSHUFPS	$0x55,%XMM2,%XMM2,%XMM0

    (34) 0x2efb VMAXPS	%XMM2,%XMM0,%XMM0

    (34) 0x2eff CMP	%R8D,%EAX

    (34) 0x2f02 JE	2fb2

  (35) 0x2f08 VMAXPS	%YMM3,%YMM1,%YMM1

  (35) 0x2f0c MOV	%EAX,%ESI

  (35) 0x2f0e MOV	%R15D,%EDI

  (35) 0x2f11 SUB	%EAX,%EDI

  (35) 0x2f13 CMP	$0x6,%EDI

  (35) 0x2f16 JBE	2f52

  (35) 0x2f18 MOV	-0x88(%RBP),%RDX

  (35) 0x2f1f ADD	-0x48(%RBP),%RAX

  (35) 0x2f23 INC	%EDI

  (35) 0x2f25 VMAXPS	(%RDX,%RAX,4),%YMM1,%YMM1

  (35) 0x2f2a MOV	%EDI,%EAX

  (35) 0x2f2c AND	$-0x8,%EAX

  (35) 0x2f2f AND	$0x7,%EDI

  (35) 0x2f32 VEXTRACTF32X4	$0x1,%YMM1,%XMM0

  (35) 0x2f39 VMAXPS	%XMM1,%XMM0,%XMM0

  (35) 0x2f3d VMOVHLPS	%XMM0,%XMM0,%XMM1

  (35) 0x2f41 VMAXPS	%XMM0,%XMM1,%XMM1

  (35) 0x2f45 VSHUFPS	$0x55,%XMM1,%XMM1,%XMM0

  (35) 0x2f4a VMAXPS	%XMM1,%XMM0,%XMM0

  (35) 0x2f4e JE	2fb2

  (35) 0x2f50 ADD	%EAX,%ESI

  (35) 0x2f52 MOVSXD	%ESI,%RAX

  (35) 0x2f55 VMAXSS	(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f5b CMP	%ESI,%R15D

  (35) 0x2f5e JLE	2fb2

  (35) 0x2f60 LEA	0x2(%RSI),%EDI

  (35) 0x2f63 VMAXSS	0x4(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f6a CMP	%EDI,%R15D

  (35) 0x2f6d JL	2fb2

  (35) 0x2f6f LEA	0x3(%RSI),%EDI

  (35) 0x2f72 VMAXSS	0x8(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f79 CMP	%EDI,%R15D

  (35) 0x2f7c JL	2fb2

  (35) 0x2f7e LEA	0x4(%RSI),%EDI

  (35) 0x2f81 VMAXSS	0xc(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f88 CMP	%EDI,%R15D

  (35) 0x2f8b JL	2fb2

  (35) 0x2f8d LEA	0x5(%RSI),%EDI

  (35) 0x2f90 VMAXSS	0x10(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2f97 CMP	%R15D,%EDI

  (35) 0x2f9a JG	2fb2

  (35) 0x2f9c ADD	$0x6,%ESI

  (35) 0x2f9f VMAXSS	0x14(%R14,%RAX,4),%XMM0,%XMM0

  (35) 0x2fa6 CMP	%ESI,%R15D

  (35) 0x2fa9 JL	2fb2

  (35) 0x2fab VMAXSS	0x18(%R14,%RAX,4),%XMM0,%XMM0

    (34) 0x2fb2 MOVL	$0,-0x34(%RBP)

    (34) 0x2fb9 MOV	%R14,%R12

    (34) 0x2fbc VMOVSS	%XMM0,-0x38(%RBP)

    (34) 0x2fc1 VZEROUPPER

    (34) 0x2fc4 NOPL	(%RAX)

      (31) 0x2fc8 VMOVSS	(%R12),%XMM1

      (31) 0x2fce ADD	$0x4,%R12

      (31) 0x2fd2 VSUBSS	-0x38(%RBP),%XMM1,%XMM0

      (31) 0x2fd7 CALL	1110 <expf@plt>

      (31) 0x2fdc VADDSS	-0x34(%RBP),%XMM0,%XMM5

      (31) 0x2fe1 VMOVSS	%XMM5,-0x34(%RBP)

      (31) 0x2fe6 CMP	%R12,%RBX

      (31) 0x2fe9 JNE	2fc8

    (34) 0x2feb MOV	-0x60(%RBP),%RAX

    (34) 0x2fef MOV	-0x48(%RBP),%RCX

    (34) 0x2ff3 MOV	%R14,%R13

    (34) 0x2ff6 LEA	(%RAX,%RCX,4),%R12

    (34) 0x2ffa NOPW	(%RAX,%RAX,1)

      (32) 0x3000 VMOVSS	(%R13),%XMM1

      (32) 0x3006 ADD	$0x4,%R13

      (32) 0x300a ADD	$0x4,%R12

      (32) 0x300e VSUBSS	-0x38(%RBP),%XMM1,%XMM0

      (32) 0x3013 CALL	1110 <expf@plt>

      (32) 0x3018 VDIVSS	-0x34(%RBP),%XMM0,%XMM0

      (32) 0x301d VMOVSS	%XMM0,-0x4(%R12)

      (32) 0x3024 CMP	%R13,%RBX

      (32) 0x3027 JNE	3000

    (34) 0x3029 MOV	-0x54(%RBP),%EDX

    (34) 0x302c LEA	0x1(%R15),%R8D

    (34) 0x3030 CMP	%R8D,%EDX

    (34) 0x3033 JE	30c0

    (34) 0x3039 INCQ	-0x40(%RBP)

    (34) 0x303d MOV	-0x80(%RBP),%RSI

    (34) 0x3041 MOV	%EDX,%EAX

    (34) 0x3043 MOV	-0x50(%RBP),%R13

    (34) 0x3047 MOV	-0x78(%RBP),%R12

    (34) 0x304b MOV	%R8D,-0x38(%RBP)

    (34) 0x304f ADD	%RSI,-0x48(%RBP)

    (34) 0x3053 XOR	%ESI,%ESI

    (34) 0x3055 ADD	-0x70(%RBP),%R14

    (34) 0x3059 MOV	%R13,%RDI

    (34) 0x305c ADD	%R12,%R13

    (34) 0x305f ADD	%R12,%RBX

    (34) 0x3062 MOV	-0x40(%RBP),%R15

    (34) 0x3066 SUB	%R15D,%EAX

    (34) 0x3069 LEA	0x4(,%RAX,4),%RDX

    (34) 0x3071 CALL	1050 <memset@plt>

    (34) 0x3076 MOV	-0x68(%RBP),%RAX

    (34) 0x307a VMOVSS	-0x34(%RBP),%XMM2

    (34) 0x307f MOV	%R13,-0x50(%RBP)

    (34) 0x3083 VBROADCASTSS	0xf77(%RIP),%ZMM0

    (34) 0x308d VMOVSS	%XMM2,-0x8(%RAX,%R15,4)

    (34) 0x3094 MOV	-0x38(%RBP),%R15D

    (34) 0x3098 CMP	$0xe,%R15D

    (34) 0x309c JG	2ea0

(36) 0x30a2 VMOVAPS	%YMM0,%YMM1

(36) 0x30a6 XOR	%EAX,%EAX

(36) 0x30a8 VMOVSS	0xf54(%RIP),%XMM0

(36) 0x30b0 XOR	%ESI,%ESI

(36) 0x30b2 JMP	2f0e

0x30b7 NOPW	(%RAX,%RAX,1)

0x30c0 MOV	-0x68(%RBP),%RAX

0x30c4 VMOVSS	-0x34(%RBP),%XMM2

0x30c9 MOV	%R15D,%EDX

0x30cc VMOVSS	%XMM2,(%RAX,%RDX,4)

0x30d1 SUB	$-0x80,%RSP

0x30d5 POP	%RBX

0x30d6 POP	%R10

0x30d8 POP	%R12

0x30da POP	%R13

0x30dc POP	%R14

0x30de POP	%R15

0x30e0 POP	%RBP

0x30e1 LEA	-0x8(%R10),%RSP

0x30e5 RET

0x30e6 RET

0x30e7 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	main	attention_v2.cpp:283	attention-gcc-skl512
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:183	attention-gcc-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-skl512

The function is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.00 to 2.25 cycles (8.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 19.00 to 1.62 cycles (11.69x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.00 to 13.25 cycles (1.43x speedup).

Workaround

Write less array elements

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	52
nb uops	53
loop length	201
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	1
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.25 cycles
front end	13.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.75	3.75	10.83	10.50	19.00	3.75	3.75	10.67
cycles	3.75	4.25	10.83	10.50	19.00	3.75	3.75	10.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.25
Dispatch	19.00
Overall L1	19.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

0% of peak load performance is reached (1.26 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.21 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2e10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JLE 30e6 <_Z7softmaxPKfPfS1_i+0x2d6>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x8(%RSP),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %ECX,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSHQ -0x8(%R10)	2	0	0	0.83	0.83	1	0	0	0.33	3	1	N/A
LEA 0x4(,%R9,4),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSH %R15	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
PUSH %R14	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
PUSH %R13	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %R12	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %R10	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %RBX	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
LEA 0x4(%RDI),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
ADD $-0x80,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (,%R9,4),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VBROADCASTSS 0x1199(%RIP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
MOV %ECX,-0x54(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV %RSI,-0x68(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
MOV %R9,-0x80(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,-0x88(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
CMP $0xe,%R15D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JLE 30a2 <_Z7softmaxPKfPfS1_i+0x292>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS %XMM2,(%RAX,%RDX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
SUB $-0x80,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
POP %RBX	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R10	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R12	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R13	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R14	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R15	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %RBP	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
LEA -0x8(%R10),%RSP	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-skl512

The function is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.00 to 2.25 cycles (8.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Write less array elements

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	52
nb uops	53
loop length	201
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	1
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.25 cycles
front end	13.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.75	3.75	10.83	10.50	19.00	3.75	3.75	10.67
cycles	3.75	4.25	10.83	10.50	19.00	3.75	3.75	10.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.25
Dispatch	19.00
Overall L1	19.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

0% of peak load performance is reached (1.26 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.21 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2e10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JLE 30e6 <_Z7softmaxPKfPfS1_i+0x2d6>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x8(%RSP),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %ECX,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSHQ -0x8(%R10)	2	0	0	0.83	0.83	1	0	0	0.33	3	1	N/A
LEA 0x4(,%R9,4),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSH %R15	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
PUSH %R14	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
PUSH %R13	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %R12	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %R10	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %RBX	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
LEA 0x4(%RDI),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
ADD $-0x80,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (,%R9,4),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VBROADCASTSS 0x1199(%RIP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
MOV %ECX,-0x54(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV %RSI,-0x68(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
MOV %R9,-0x80(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,-0x88(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
CMP $0xe,%R15D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JLE 30a2 <_Z7softmaxPKfPfS1_i+0x292>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS %XMM2,(%RAX,%RDX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
SUB $-0x80,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
POP %RBX	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R10	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R12	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R13	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R14	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R15	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %RBP	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
LEA -0x8(%R10),%RSP	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A

Name	Coverage (%)	Time (s)
▼softmax(float const, float, float*, int)–	5.29	1.46
▼Loop 36 - attention_v2.cpp:43-61 - attention-gcc-skl512–	0.02	0.01
▼Loop 35 - attention_v2.cpp:43-61 - attention-gcc-skl512–	0.11	0.03
▼Loop 34 - attention_v2.cpp:43-61 - attention-gcc-skl512–	0.11	0.03
○Loop 32 - attention_v2.cpp:55-56 - attention-gcc-skl512	4.42	1.23
○Loop 31 - attention_v2.cpp:52-53 - attention-gcc-skl512	0.61	0.17
○Loop 33 - attention_v2.cpp:47-48 - attention-gcc-skl512	0.02	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code