OV - attention-gcc-skl256 - Loop 4 - attention-gcc-skl256

0x2090 LEA	(%RAX,%RCX,1),%R11D

0x2094 INC	%EAX

0x2096 VCVTSS2SD	(%RBX,%R11,4),%XMM2,%XMM0    [1]

0x209c MOV	%ESI,%R11D

0x209f VMOVAPD	%XMM0,%XMM1

0x20a3 ADD	%R8D,%ESI

0x20a6 VCVTSS2SD	(%RDI,%R11,4),%XMM2,%XMM0    [2]

0x20ac VFMADD231SD	%XMM0,%XMM1,%XMM3

0x20b1 CMP	%R8D,%EAX

0x20b4 JB	2090

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	main	new_allocator.h:183	attention-gcc-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.58
CQA speedup if fully vectorized	14.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	1.55
CQA cycles if fully vectorized	0.28
Front-end cycles	2.75
P0 cycles	2.00
P1 cycles	1.75
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.00
P5 cycles	1.75
P6 cycles	1.50
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	9.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.58
CQA speedup if fully vectorized	14.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	1.55
CQA cycles if fully vectorized	0.28
Front-end cycles	2.75
P0 cycles	2.00
P1 cycles	1.75
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.00
P5 cycles	1.75
P6 cycles	1.50
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	9.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-gcc-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.28 cycles (14.55x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	10
nb uops	9
loop length	38
used x86 registers	7
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	1.75	1.00	1.00	0.00	1.75	1.50	0.00
cycles	2.00	1.75	1.00	1.00	0.00	1.75	1.50	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	2.75
Dispatch	2.00
Data deps.	4.00
Overall L1	4.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	20%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	12%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

1% of peak load performance is reached (2.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2090

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA (%RAX,%RCX,1),%R11D	1	0	0.50	0	0	0.50	0	1	0.50	N/A
INC %EAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
VCVTSS2SD (%RBX,%R11,4),%XMM2,%XMM0	1	0.50	0.50	0.50	0.50	0	0	5	0.50	scal (6.3%)
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0.25	N/A
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
ADD %R8D,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
VCVTSS2SD (%RDI,%R11,4),%XMM2,%XMM0	1	0.50	0.50	0.50	0.50	0	0	5	0.50	scal (6.3%)
VFMADD231SD %XMM0,%XMM1,%XMM3	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R8D,%EAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JB 2090 <main+0xd50>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-gcc-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.28 cycles (14.55x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	10
nb uops	9
loop length	38
used x86 registers	7
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	1.75	1.00	1.00	0.00	1.75	1.50	0.00
cycles	2.00	1.75	1.00	1.00	0.00	1.75	1.50	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	2.75
Dispatch	2.00
Data deps.	4.00
Overall L1	4.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	20%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	12%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

1% of peak load performance is reached (2.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2090

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA (%RAX,%RCX,1),%R11D	1	0	0.50	0	0	0.50	0	1	0.50	N/A
INC %EAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
VCVTSS2SD (%RBX,%R11,4),%XMM2,%XMM0	1	0.50	0.50	0.50	0.50	0	0	5	0.50	scal (6.3%)
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0.25	N/A
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
ADD %R8D,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
VCVTSS2SD (%RDI,%R11,4),%XMM2,%XMM0	1	0.50	0.50	0.50	0.50	0	0	5	0.50	scal (6.3%)
VFMADD231SD %XMM0,%XMM1,%XMM3	1	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
CMP %R8D,%EAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JB 2090 <main+0xd50>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code