OV - attention-gcc-skl256 - Loop 35

	Loop Id: 35	Module: attention-gcc-skl256	Source: attention_v2.cpp:43-61	Coverage: 0.04%

  (34) 0x2d00 MOV	%R13D,%ECX

  (34) 0x2d03 MOV	%R13D,%ESI

  (34) 0x2d06 MOV	%R12,%RAX

  (34) 0x2d09 SHR	$0x3,%ECX

  (34) 0x2d0c MOV	%ECX,%EDX

  (34) 0x2d0e SAL	$0x5,%RDX

  (34) 0x2d12 ADD	%R12,%RDX

  (34) 0x2d15 NOPL	(%RAX)

    (33) 0x2d18 VMAXPS	(%RAX),%YMM0,%YMM0

    (33) 0x2d1c ADD	$0x20,%RAX

    (33) 0x2d20 CMP	%RDX,%RAX

    (33) 0x2d23 JNE	2d18

  (34) 0x2d25 VEXTRACTF32X4	$0x1,%YMM0,%XMM3

  (34) 0x2d2c LEA	(,%RCX,8),%EAX

  (34) 0x2d33 VMAXPS	%XMM0,%XMM3,%XMM1

  (34) 0x2d37 VMOVHLPS	%XMM1,%XMM1,%XMM2

  (34) 0x2d3b VMAXPS	%XMM1,%XMM2,%XMM2

  (34) 0x2d3f VSHUFPS	$0x55,%XMM2,%XMM2,%XMM1

  (34) 0x2d44 VMAXPS	%XMM2,%XMM1,%XMM1

  (34) 0x2d48 CMP	%ESI,%EAX

  (34) 0x2d4a JE	2dad

0x2d4c VMAXPS	%XMM3,%XMM0,%XMM0

0x2d50 MOV	%EAX,%ECX

0x2d52 MOV	-0x3c(%RBP),%EDX

0x2d55 SUB	%EAX,%EDX

0x2d57 CMP	$0x2,%EDX

0x2d5a JBE	2d88

0x2d5c MOV	-0x80(%RBP),%RDI

0x2d60 ADD	-0x48(%RBP),%RAX

0x2d64 INC	%EDX

0x2d66 VMAXPS	(%RDI,%RAX,4),%XMM0,%XMM0

0x2d6b MOV	%EDX,%EAX

0x2d6d AND	$-0x4,%EAX

0x2d70 AND	$0x3,%EDX

0x2d73 VMOVHLPS	%XMM0,%XMM0,%XMM1

0x2d77 VMAXPS	%XMM0,%XMM1,%XMM0

0x2d7b VSHUFPS	$0x55,%XMM0,%XMM0,%XMM1

0x2d80 VMAXPS	%XMM0,%XMM1,%XMM1

0x2d84 JE	2dad

0x2d86 ADD	%EAX,%ECX

0x2d88 MOV	-0x3c(%RBP),%ESI

0x2d8b MOVSXD	%ECX,%RAX

0x2d8e VMAXSS	(%R12,%RAX,4),%XMM1,%XMM1

0x2d94 CMP	%ECX,%ESI

0x2d96 JLE	2dad

0x2d98 ADD	$0x2,%ECX

0x2d9b VMAXSS	0x4(%R12,%RAX,4),%XMM1,%XMM1

0x2da2 CMP	%ECX,%ESI

0x2da4 JL	2dad

0x2da6 VMAXSS	0x8(%R12,%RAX,4),%XMM1,%XMM1

  (34) 0x2dad MOVL	$0,-0x34(%RBP)

  (34) 0x2db4 MOV	%R12,%R14

  (34) 0x2db7 VMOVSS	%XMM1,-0x38(%RBP)

  (34) 0x2dbc VZEROUPPER

  (34) 0x2dbf NOP

    (31) 0x2dc0 VMOVSS	(%R14),%XMM0

    (31) 0x2dc5 ADD	$0x4,%R14

    (31) 0x2dc9 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

    (31) 0x2dce CALL	1110 <expf@plt>

    (31) 0x2dd3 VADDSS	-0x34(%RBP),%XMM0,%XMM5

    (31) 0x2dd8 VMOVSS	%XMM5,-0x34(%RBP)

    (31) 0x2ddd CMP	%RBX,%R14

    (31) 0x2de0 JNE	2dc0

  (34) 0x2de2 MOV	-0x58(%RBP),%RAX

  (34) 0x2de6 MOV	-0x48(%RBP),%RDI

  (34) 0x2dea MOV	%R12,%R15

  (34) 0x2ded LEA	(%RAX,%RDI,4),%R14

  (34) 0x2df1 NOPL	(%RAX)

    (32) 0x2df8 VMOVSS	(%R15),%XMM0

    (32) 0x2dfd ADD	$0x4,%R15

    (32) 0x2e01 ADD	$0x4,%R14

    (32) 0x2e05 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

    (32) 0x2e0a CALL	1110 <expf@plt>

    (32) 0x2e0f VDIVSS	-0x34(%RBP),%XMM0,%XMM0

    (32) 0x2e14 VMOVSS	%XMM0,-0x4(%R14)

    (32) 0x2e1a CMP	%RBX,%R15

    (32) 0x2e1d JNE	2df8

  (34) 0x2e1f MOV	-0x3c(%RBP),%EAX

  (34) 0x2e22 MOV	-0x40(%RBP),%EDI

  (34) 0x2e25 LEA	0x1(%RAX),%ECX

  (34) 0x2e28 CMP	%ECX,%EDI

  (34) 0x2e2a JE	2ea8

  (34) 0x2e2c MOV	-0x78(%RBP),%RSI

  (34) 0x2e30 MOV	-0x50(%RBP),%R15

  (34) 0x2e34 INC	%R13

  (34) 0x2e37 MOV	%EDI,%EAX

  (34) 0x2e39 SUB	%R13D,%EAX

  (34) 0x2e3c MOV	-0x70(%RBP),%R14

  (34) 0x2e40 ADD	-0x68(%RBP),%R12

  (34) 0x2e44 MOV	%ECX,-0x38(%RBP)

  (34) 0x2e47 ADD	%RSI,-0x48(%RBP)

  (34) 0x2e4b MOV	%R15,%RDI

  (34) 0x2e4e LEA	0x4(,%RAX,4),%RDX

  (34) 0x2e56 XOR	%ESI,%ESI

  (34) 0x2e58 CALL	1050 <memset@plt>

  (34) 0x2e5d MOV	-0x38(%RBP),%ECX

  (34) 0x2e60 MOV	-0x60(%RBP),%RAX

  (34) 0x2e64 ADD	%R14,%R15

  (34) 0x2e67 VMOVSS	-0x34(%RBP),%XMM2

  (34) 0x2e6c ADD	%R14,%RBX

  (34) 0x2e6f VBROADCASTSS	0x118c(%RIP),%YMM0

  (34) 0x2e78 MOV	%R15,-0x50(%RBP)

  (34) 0x2e7c MOV	%ECX,-0x3c(%RBP)

  (34) 0x2e7f VMOVSS	%XMM2,-0x8(%RAX,%R13,4)

  (34) 0x2e86 CMPL	$0x6,-0x3c(%RBP)

  (34) 0x2e8a JG	2d00

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Source Location	Module
►100.00+	main	attention_v2.cpp:283	attention-gcc-skl256
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	main	new_allocator.h:183	attention-gcc-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.43
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:47-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	5.75
CQA cycles if FP arith vectorized	8.25
CQA cycles if fully vectorized	0.78
Front-end cycles	8.25
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	29.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.30
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.00
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	12.92
Vector-efficiency ratio load	10.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	1.43
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:47-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	5.75
CQA cycles if FP arith vectorized	8.25
CQA cycles if fully vectorized	0.78
Front-end cycles	8.25
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	29.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.30
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.00
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	12.92
Vector-efficiency ratio load	10.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:47-48.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.25 to 5.75 cycles (1.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.25 to 0.78 cycles (10.55x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 52 bytes (13 single precision FP elements).

General properties

nb instructions	29
nb uops	29
loop length	97
used x86 registers	7
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.00	6.00	4.00	4.00	0.00	6.00	6.00	0.00
cycles	6.00	6.00	4.00	4.00	0.00	6.00	6.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Dispatch	6.00
Overall L1	8.25

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	66%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	40%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	17%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	12%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

4% of peak load performance is reached (6.30 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.25 to 6.00 cycles (1.38x speedup).

ASM code

In the binary file, the address of the loop is: 2d52

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
VMAXPS %XMM3,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0.25	N/A
MOV -0x3c(%RBP),%EDX	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
SUB %EAX,%EDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
CMP $0x2,%EDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JBE 2d88 <_Z7softmaxPKfPfS1_i+0x118>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
ADD -0x48(%RBP),%RAX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
INC %EDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
VMAXPS (%RDI,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	4	0.50	vect (25.0%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0.25	N/A
AND $-0x4,%EAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
AND $0x3,%EDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
VMOVHLPS %XMM0,%XMM0,%XMM1	1	0	0	0	0	1	0	1	1	vect (12.5%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM0,%XMM0,%XMM1	1	0	0	0	0	1	0	1	1	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
JE 2dad <_Z7softmaxPKfPfS1_i+0x13d>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
ADD %EAX,%ECX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
MOVSXD %ECX,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
VMAXSS (%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.50	0.50	0	0	4	0.50	scal (6.3%)
CMP %ECX,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JLE 2dad <_Z7softmaxPKfPfS1_i+0x13d>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
ADD $0x2,%ECX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
VMAXSS 0x4(%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.50	0.50	0	0	4	0.50	scal (6.3%)
CMP %ECX,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JL 2dad <_Z7softmaxPKfPfS1_i+0x13d>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
VMAXSS 0x8(%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.50	0.50	0	0	4	0.50	scal (6.3%)

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:47-48.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.25 to 5.75 cycles (1.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 52 bytes (13 single precision FP elements).

General properties

nb instructions	29
nb uops	29
loop length	97
used x86 registers	7
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.00	6.00	4.00	4.00	0.00	6.00	6.00	0.00
cycles	6.00	6.00	4.00	4.00	0.00	6.00	6.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Dispatch	6.00
Overall L1	8.25

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	66%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	40%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	17%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	12%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

4% of peak load performance is reached (6.30 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 2d52

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
VMAXPS %XMM3,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0.25	N/A
MOV -0x3c(%RBP),%EDX	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
SUB %EAX,%EDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
CMP $0x2,%EDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JBE 2d88 <_Z7softmaxPKfPfS1_i+0x118>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
ADD -0x48(%RBP),%RAX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
INC %EDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
VMAXPS (%RDI,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	4	0.50	vect (25.0%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0.25	N/A
AND $-0x4,%EAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
AND $0x3,%EDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
VMOVHLPS %XMM0,%XMM0,%XMM1	1	0	0	0	0	1	0	1	1	vect (12.5%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM0,%XMM0,%XMM1	1	0	0	0	0	1	0	1	1	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
JE 2dad <_Z7softmaxPKfPfS1_i+0x13d>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
ADD %EAX,%ECX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
MOVSXD %ECX,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
VMAXSS (%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.50	0.50	0	0	4	0.50	scal (6.3%)
CMP %ECX,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JLE 2dad <_Z7softmaxPKfPfS1_i+0x13d>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
ADD $0x2,%ECX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
VMAXSS 0x4(%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.50	0.50	0	0	4	0.50	scal (6.3%)
CMP %ECX,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JL 2dad <_Z7softmaxPKfPfS1_i+0x13d>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
VMAXSS 0x8(%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.50	0.50	0	0	4	0.50	scal (6.3%)

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code