OV - attention-gcc-skl256 - Loop 34

	Loop Id: 34	Module: attention-gcc-skl256	Source: attention_v2.cpp:43-61	Coverage: 0.18%

0x2d00 MOV	%R13D,%ECX

0x2d03 MOV	%R13D,%ESI

0x2d06 MOV	%R12,%RAX

0x2d09 SHR	$0x3,%ECX

0x2d0c MOV	%ECX,%EDX

0x2d0e SAL	$0x5,%RDX

0x2d12 ADD	%R12,%RDX

0x2d15 NOPL	(%RAX)

  (33) 0x2d18 VMAXPS	(%RAX),%YMM0,%YMM0

  (33) 0x2d1c ADD	$0x20,%RAX

  (33) 0x2d20 CMP	%RDX,%RAX

  (33) 0x2d23 JNE	2d18

0x2d25 VEXTRACTF32X4	$0x1,%YMM0,%XMM3

0x2d2c LEA	(,%RCX,8),%EAX

0x2d33 VMAXPS	%XMM0,%XMM3,%XMM1

0x2d37 VMOVHLPS	%XMM1,%XMM1,%XMM2

0x2d3b VMAXPS	%XMM1,%XMM2,%XMM2

0x2d3f VSHUFPS	$0x55,%XMM2,%XMM2,%XMM1

0x2d44 VMAXPS	%XMM2,%XMM1,%XMM1

0x2d48 CMP	%ESI,%EAX

0x2d4a JE	2dad

0x2dad MOVL	$0,-0x34(%RBP)

0x2db4 MOV	%R12,%R14

0x2db7 VMOVSS	%XMM1,-0x38(%RBP)

0x2dbc VZEROUPPER

0x2dbf NOP

  (31) 0x2dc0 VMOVSS	(%R14),%XMM0

  (31) 0x2dc5 ADD	$0x4,%R14

  (31) 0x2dc9 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

  (31) 0x2dce CALL	1110 <expf@plt>

  (31) 0x2dd3 VADDSS	-0x34(%RBP),%XMM0,%XMM5

  (31) 0x2dd8 VMOVSS	%XMM5,-0x34(%RBP)

  (31) 0x2ddd CMP	%RBX,%R14

  (31) 0x2de0 JNE	2dc0

0x2de2 MOV	-0x58(%RBP),%RAX

0x2de6 MOV	-0x48(%RBP),%RDI

0x2dea MOV	%R12,%R15

0x2ded LEA	(%RAX,%RDI,4),%R14

0x2df1 NOPL	(%RAX)

  (32) 0x2df8 VMOVSS	(%R15),%XMM0

  (32) 0x2dfd ADD	$0x4,%R15

  (32) 0x2e01 ADD	$0x4,%R14

  (32) 0x2e05 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

  (32) 0x2e0a CALL	1110 <expf@plt>

  (32) 0x2e0f VDIVSS	-0x34(%RBP),%XMM0,%XMM0

  (32) 0x2e14 VMOVSS	%XMM0,-0x4(%R14)

  (32) 0x2e1a CMP	%RBX,%R15

  (32) 0x2e1d JNE	2df8

0x2e1f MOV	-0x3c(%RBP),%EAX

0x2e22 MOV	-0x40(%RBP),%EDI

0x2e25 LEA	0x1(%RAX),%ECX

0x2e28 CMP	%ECX,%EDI

0x2e2a JE	2ea8

0x2e2c MOV	-0x78(%RBP),%RSI

0x2e30 MOV	-0x50(%RBP),%R15

0x2e34 INC	%R13

0x2e37 MOV	%EDI,%EAX

0x2e39 SUB	%R13D,%EAX

0x2e3c MOV	-0x70(%RBP),%R14

0x2e40 ADD	-0x68(%RBP),%R12

0x2e44 MOV	%ECX,-0x38(%RBP)

0x2e47 ADD	%RSI,-0x48(%RBP)

0x2e4b MOV	%R15,%RDI

0x2e4e LEA	0x4(,%RAX,4),%RDX

0x2e56 XOR	%ESI,%ESI

0x2e58 CALL	1050 <memset@plt>

0x2e5d MOV	-0x38(%RBP),%ECX

0x2e60 MOV	-0x60(%RBP),%RAX

0x2e64 ADD	%R14,%R15

0x2e67 VMOVSS	-0x34(%RBP),%XMM2

0x2e6c ADD	%R14,%RBX

0x2e6f VBROADCASTSS	0x118c(%RIP),%YMM0

0x2e78 MOV	%R15,-0x50(%RBP)

0x2e7c MOV	%ECX,-0x3c(%RBP)

0x2e7f VMOVSS	%XMM2,-0x8(%RAX,%R13,4)

0x2e86 CMPL	$0x6,-0x3c(%RBP)

0x2e8a JG	2d00

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Source Location	Module
►100.00+	main	attention_v2.cpp:283	attention-gcc-skl256
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	main	new_allocator.h:183	attention-gcc-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.39
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.91
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:43-43,attention_v2.cpp:46-47,attention_v2.cpp:50-52,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.25
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	15.25
CQA cycles if fully vectorized	1.43
Front-end cycles	15.25
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	8.00
P5 cycles	6.50
P6 cycles	6.50
P7 cycles	7.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	61.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.13
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	22.58
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	43.75
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.71
Vector-efficiency ratio store	8.04
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.84

Metric	Value
CQA speedup if no scalar integer	3.39
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.91
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:43-43,attention_v2.cpp:46-47,attention_v2.cpp:50-52,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.25
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	15.25
CQA cycles if fully vectorized	1.43
Front-end cycles	15.25
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	8.00
P5 cycles	6.50
P6 cycles	6.50
P7 cycles	7.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	61.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.13
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	22.58
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	43.75
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.71
Vector-efficiency ratio store	8.04
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.84

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:43,46-47,50-52,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.25 to 4.50 cycles (3.39x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

memset@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:58
VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:50

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF32X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 88 bytes (22 single precision FP elements). The binary loop is storing 36 bytes (9 single precision FP elements).

General properties

nb instructions	56
nb uops	61
loop length	217
used x86 registers	11
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.50	6.50	7.33	7.33	8.00	6.50	6.50	7.33
cycles	6.50	6.50	7.33	7.33	8.00	6.50	6.50	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Dispatch	8.00
Overall L1	15.25

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	60%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	22%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Vector efficiency ratios

INT

all	10%
load	12%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	12%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.25 cycles. At this rate:

4% of peak load performance is reached (5.77 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.36 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.25 to 8.00 cycles (1.91x speedup).

ASM code

In the binary file, the address of the loop is: 2dad

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %R13D,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SHR $0x3,%ECX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0x5,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
ADD %R12,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF32X4 $0x1,%YMM0,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
LEA (,%RCX,8),%EAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMAXPS %XMM0,%XMM3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVHLPS %XMM1,%XMM1,%XMM2	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXPS %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM2,%XMM2,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM2,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
CMP %ESI,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 2dad <_Z7softmaxPKfPfS1_i+0x13d>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
MOV %R12,%R14	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
VMOVSS %XMM1,-0x38(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
NOP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
LEA (%RAX,%RDI,4),%R14	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x3c(%RBP),%EAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x40(%RBP),%EDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RAX),%ECX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP %ECX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 2ea8 <_Z7softmaxPKfPfS1_i+0x238>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x50(%RBP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SUB %R13D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD -0x68(%RBP),%R12	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %ECX,-0x38(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD %RSI,-0x48(%RBP)	2	0.25	0.25	0.83	0.83	1	0.25	0.25	0.33	5	1	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CALL 1050 <memset@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R14,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
ADD %R14,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VBROADCASTSS 0x118c(%RIP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
MOV %R15,-0x50(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %ECX,-0x3c(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VMOVSS %XMM2,-0x8(%RAX,%R13,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
CMPL $0x6,-0x3c(%RBP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JG 2d00 <_Z7softmaxPKfPfS1_i+0x90>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-skl256

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.25 to 4.50 cycles (3.39x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

memset@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:58
VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:50

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF32X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:47

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	56
nb uops	61
loop length	217
used x86 registers	11
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.50	6.50	7.33	7.33	8.00	6.50	6.50	7.33
cycles	6.50	6.50	7.33	7.33	8.00	6.50	6.50	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Dispatch	8.00
Overall L1	15.25

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	60%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	22%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Vector efficiency ratios

INT

all	10%
load	12%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	12%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.25 cycles. At this rate:

4% of peak load performance is reached (5.77 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.36 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 2dad

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %R13D,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SHR $0x3,%ECX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0x5,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
ADD %R12,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF32X4 $0x1,%YMM0,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
LEA (,%RCX,8),%EAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMAXPS %XMM0,%XMM3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVHLPS %XMM1,%XMM1,%XMM2	1	0	0	0	0	0	1	0	0	1	1	vect (12.5%)
VMAXPS %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM2,%XMM2,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VMAXPS %XMM2,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
CMP %ESI,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 2dad <_Z7softmaxPKfPfS1_i+0x13d>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
MOV %R12,%R14	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
VMOVSS %XMM1,-0x38(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
NOP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
LEA (%RAX,%RDI,4),%R14	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x3c(%RBP),%EAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x40(%RBP),%EDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RAX),%ECX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP %ECX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JE 2ea8 <_Z7softmaxPKfPfS1_i+0x238>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x50(%RBP),%R15	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SUB %R13D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD -0x68(%RBP),%R12	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %ECX,-0x38(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD %RSI,-0x48(%RBP)	2	0.25	0.25	0.83	0.83	1	0.25	0.25	0.33	5	1	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CALL 1050 <memset@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R14,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
ADD %R14,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VBROADCASTSS 0x118c(%RIP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
MOV %R15,-0x50(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %ECX,-0x3c(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VMOVSS %XMM2,-0x8(%RAX,%R13,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
CMPL $0x6,-0x3c(%RBP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JG 2d00 <_Z7softmaxPKfPfS1_i+0x90>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code