| Loop Id: 3 | Module: attention-gcc-skl256 | Source: random.tcc:404-3558 [...] | Coverage: 0.44% |
|---|
| Loop Id: 3 | Module: attention-gcc-skl256 | Source: random.tcc:404-3558 [...] | Coverage: 0.44% |
|---|
0x1c58 LEA 0x1(%RDX),%RAX |
0x1c5c MOV -0x2750(%RBP,%RDX,8),%RDX |
0x1c64 VMOVSS 0x23a0(%RIP),%XMM7 |
0x1c6c MOV %RAX,-0x13d0(%RBP) |
0x1c73 MOV %RDX,%RSI |
0x1c76 SHR $0xb,%RSI |
0x1c7a MOV %ESI,%ESI |
0x1c7c XOR %RSI,%RDX |
0x1c7f MOV %RDX,%RSI |
0x1c82 SAL $0x7,%RSI |
0x1c86 AND $-0x62d3a980,%ESI |
0x1c8c XOR %RSI,%RDX |
0x1c8f MOV %RDX,%RSI |
0x1c92 SAL $0xf,%RSI |
0x1c96 AND $-0x103a0000,%ESI |
0x1c9c XOR %RSI,%RDX |
0x1c9f MOV %RDX,%RSI |
0x1ca2 SHR $0x12,%RSI |
0x1ca6 XOR %RSI,%RDX |
0x1ca9 VCVTUSI2SS %EDX,%XMM2,%XMM0 |
0x1caf VMULSS 0x2351(%RIP),%XMM0,%XMM0 |
0x1cb7 VCOMISS %XMM0,%XMM7 |
0x1cbb JA 1d19 |
0x1cbd MOV %RAX,%RDX |
0x1cc0 CMP $0x26f,%RAX |
0x1cc6 JBE 1c58 |
0x1cc8 MOV %R8,-0x27a8(%RBP) |
0x1ccf LEA -0x2750(%RBP),%RDI |
0x1cd6 MOV %R9,-0x27a0(%RBP) |
0x1cdd MOV %RCX,-0x2798(%RBP) |
0x1ce4 VZEROUPPER |
0x1ce7 CALL 3380 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv> |
0x1cec MOV -0x13d0(%RBP),%RDX |
0x1cf3 MOV -0x27a8(%RBP),%R8 |
0x1cfa MOV -0x27a0(%RBP),%R9 |
0x1d01 MOV -0x2798(%RBP),%RCX |
0x1d08 VXORPS %XMM2,%XMM2,%XMM2 |
0x1d0c VMOVDQA 0x252c(%RIP),%YMM6 |
0x1d14 JMP 1c58 |
0x1d19 MOV -0x27f0(%RBP),%RDI |
0x1d20 MOV %RCX,-0x2798(%RBP) |
0x1d27 MOV %R9,-0x27a0(%RBP) |
0x1d2e MOV %R8,-0x27a8(%RBP) |
0x1d35 VMOVSS %XMM0,(%RDI) |
0x1d39 JMP 1da5 |
(26) 0x1d40 LEA 0x1(%RDX),%RAX |
(26) 0x1d44 MOV -0x2750(%RBP,%RDX,8),%RDX |
(26) 0x1d4c VMOVSS 0x22b8(%RIP),%XMM7 |
(26) 0x1d54 MOV %RAX,-0x13d0(%RBP) |
(26) 0x1d5b MOV %RDX,%RCX |
(26) 0x1d5e SHR $0xb,%RCX |
(26) 0x1d62 MOV %ECX,%ECX |
(26) 0x1d64 XOR %RCX,%RDX |
(26) 0x1d67 MOV %RDX,%RCX |
(26) 0x1d6a SAL $0x7,%RCX |
(26) 0x1d6e AND $-0x62d3a980,%ECX |
(26) 0x1d74 XOR %RCX,%RDX |
(26) 0x1d77 MOV %RDX,%RCX |
(26) 0x1d7a SAL $0xf,%RCX |
(26) 0x1d7e AND $-0x103a0000,%ECX |
(26) 0x1d84 XOR %RCX,%RDX |
(26) 0x1d87 MOV %RDX,%RCX |
(26) 0x1d8a SHR $0x12,%RCX |
(26) 0x1d8e XOR %RCX,%RDX |
(26) 0x1d91 VCVTUSI2SS %EDX,%XMM2,%XMM0 |
(26) 0x1d97 VMULSS 0x2269(%RIP),%XMM0,%XMM0 |
(26) 0x1d9f VCOMISS %XMM0,%XMM7 |
(26) 0x1da3 JA 1dd7 |
(26) 0x1da5 MOV %RAX,%RDX |
(26) 0x1da8 CMP $0x26f,%RAX |
(26) 0x1dae JBE 1d40 |
(26) 0x1db0 LEA -0x2750(%RBP),%RDI |
(26) 0x1db7 VZEROUPPER |
(26) 0x1dba CALL 3380 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv> |
(26) 0x1dbf MOV -0x13d0(%RBP),%RDX |
(26) 0x1dc6 VMOVDQA 0x2472(%RIP),%YMM6 |
(26) 0x1dce VXORPS %XMM2,%XMM2,%XMM2 |
(26) 0x1dd2 JMP 1d40 |
0x1dd7 MOV $0x1,%EDX |
0x1ddc MOV -0x2800(%RBP),%RDI |
0x1de3 MOV -0x2798(%RBP),%RCX |
0x1dea VPBROADCASTQ %RDX,%YMM8 |
0x1df0 MOV $-0x80000000,%RDX |
0x1df7 MOV -0x27a0(%RBP),%R9 |
0x1dfe MOV -0x27a8(%RBP),%R8 |
0x1e05 VPBROADCASTQ %RDX,%YMM9 |
0x1e0b MOV $0x7fffffff,%EDX |
0x1e10 VMOVSS %XMM0,(%RDI) |
0x1e14 VMOVDQA %YMM8,%YMM3 |
0x1e18 VPBROADCASTQ %RDX,%YMM7 |
0x1e1e VMOVDQA %YMM9,%YMM4 |
0x1e22 VMOVDQA %YMM7,%YMM5 |
0x1e26 JMP 1e91 |
(23) 0x1e30 MOV -0x2750(%RBP,%RAX,8),%RSI |
(23) 0x1e38 INC %RAX |
(23) 0x1e3b MOV %RSI,%RDX |
(23) 0x1e3e VMOVSS 0x21c6(%RIP),%XMM1 |
(23) 0x1e46 SHR $0xb,%RDX |
(23) 0x1e4a MOV %EDX,%EDX |
(23) 0x1e4c XOR %RSI,%RDX |
(23) 0x1e4f MOV %RDX,%RSI |
(23) 0x1e52 SAL $0x7,%RSI |
(23) 0x1e56 AND $-0x62d3a980,%ESI |
(23) 0x1e5c XOR %RSI,%RDX |
(23) 0x1e5f MOV %RDX,%RSI |
(23) 0x1e62 SAL $0xf,%RSI |
(23) 0x1e66 AND $-0x103a0000,%ESI |
(23) 0x1e6c XOR %RSI,%RDX |
(23) 0x1e6f MOV %RDX,%RSI |
(23) 0x1e72 SHR $0x12,%RSI |
(23) 0x1e76 XOR %RSI,%RDX |
(23) 0x1e79 VCVTUSI2SS %EDX,%XMM2,%XMM0 |
(23) 0x1e7f VMULSS 0x2181(%RIP),%XMM0,%XMM0 |
(23) 0x1e87 VCOMISS %XMM0,%XMM1 |
(23) 0x1e8b JA 1ffb |
(23) 0x1e91 CMP $0x26f,%RAX |
(23) 0x1e97 JBE 1e30 |
(23) 0x1e99 LEA -0x2750(%RBP),%RAX |
(24) 0x1ea0 VPANDQ (%RAX),%YMM4,%YMM1 |
(24) 0x1ea6 VMOVDQA %YMM5,%YMM0 |
(24) 0x1eaa ADD $0x20,%RAX |
(24) 0x1eae VPTERNLOGQ $-0x14,-0x18(%RAX),%YMM1,%YMM0 |
(24) 0x1eb9 VPSRLQ $0x1,%YMM0,%YMM1 |
(24) 0x1ebe VPANDQ %YMM3,%YMM0,%YMM0 |
(24) 0x1ec4 VPMULLQ %YMM6,%YMM0,%YMM0 |
(24) 0x1eca VPTERNLOGQ $-0x6a,0xc48(%RAX),%YMM0,%YMM1 |
(24) 0x1ed5 VMOVDQA %YMM1,-0x20(%RAX) |
(24) 0x1eda CMP %RAX,%RBX |
(24) 0x1edd JNE 1ea0 |
(23) 0x1edf MOV -0x2040(%RBP),%RDX |
(23) 0x1ee6 MOV -0x2038(%RBP),%RAX |
(23) 0x1eed VMOVDQA %XMM7,%XMM0 |
(23) 0x1ef1 VPANDQ -0x2050(%RBP),%XMM9,%XMM1 |
(23) 0x1efb AND $-0x80000000,%RDX |
(23) 0x1f02 AND $0x7fffffff,%EAX |
(23) 0x1f07 OR %RDX,%RAX |
(23) 0x1f0a VPTERNLOGQ $-0x14,-0x2048(%RBP),%XMM1,%XMM0 |
(23) 0x1f15 MOV %RAX,%RDX |
(23) 0x1f18 VPSRLQ $0x1,%XMM0,%XMM1 |
(23) 0x1f1d VPANDQ %XMM8,%XMM0,%XMM0 |
(23) 0x1f23 AND $0x1,%EAX |
(23) 0x1f26 SHR $0x1,%RDX |
(23) 0x1f29 NEG %RAX |
(23) 0x1f2c VPMULLQ -0x27d0(%RBP),%XMM0,%XMM0 |
(23) 0x1f36 VPTERNLOGQ $-0x6a,-0x13e8(%RBP),%XMM0,%XMM1 |
(23) 0x1f41 XOR -0x13d8(%RBP),%RDX |
(23) 0x1f48 AND $-0x66f74f21,%EAX |
(23) 0x1f4d VMOVDQA %XMM1,-0x2050(%RBP) |
(23) 0x1f55 XOR %RDX,%RAX |
(23) 0x1f58 LEA -0x13d8(%RBP),%RDX |
(23) 0x1f5f MOV %RAX,-0x2040(%RBP) |
(23) 0x1f66 LEA -0x2038(%RBP),%RAX |
(23) 0x1f6d NOPL (%RAX) |
(25) 0x1f70 VPANDQ (%RAX),%YMM4,%YMM1 |
(25) 0x1f76 VMOVDQA %YMM5,%YMM0 |
(25) 0x1f7a ADD $0x20,%RAX |
(25) 0x1f7e VPTERNLOGQ $-0x14,-0x18(%RAX),%YMM1,%YMM0 |
(25) 0x1f89 VPSRLQ $0x1,%YMM0,%YMM1 |
(25) 0x1f8e VPANDQ %YMM3,%YMM0,%YMM0 |
(25) 0x1f94 VPMULLQ %YMM6,%YMM0,%YMM0 |
(25) 0x1f9a VPTERNLOGQ $-0x6a,-0x738(%RAX),%YMM0,%YMM1 |
(25) 0x1fa5 VMOVDQU %YMM1,-0x20(%RAX) |
(25) 0x1faa CMP %RDX,%RAX |
(25) 0x1fad JNE 1f70 |
(23) 0x1faf MOV -0x2750(%RBP),%RSI |
(23) 0x1fb6 MOV -0x13d8(%RBP),%RAX |
(23) 0x1fbd MOV %RSI,%RDX |
(23) 0x1fc0 AND $-0x80000000,%RAX |
(23) 0x1fc6 AND $0x7fffffff,%EDX |
(23) 0x1fcc OR %RDX,%RAX |
(23) 0x1fcf MOV %RAX,%RDX |
(23) 0x1fd2 AND $0x1,%EAX |
(23) 0x1fd5 SHR $0x1,%RDX |
(23) 0x1fd8 NEG %RAX |
(23) 0x1fdb XOR -0x1af0(%RBP),%RDX |
(23) 0x1fe2 AND $-0x66f74f21,%EAX |
(23) 0x1fe7 XOR %RDX,%RAX |
(23) 0x1fea MOV %RAX,-0x13d8(%RBP) |
(23) 0x1ff1 MOV $0x1,%EAX |
(23) 0x1ff6 JMP 1e3b |
0x1ffb MOV -0x27f8(%RBP),%RDI |
0x2002 ADDQ $0x4,-0x2800(%RBP) |
0x200a ADDQ $0x4,-0x27f0(%RBP) |
0x2012 VMOVSS %XMM0,(%RDI) |
0x2016 ADD $0x4,%RDI |
0x201a MOV %RAX,-0x13d0(%RBP) |
0x2021 MOV %RDI,-0x27f8(%RBP) |
0x2028 CMP -0x2850(%RBP),%RDI |
0x202f JNE 1cbd |
/home/eoseret/Applications/llm-attention/attention_v2.cpp: 164 - 167 |
-------------------------------------------------------------------------------- |
164: for (size_t i = 0; i < elemsW; ++i) { |
165: h_WQ[i] = dist(rng); |
166: h_WK[i] = dist(rng); |
167: h_WV[i] = dist(rng); |
/usr/include/c++/16.1.1/bits/random.tcc: 404 - 3558 |
-------------------------------------------------------------------------------- |
404: for (size_t __k = 0; __k < (__n - __m); ++__k) |
405: { |
406: _UIntType __y = ((_M_x[__k] & __upper_mask) |
407: | (_M_x[__k + 1] & __lower_mask)); |
408: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
409: ^ ((__y & 0x01) ? __a : 0)); |
410: } |
411: |
412: for (size_t __k = (__n - __m); __k < (__n - 1); ++__k) |
413: { |
414: _UIntType __y = ((_M_x[__k] & __upper_mask) |
415: | (_M_x[__k + 1] & __lower_mask)); |
416: _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1) |
417: ^ ((__y & 0x01) ? __a : 0)); |
418: } |
419: |
420: _UIntType __y = ((_M_x[__n - 1] & __upper_mask) |
421: | (_M_x[0] & __lower_mask)); |
422: _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1) |
423: ^ ((__y & 0x01) ? __a : 0)); |
[...] |
458: if (_M_p >= state_size) |
459: _M_gen_rand(); |
460: |
461: // Calculate o(x(i)). |
462: result_type __z = _M_x[_M_p++]; |
463: __z ^= (__z >> __u) & __d; |
464: __z ^= (__z << __s) & __b; |
465: __z ^= (__z << __t) & __c; |
466: __z ^= (__z >> __l); |
[...] |
3519: __generate_canonical_pow2(_Urbg& __urng) |
[...] |
3557: const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd); |
3558: if (__ret < _RealT(1.0)) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | main | new_allocator.h:183 | attention-gcc-skl256 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.68 |
| CQA speedup if FP arith vectorized | 1.33 |
| CQA speedup if fully vectorized | 10.62 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.25 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:164-167,random.tcc:406-409,random.tcc:458-459,random.tcc:462-466,random.tcc:3519-3519,random.tcc:3557-3558 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 18.75 |
| CQA cycles if no scalar integer | 7.00 |
| CQA cycles if FP arith vectorized | 14.06 |
| CQA cycles if fully vectorized | 1.77 |
| Front-end cycles | 18.75 |
| P0 cycles | 8.25 |
| P1 cycles | 8.25 |
| P2 cycles | 10.83 |
| P3 cycles | 10.50 |
| P4 cycles | 15.00 |
| P5 cycles | 8.25 |
| P6 cycles | 8.25 |
| P7 cycles | 10.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 69.00 |
| Nb uops | 75.00 |
| Nb loads | 17.00 |
| Nb stores | 14.00 |
| Nb stack references | 9.00 |
| FLOP/cycle | 0.05 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 13.44 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 152.00 |
| Bytes stored | 100.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 13.33 |
| Vectorization ratio load | 9.09 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 22.73 |
| Vector-efficiency ratio all | 15.00 |
| Vector-efficiency ratio load | 14.77 |
| Vector-efficiency ratio store | 11.16 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 17.33 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.68 |
| CQA speedup if FP arith vectorized | 1.33 |
| CQA speedup if fully vectorized | 10.62 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.25 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:164-167,random.tcc:406-409,random.tcc:458-459,random.tcc:462-466,random.tcc:3519-3519,random.tcc:3557-3558 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 18.75 |
| CQA cycles if no scalar integer | 7.00 |
| CQA cycles if FP arith vectorized | 14.06 |
| CQA cycles if fully vectorized | 1.77 |
| Front-end cycles | 18.75 |
| P0 cycles | 8.25 |
| P1 cycles | 8.25 |
| P2 cycles | 10.83 |
| P3 cycles | 10.50 |
| P4 cycles | 15.00 |
| P5 cycles | 8.25 |
| P6 cycles | 8.25 |
| P7 cycles | 10.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 69.00 |
| Nb uops | 75.00 |
| Nb loads | 17.00 |
| Nb stores | 14.00 |
| Nb stack references | 9.00 |
| FLOP/cycle | 0.05 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 13.44 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 152.00 |
| Bytes stored | 100.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 13.33 |
| Vectorization ratio load | 9.09 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 22.73 |
| Vector-efficiency ratio all | 15.00 |
| Vector-efficiency ratio load | 14.77 |
| Vector-efficiency ratio store | 11.16 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 17.33 |
| Path / |
| Function | main |
| Source file and lines | random.tcc:404-3558 |
| Module | attention-gcc-skl256 |
| nb instructions | 69 |
| nb uops | 75 |
| loop length | 366 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 7 |
| used zmm registers | 0 |
| nb stack references | 9 |
| micro-operation queue | 18.75 cycles |
| front end | 18.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 8.25 | 8.25 | 10.83 | 10.50 | 15.00 | 8.25 | 8.25 | 10.67 |
| cycles | 8.25 | 8.25 | 10.83 | 10.50 | 15.00 | 8.25 | 8.25 | 10.67 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 18.75 |
| Dispatch | 15.00 |
| Overall L1 | 18.75 |
| all | 13% |
| load | 11% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 20% |
| all | 14% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 13% |
| load | 9% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 22% |
| all | 16% |
| load | 16% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 17% |
| all | 8% |
| load | 6% |
| store | 6% |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 15% |
| all | 15% |
| load | 14% |
| store | 11% |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 17% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LEA 0x1(%RDX),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| MOV -0x2750(%RBP,%RDX,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVSS 0x23a0(%RIP),%XMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| MOV %RAX,-0x13d0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0xb,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SAL $0x7,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x62d3a980,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SAL $0xf,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x103a0000,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0x12,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VCVTUSI2SS %EDX,%XMM2,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 | scal (6.3%) |
| VMULSS 0x2351(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VCOMISS %XMM0,%XMM7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| JA 1d19 <main+0x9d9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| CMP $0x26f,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| JBE 1c58 <main+0x918> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| MOV %R8,-0x27a8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| LEA -0x2750(%RBP),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| MOV %R9,-0x27a0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %RCX,-0x2798(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
| CALL 3380 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 | N/A |
| MOV -0x13d0(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| MOV -0x27a8(%RBP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| MOV -0x27a0(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| MOV -0x2798(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| VXORPS %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| VMOVDQA 0x252c(%RIP),%YMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 | vect (50.0%) |
| JMP 1c58 <main+0x918> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| MOV -0x27f0(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| MOV %RCX,-0x2798(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %R9,-0x27a0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %R8,-0x27a8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| VMOVSS %XMM0,(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| JMP 1da5 <main+0xa65> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| MOV $0x1,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV -0x2800(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| MOV -0x2798(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| VPBROADCASTQ %RDX,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (12.5%) |
| MOV $-0x80000000,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV -0x27a0(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| MOV -0x27a8(%RBP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| VPBROADCASTQ %RDX,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (12.5%) |
| MOV $0x7fffffff,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VMOVSS %XMM0,(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| VMOVDQA %YMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| VPBROADCASTQ %RDX,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (12.5%) |
| VMOVDQA %YMM9,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| VMOVDQA %YMM7,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| JMP 1e91 <main+0xb51> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| MOV -0x27f8(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| ADDQ $0x4,-0x2800(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 | scal (12.5%) |
| ADDQ $0x4,-0x27f0(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 | scal (12.5%) |
| VMOVSS %XMM0,(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| ADD $0x4,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RAX,-0x13d0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %RDI,-0x27f8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| CMP -0x2850(%RBP),%RDI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | N/A |
| JNE 1cbd <main+0x97d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| Function | main |
| Source file and lines | random.tcc:404-3558 |
| Module | attention-gcc-skl256 |
| nb instructions | 69 |
| nb uops | 75 |
| loop length | 366 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 7 |
| used zmm registers | 0 |
| nb stack references | 9 |
| micro-operation queue | 18.75 cycles |
| front end | 18.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 8.25 | 8.25 | 10.83 | 10.50 | 15.00 | 8.25 | 8.25 | 10.67 |
| cycles | 8.25 | 8.25 | 10.83 | 10.50 | 15.00 | 8.25 | 8.25 | 10.67 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 18.75 |
| Dispatch | 15.00 |
| Overall L1 | 18.75 |
| all | 13% |
| load | 11% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 20% |
| all | 14% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 13% |
| load | 9% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 22% |
| all | 16% |
| load | 16% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 17% |
| all | 8% |
| load | 6% |
| store | 6% |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 15% |
| all | 15% |
| load | 14% |
| store | 11% |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 17% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LEA 0x1(%RDX),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| MOV -0x2750(%RBP,%RDX,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVSS 0x23a0(%RIP),%XMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (6.3%) |
| MOV %RAX,-0x13d0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0xb,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SAL $0x7,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x62d3a980,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SAL $0xf,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x103a0000,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0x12,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VCVTUSI2SS %EDX,%XMM2,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 | scal (6.3%) |
| VMULSS 0x2351(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VCOMISS %XMM0,%XMM7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| JA 1d19 <main+0x9d9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| CMP $0x26f,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| JBE 1c58 <main+0x918> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| MOV %R8,-0x27a8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| LEA -0x2750(%RBP),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| MOV %R9,-0x27a0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %RCX,-0x2798(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
| CALL 3380 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 | N/A |
| MOV -0x13d0(%RBP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| MOV -0x27a8(%RBP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| MOV -0x27a0(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| MOV -0x2798(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| VXORPS %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| VMOVDQA 0x252c(%RIP),%YMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 | vect (50.0%) |
| JMP 1c58 <main+0x918> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| MOV -0x27f0(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| MOV %RCX,-0x2798(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %R9,-0x27a0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %R8,-0x27a8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| VMOVSS %XMM0,(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| JMP 1da5 <main+0xa65> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| MOV $0x1,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV -0x2800(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| MOV -0x2798(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| VPBROADCASTQ %RDX,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (12.5%) |
| MOV $-0x80000000,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV -0x27a0(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| MOV -0x27a8(%RBP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| VPBROADCASTQ %RDX,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (12.5%) |
| MOV $0x7fffffff,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VMOVSS %XMM0,(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| VMOVDQA %YMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| VPBROADCASTQ %RDX,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (12.5%) |
| VMOVDQA %YMM9,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| VMOVDQA %YMM7,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| JMP 1e91 <main+0xb51> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| MOV -0x27f8(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| ADDQ $0x4,-0x2800(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 | scal (12.5%) |
| ADDQ $0x4,-0x27f0(%RBP) | 2 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 | scal (12.5%) |
| VMOVSS %XMM0,(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| ADD $0x4,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RAX,-0x13d0(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV %RDI,-0x27f8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| CMP -0x2850(%RBP),%RDI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | N/A |
| JNE 1cbd <main+0x97d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
