OV - attention-gcc-skl256 - Loop 23

	Loop Id: 23	Module: attention-gcc-skl256	Source: random.tcc:404-3558 [...]	Coverage: 0.20%

0x1e30 MOV	-0x2750(%RBP,%RAX,8),%RSI

0x1e38 INC	%RAX

0x1e3b MOV	%RSI,%RDX

0x1e3e VMOVSS	0x21c6(%RIP),%XMM1

0x1e46 SHR	$0xb,%RDX

0x1e4a MOV	%EDX,%EDX

0x1e4c XOR	%RSI,%RDX

0x1e4f MOV	%RDX,%RSI

0x1e52 SAL	$0x7,%RSI

0x1e56 AND	$-0x62d3a980,%ESI

0x1e5c XOR	%RSI,%RDX

0x1e5f MOV	%RDX,%RSI

0x1e62 SAL	$0xf,%RSI

0x1e66 AND	$-0x103a0000,%ESI

0x1e6c XOR	%RSI,%RDX

0x1e6f MOV	%RDX,%RSI

0x1e72 SHR	$0x12,%RSI

0x1e76 XOR	%RSI,%RDX

0x1e79 VCVTUSI2SS	%EDX,%XMM2,%XMM0

0x1e7f VMULSS	0x2181(%RIP),%XMM0,%XMM0

0x1e87 VCOMISS	%XMM0,%XMM1

0x1e8b JA	1ffb

0x1e91 CMP	$0x26f,%RAX

0x1e97 JBE	1e30

0x1e99 LEA	-0x2750(%RBP),%RAX

  (24) 0x1ea0 VPANDQ	(%RAX),%YMM4,%YMM1

  (24) 0x1ea6 VMOVDQA	%YMM5,%YMM0

  (24) 0x1eaa ADD	$0x20,%RAX

  (24) 0x1eae VPTERNLOGQ	$-0x14,-0x18(%RAX),%YMM1,%YMM0

  (24) 0x1eb9 VPSRLQ	$0x1,%YMM0,%YMM1

  (24) 0x1ebe VPANDQ	%YMM3,%YMM0,%YMM0

  (24) 0x1ec4 VPMULLQ	%YMM6,%YMM0,%YMM0

  (24) 0x1eca VPTERNLOGQ	$-0x6a,0xc48(%RAX),%YMM0,%YMM1

  (24) 0x1ed5 VMOVDQA	%YMM1,-0x20(%RAX)

  (24) 0x1eda CMP	%RAX,%RBX

  (24) 0x1edd JNE	1ea0

0x1edf MOV	-0x2040(%RBP),%RDX

0x1ee6 MOV	-0x2038(%RBP),%RAX

0x1eed VMOVDQA	%XMM7,%XMM0

0x1ef1 VPANDQ	-0x2050(%RBP),%XMM9,%XMM1

0x1efb AND	$-0x80000000,%RDX

0x1f02 AND	$0x7fffffff,%EAX

0x1f07 OR	%RDX,%RAX

0x1f0a VPTERNLOGQ	$-0x14,-0x2048(%RBP),%XMM1,%XMM0

0x1f15 MOV	%RAX,%RDX

0x1f18 VPSRLQ	$0x1,%XMM0,%XMM1

0x1f1d VPANDQ	%XMM8,%XMM0,%XMM0

0x1f23 AND	$0x1,%EAX

0x1f26 SHR	$0x1,%RDX

0x1f29 NEG	%RAX

0x1f2c VPMULLQ	-0x27d0(%RBP),%XMM0,%XMM0

0x1f36 VPTERNLOGQ	$-0x6a,-0x13e8(%RBP),%XMM0,%XMM1

0x1f41 XOR	-0x13d8(%RBP),%RDX

0x1f48 AND	$-0x66f74f21,%EAX

0x1f4d VMOVDQA	%XMM1,-0x2050(%RBP)

0x1f55 XOR	%RDX,%RAX

0x1f58 LEA	-0x13d8(%RBP),%RDX

0x1f5f MOV	%RAX,-0x2040(%RBP)

0x1f66 LEA	-0x2038(%RBP),%RAX

0x1f6d NOPL	(%RAX)

  (25) 0x1f70 VPANDQ	(%RAX),%YMM4,%YMM1

  (25) 0x1f76 VMOVDQA	%YMM5,%YMM0

  (25) 0x1f7a ADD	$0x20,%RAX

  (25) 0x1f7e VPTERNLOGQ	$-0x14,-0x18(%RAX),%YMM1,%YMM0

  (25) 0x1f89 VPSRLQ	$0x1,%YMM0,%YMM1

  (25) 0x1f8e VPANDQ	%YMM3,%YMM0,%YMM0

  (25) 0x1f94 VPMULLQ	%YMM6,%YMM0,%YMM0

  (25) 0x1f9a VPTERNLOGQ	$-0x6a,-0x738(%RAX),%YMM0,%YMM1

  (25) 0x1fa5 VMOVDQU	%YMM1,-0x20(%RAX)

  (25) 0x1faa CMP	%RDX,%RAX

  (25) 0x1fad JNE	1f70

0x1faf MOV	-0x2750(%RBP),%RSI

0x1fb6 MOV	-0x13d8(%RBP),%RAX

0x1fbd MOV	%RSI,%RDX

0x1fc0 AND	$-0x80000000,%RAX

0x1fc6 AND	$0x7fffffff,%EDX

0x1fcc OR	%RDX,%RAX

0x1fcf MOV	%RAX,%RDX

0x1fd2 AND	$0x1,%EAX

0x1fd5 SHR	$0x1,%RDX

0x1fd8 NEG	%RAX

0x1fdb XOR	-0x1af0(%RBP),%RDX

0x1fe2 AND	$-0x66f74f21,%EAX

0x1fe7 XOR	%RDX,%RAX

0x1fea MOV	%RAX,-0x13d8(%RBP)

0x1ff1 MOV	$0x1,%EAX

0x1ff6 JMP	1e3b

/usr/include/c++/16.1.1/bits/random.tcc: 404 - 3558

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3557: 	  const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd);

3558: 	  if (__ret < _RealT(1.0))

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	main	new_allocator.h:183	attention-gcc-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.33
CQA speedup if FP arith vectorized	2.17
CQA speedup if fully vectorized	11.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks
Function	main
Source	random.tcc:404-409,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.63
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.36
CQA cycles if fully vectorized	1.06
Front-end cycles	11.63
P0 cycles	8.08
P1 cycles	8.13
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	1.50
P5 cycles	8.17
P6 cycles	8.13
P7 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.50
Nb uops	46.50
Nb loads	7.50
Nb stores	1.50
Nb stack references	4.50
FLOP/cycle	0.09
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.74
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	10.00
Vectorization ratio load	20.00
Vectorization ratio store	33.33
Vectorization ratio mul	25.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	9.38
Vector-efficiency ratio all	12.03
Vector-efficiency ratio load	12.29
Vector-efficiency ratio store	16.67
Vector-efficiency ratio mul	10.94
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.17

Metric	Value
CQA speedup if no scalar integer	2.16
CQA speedup if FP arith vectorized	2.19
CQA speedup if fully vectorized	10.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.25
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	7.88
CQA cycles if fully vectorized	1.66
Front-end cycles	17.25
P0 cycles	11.92
P1 cycles	12.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	3.00
P5 cycles	12.08
P6 cycles	12.00
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	69.00
Nb loads	12.00
Nb stores	3.00
Nb stack references	9.00
FLOP/cycle	0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.81
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	20.00
Vectorization ratio load	40.00
Vectorization ratio store	33.33
Vectorization ratio mul	50.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.75
Vector-efficiency ratio all	13.75
Vector-efficiency ratio load	16.25
Vector-efficiency ratio store	16.67
Vector-efficiency ratio mul	15.63
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.67

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	2.12
CQA speedup if fully vectorized	13.24
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.84
CQA cycles if fully vectorized	0.45
Front-end cycles	6.00
P0 cycles	4.25
P1 cycles	4.25
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	0.00
P5 cycles	4.25
P6 cycles	4.25
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	3.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.17
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.67
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.31
Vector-efficiency ratio load	8.33
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.66

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-gcc-skl256

The loop is defined in /usr/include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558.

Analyzed code is defined in /usr/include/c++/16.1.1/bits/random.tcc:404-409,420-423,458,462-466,3557-3558.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.63 to 1.06 cycles (11.00x speedup).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
25% of SSE/AVX multiply instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 0 occurrences
VPMULLQ: 0 occurrences
VPTERNLOGQ: 0 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 68 bytes (17 single precision FP elements). The binary loop is storing 16 bytes (4 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	43.50
nb uops	46.50
loop length	213.50
used x86 registers	4
used mmx registers	0
used xmm registers	4.50
used ymm registers	0
used zmm registers	0
nb stack references	4.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	11.63 cycles
front end	11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	8.08	8.13	3.75	3.75	1.50	8.17	8.13	1.50
cycles	8.08	8.13	3.75	3.75	1.50	8.17	8.13	1.50

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	11.63
Dispatch	8.17
Data deps.	0.00
Overall L1	11.63

Vectorization ratios

INT

all	10%
load	25%
store	33%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	10%
load	20%
store	33%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	12%
load	15%
store	16%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	12%
load	12%
store	16%
mul	10%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.63 cycles. At this rate:

3% of peak load performance is reached (4.81 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.93 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-gcc-skl256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.25 to 8.00 cycles (2.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 17.25 to 1.66 cycles (10.39x speedup).

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
18% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557
VPMULLQ: 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:408
VPTERNLOGQ: 2 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:406

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 120 bytes (30 single precision FP elements). The binary loop is storing 32 bytes (8 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	69
loop length	322
used x86 registers	4
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.25 cycles
front end	17.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	11.92	12.00	6.00	6.00	3.00	12.08	12.00	3.00
cycles	11.92	12.00	6.00	6.00	3.00	12.08	12.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	17.25
Dispatch	12.08
Data deps.	0.00
Overall L1	17.25

Vectorization ratios

INT

all	21%
load	50%
store	33%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	20%
load	40%
store	33%
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	14%
load	18%
store	16%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	13%
load	16%
store	16%
mul	15%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.25 cycles. At this rate:

5% of peak load performance is reached (6.96 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.86 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.25 to 12.08 cycles (1.43x speedup).

ASM code

In the binary file, the address of the loop is: 1e91

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
VMOVSS 0x21c6(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
SHR $0xb,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0x7,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x62d3a980,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0xf,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x103a0000,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
VCVTUSI2SS %EDX,%XMM2,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS 0x2181(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM0,%XMM1	1	1	0	0	0	0	0	0	0	3	1	scal (6.3%)
JA 1ffb <main+0xcbb>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP $0x26f,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JBE 1e30 <main+0xaf0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA -0x2750(%RBP),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV -0x2040(%RBP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x2038(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVDQA %XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPANDQ -0x2050(%RBP),%XMM9,%XMM1	1	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (25.0%)
AND $-0x80000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
AND $0x7fffffff,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
OR %RDX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VPTERNLOGQ $-0x14,-0x2048(%RBP),%XMM1,%XMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (25.0%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
VPSRLQ $0x1,%XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPANDQ %XMM8,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
AND $0x1,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
NEG %RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VPMULLQ -0x27d0(%RBP),%XMM0,%XMM0	4	1.50	1.50	0.50	0.50	0	0	0	0	15	1.50	vect (25.0%)
VPTERNLOGQ $-0x6a,-0x13e8(%RBP),%XMM0,%XMM1	2	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (25.0%)
XOR -0x13d8(%RBP),%RDX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVDQA %XMM1,-0x2050(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (25.0%)
XOR %RDX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
LEA -0x13d8(%RBP),%RDX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RAX,-0x2040(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA -0x2038(%RBP),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x2750(%RBP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV -0x13d8(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $-0x80000000,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND $0x7fffffff,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RDX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
AND $0x1,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
NEG %RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR -0x1af0(%RBP),%RDX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RDX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,-0x13d8(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0x1,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JMP 1e3b <main+0xafb>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-gcc-skl256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 2.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.45 cycles (13.24x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 16 bytes (4 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	24
loop length	105
used x86 registers	4
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.25	4.25	1.50	1.50	0.00	4.25	4.25	0.00
cycles	4.25	4.25	1.50	1.50	0.00	4.25	4.25	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.00
Dispatch	4.25
Data deps.	0.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	10%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

2% of peak load performance is reached (2.67 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 1e91

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
MOV -0x2750(%RBP,%RAX,8),%RSI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
INC %RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
VMOVSS 0x21c6(%RIP),%XMM1	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (6.3%)
SHR $0xb,%RDX	1	0.50	0	0	0	0	0.50	1	0.50	scal (12.5%)
MOV %EDX,%EDX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0x7,%RSI	1	0.50	0	0	0	0	0.50	1	0.50	scal (12.5%)
AND $-0x62d3a980,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0xf,%RSI	1	0.50	0	0	0	0	0.50	1	0.50	scal (12.5%)
AND $-0x103a0000,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RSI	1	0.50	0	0	0	0	0.50	1	0.50	scal (12.5%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
VCVTUSI2SS %EDX,%XMM2,%XMM0	2	0.50	0.50	0	0	1	0	6	1	scal (6.3%)
VMULSS 0x2181(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM0,%XMM1	1	1	0	0	0	0	0	3	1	scal (6.3%)
JA 1ffb <main+0xcbb>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
CMP $0x26f,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JBE 1e30 <main+0xaf0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code