OV - attention-gcc-skl256 - Loop 2 - attention-gcc-skl256

	Loop Id: 2	Module: attention-gcc-skl256	Source: random.tcc:458-3558 [...]	Coverage: 0.78%

0x1900 LEA	0x1(%RDX),%RAX

0x1904 MOV	-0x2750(%RBP,%RDX,8),%RDX    [2]

0x190c VMOVSS	0x26f8(%RIP),%XMM7    [3]

0x1914 MOV	%RAX,-0x13d0(%RBP)    [2]

0x191b MOV	%RDX,%RCX

0x191e SHR	$0xb,%RCX

0x1922 MOV	%ECX,%ECX

0x1924 XOR	%RCX,%RDX

0x1927 MOV	%RDX,%RCX

0x192a SAL	$0x7,%RCX

0x192e AND	$-0x62d3a980,%ECX

0x1934 XOR	%RCX,%RDX

0x1937 MOV	%RDX,%RCX

0x193a SAL	$0xf,%RCX

0x193e AND	$-0x103a0000,%ECX

0x1944 XOR	%RCX,%RDX

0x1947 MOV	%RDX,%RCX

0x194a SHR	$0x12,%RCX

0x194e XOR	%RCX,%RDX

0x1951 VCVTUSI2SS	%EDX,%XMM2,%XMM0

0x1957 VMULSS	0x26a9(%RIP),%XMM0,%XMM0    [3]

0x195f VCOMISS	%XMM0,%XMM7

0x1963 JA	1bd8

0x1969 MOV	%RAX,%RDX

0x196c CMP	$0x26f,%RAX

0x1972 JBE	1900

0x1974 LEA	-0x2750(%RBP),%RDI

0x197b MOV	%R8,-0x27a0(%RBP)    [2]

0x1982 MOV	%R9,-0x2798(%RBP)    [2]

0x1989 CALL	3380 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

0x198e MOV	-0x13d0(%RBP),%RDX    [2]

0x1995 MOV	-0x27a0(%RBP),%R8    [2]

0x199c VXORPS	%XMM2,%XMM2,%XMM2

0x19a0 MOV	-0x2798(%RBP),%R9    [2]

0x19a7 JMP	1900

0x1bd8 MOV	-0x27a8(%RBP),%RDI    [2]

0x1bdf VMOVSS	%XMM0,(%RDI)    [1]

0x1be3 ADD	$0x4,%RDI

0x1be7 MOV	%RDI,-0x27a8(%RBP)    [2]

0x1bee CMP	-0x27d0(%RBP),%RDI    [2]

0x1bf5 JNE	1969

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 163 - 163

--------------------------------------------------------------------------------

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

/usr/include/c++/16.1.1/bits/random.tcc: 458 - 3558

--------------------------------------------------------------------------------

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3557: 	  const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd);

3558: 	  if (__ret < _RealT(1.0))

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	main	new_allocator.h:183	attention-gcc-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.08
CQA speedup if FP arith vectorized	2.12
CQA speedup if fully vectorized	12.83
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.68
Bottlenecks
Function	main
Source	attention_v2.cpp:163-163,random.tcc:458-466,random.tcc:3557-3558
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	low
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	9.25
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	4.36
CQA cycles if fully vectorized	0.72
Front-end cycles	9.25
P0 cycles	5.38
P1 cycles	5.38
P2 cycles	3.75
P3 cycles	3.58
P4 cycles	4.50
P5 cycles	5.38
P6 cycles	5.38
P7 cycles	3.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.50
Nb uops	37.00
Nb loads	6.50
Nb stores	4.00
Nb stack references	4.50
FLOP/cycle	0.11
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.63
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	28.00
Stride 0	1.50
Stride 1	0.00
Stride n	0.00
Stride unknown	1.50
Stride indirect	0.00
Vectorization ratio all	2.08
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	3.33
Vector-efficiency ratio all	10.40
Vector-efficiency ratio load	7.81
Vector-efficiency ratio store	10.83
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.76

Metric	Value
CQA speedup if no scalar integer	3.23
CQA speedup if FP arith vectorized	2.07
CQA speedup if fully vectorized	12.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:163-163,random.tcc:458-466,random.tcc:3557-3558
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	low
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	10.50
CQA cycles if no scalar integer	3.25
CQA cycles if FP arith vectorized	5.06
CQA cycles if fully vectorized	0.83
Front-end cycles	10.50
P0 cycles	5.75
P1 cycles	5.75
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	6.00
P5 cycles	5.75
P6 cycles	5.75
P7 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	42.00
Nb loads	8.00
Nb stores	5.00
Nb stack references	6.00
FLOP/cycle	0.10
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.76
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	36.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	4.17
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	6.67
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	11.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.25

Metric	Value
CQA speedup if no scalar integer	2.91
CQA speedup if FP arith vectorized	2.18
CQA speedup if fully vectorized	13.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:163-163,random.tcc:458-466,random.tcc:3557-3558
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	low
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	8.00
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	3.66
CQA cycles if fully vectorized	0.61
Front-end cycles	8.00
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	2.83
P3 cycles	2.50
P4 cycles	3.00
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	5.00
Nb stores	3.00
Nb stack references	3.00
FLOP/cycle	0.13
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.50
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	20.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.87
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.27

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:458-3558
Module	attention-gcc-skl256

The loop is defined in:

/home/eoseret/Applications/llm-attention/attention_v2.cpp:163
/usr/include/c++/16.1.1/bits/random.tcc:458-466,3557-3558

It is peel/tail loop of related source loop which is unrolled by 3 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-generate, execute and recompile with -fprofile-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

std::mersenne_twister_engine::_M_gen_rand(): 0 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 44 bytes (11 single precision FP elements). The binary loop is storing 28 bytes (7 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	36.50
nb uops	37
loop length	179
used x86 registers	6
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	4.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	9.25 cycles
front end	9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.38	5.38	3.75	3.58	4.50	5.38	5.38	3.67
cycles	5.38	5.38	3.75	3.58	4.50	5.38	5.38	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.25
Dispatch	5.50
Data deps.	0.00
Overall L1	9.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	10%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	8%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

INT+FP

all	10%
load	7%
store	10%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

3% of peak load performance is reached (4.67 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.96 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	random.tcc:458-3558
Module	attention-gcc-skl256

The loop is defined in:

/home/eoseret/Applications/llm-attention/attention_v2.cpp:163
/usr/include/c++/16.1.1/bits/random.tcc:458-466,3557-3558

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.50 to 3.25 cycles (3.23x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-generate, execute and recompile with -fprofile-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

std::mersenne_twister_engine
::_M_gen_rand(): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 56 bytes (14 single precision FP elements). The binary loop is storing 36 bytes (9 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	41
nb uops	42
loop length	207
used x86 registers	7
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.75	5.75	4.67	4.67	6.00	5.75	5.75	4.67
cycles	5.75	5.75	4.67	4.67	6.00	5.75	5.75	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	10.50
Dispatch	6.00
Data deps.	0.00
Overall L1	10.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	10%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	10%
load	9%
store	11%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.50 cycles. At this rate:

4% of peak load performance is reached (5.33 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.43 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.50 to 6.00 cycles (1.75x speedup).

ASM code

In the binary file, the address of the loop is: 1969

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV -0x2750(%RBP,%RDX,8),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS 0x26f8(%RIP),%XMM7	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
MOV %RAX,-0x13d0(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0x7,%RCX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x62d3a980,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0xf,%RCX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x103a0000,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RCX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VCVTUSI2SS %EDX,%XMM2,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS 0x26a9(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM0,%XMM7	1	1	0	0	0	0	0	0	0	3	1	scal (6.3%)
JA 1bd8 <main+0x898>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x26f,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JBE 1900 <main+0x5c0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA -0x2750(%RBP),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %R8,-0x27a0(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %R9,-0x2798(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
CALL 3380 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV -0x13d0(%RBP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x27a0(%RBP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV -0x2798(%RBP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JMP 1900 <main+0x5c0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV -0x27a8(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RDI)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD $0x4,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDI,-0x27a8(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
CMP -0x27d0(%RBP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 1969 <main+0x629>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	random.tcc:458-3558
Module	attention-gcc-skl256

The loop is defined in:

/home/eoseret/Applications/llm-attention/attention_v2.cpp:163
/usr/include/c++/16.1.1/bits/random.tcc:458-466,3557-3558

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.00 to 2.75 cycles (2.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-generate, execute and recompile with -fprofile-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 32 bytes (8 single precision FP elements). The binary loop is storing 20 bytes (5 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	32
nb uops	32
loop length	151
used x86 registers	5
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.00	5.00	2.83	2.50	3.00	5.00	5.00	2.67
cycles	5.00	5.00	2.83	2.50	3.00	5.00	5.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.00
Dispatch	5.00
Data deps.	0.00
Overall L1	8.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	9%
load	6%
store	10%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

3% of peak load performance is reached (4.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.50 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 1969

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV -0x2750(%RBP,%RDX,8),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS 0x26f8(%RIP),%XMM7	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
MOV %RAX,-0x13d0(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0x7,%RCX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x62d3a980,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SAL $0xf,%RCX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x103a0000,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RCX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VCVTUSI2SS %EDX,%XMM2,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS 0x26a9(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VCOMISS %XMM0,%XMM7	1	1	0	0	0	0	0	0	0	3	1	scal (6.3%)
JA 1bd8 <main+0x898>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP $0x26f,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JBE 1900 <main+0x5c0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV -0x27a8(%RBP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RDI)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD $0x4,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDI,-0x27a8(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
CMP -0x27d0(%RBP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 1969 <main+0x629>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios