OV - attention-gcc-skl256 - Function softmax(float const*, float*, float*, int)

	Function: softmax(float const, float, float*, int)	Module: attention-gcc-skl256	Source: attention_v2.cpp:42-63	Coverage (incl. loops): 5.40% \| (excl. loops): 0.04%

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 42 - 63

--------------------------------------------------------------------------------

42: {

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

62:    }

63: }

0x2c70 TEST	%ECX,%ECX

0x2c72 JLE	2ed0

0x2c78 LEA	0x8(%RSP),%R10

0x2c7d AND	$-0x20,%RSP

0x2c81 PUSHQ	-0x8(%R10)

0x2c85 PUSH	%RBP

0x2c86 MOV	%RSP,%RBP

0x2c89 PUSH	%R15

0x2c8b PUSH	%R14

0x2c8d PUSH	%R13

0x2c8f MOV	$0x1,%R13D

0x2c95 PUSH	%R12

0x2c97 MOV	%RDI,%R12

0x2c9a PUSH	%R10

0x2c9c PUSH	%RBX

0x2c9d LEA	0x4(%RDI),%RBX

0x2ca1 SUB	$0x60,%RSP

0x2ca5 MOV	%RSI,-0x60(%RBP)

0x2ca9 MOV	%ECX,%ESI

0x2cab MOVL	$0,-0x3c(%RBP)

0x2cb2 LEA	0x4(,%RSI,4),%RAX

0x2cba VBROADCASTSS	0x1341(%RIP),%YMM0

0x2cc3 MOV	%RAX,-0x70(%RBP)

0x2cc7 LEA	0x4(%RDX),%RAX

0x2ccb MOV	%RAX,-0x50(%RBP)

0x2ccf LEA	(,%RSI,4),%RAX

0x2cd7 CMPL	$0x6,-0x3c(%RBP)

0x2cdb MOV	%ECX,-0x40(%RBP)

0x2cde MOV	%RAX,-0x68(%RBP)

0x2ce2 MOVQ	$0,-0x48(%RBP)

0x2cea MOV	%RSI,-0x78(%RBP)

0x2cee MOV	%RDI,-0x80(%RBP)

0x2cf2 MOV	%RDX,-0x58(%RBP)

0x2cf6 JLE	2e90

0x2cfc NOPL	(%RAX)

    (34) 0x2d00 MOV	%R13D,%ECX

    (34) 0x2d03 MOV	%R13D,%ESI

    (34) 0x2d06 MOV	%R12,%RAX

    (34) 0x2d09 SHR	$0x3,%ECX

    (34) 0x2d0c MOV	%ECX,%EDX

    (34) 0x2d0e SAL	$0x5,%RDX

    (34) 0x2d12 ADD	%R12,%RDX

    (34) 0x2d15 NOPL	(%RAX)

      (33) 0x2d18 VMAXPS	(%RAX),%YMM0,%YMM0

      (33) 0x2d1c ADD	$0x20,%RAX

      (33) 0x2d20 CMP	%RDX,%RAX

      (33) 0x2d23 JNE	2d18

    (34) 0x2d25 VEXTRACTF32X4	$0x1,%YMM0,%XMM3

    (34) 0x2d2c LEA	(,%RCX,8),%EAX

    (34) 0x2d33 VMAXPS	%XMM0,%XMM3,%XMM1

    (34) 0x2d37 VMOVHLPS	%XMM1,%XMM1,%XMM2

    (34) 0x2d3b VMAXPS	%XMM1,%XMM2,%XMM2

    (34) 0x2d3f VSHUFPS	$0x55,%XMM2,%XMM2,%XMM1

    (34) 0x2d44 VMAXPS	%XMM2,%XMM1,%XMM1

    (34) 0x2d48 CMP	%ESI,%EAX

    (34) 0x2d4a JE	2dad

  (35) 0x2d4c VMAXPS	%XMM3,%XMM0,%XMM0

  (35) 0x2d50 MOV	%EAX,%ECX

  (35) 0x2d52 MOV	-0x3c(%RBP),%EDX

  (35) 0x2d55 SUB	%EAX,%EDX

  (35) 0x2d57 CMP	$0x2,%EDX

  (35) 0x2d5a JBE	2d88

  (35) 0x2d5c MOV	-0x80(%RBP),%RDI

  (35) 0x2d60 ADD	-0x48(%RBP),%RAX

  (35) 0x2d64 INC	%EDX

  (35) 0x2d66 VMAXPS	(%RDI,%RAX,4),%XMM0,%XMM0

  (35) 0x2d6b MOV	%EDX,%EAX

  (35) 0x2d6d AND	$-0x4,%EAX

  (35) 0x2d70 AND	$0x3,%EDX

  (35) 0x2d73 VMOVHLPS	%XMM0,%XMM0,%XMM1

  (35) 0x2d77 VMAXPS	%XMM0,%XMM1,%XMM0

  (35) 0x2d7b VSHUFPS	$0x55,%XMM0,%XMM0,%XMM1

  (35) 0x2d80 VMAXPS	%XMM0,%XMM1,%XMM1

  (35) 0x2d84 JE	2dad

  (35) 0x2d86 ADD	%EAX,%ECX

  (35) 0x2d88 MOV	-0x3c(%RBP),%ESI

  (35) 0x2d8b MOVSXD	%ECX,%RAX

  (35) 0x2d8e VMAXSS	(%R12,%RAX,4),%XMM1,%XMM1

  (35) 0x2d94 CMP	%ECX,%ESI

  (35) 0x2d96 JLE	2dad

  (35) 0x2d98 ADD	$0x2,%ECX

  (35) 0x2d9b VMAXSS	0x4(%R12,%RAX,4),%XMM1,%XMM1

  (35) 0x2da2 CMP	%ECX,%ESI

  (35) 0x2da4 JL	2dad

  (35) 0x2da6 VMAXSS	0x8(%R12,%RAX,4),%XMM1,%XMM1

    (34) 0x2dad MOVL	$0,-0x34(%RBP)

    (34) 0x2db4 MOV	%R12,%R14

    (34) 0x2db7 VMOVSS	%XMM1,-0x38(%RBP)

    (34) 0x2dbc VZEROUPPER

    (34) 0x2dbf NOP

      (31) 0x2dc0 VMOVSS	(%R14),%XMM0

      (31) 0x2dc5 ADD	$0x4,%R14

      (31) 0x2dc9 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

      (31) 0x2dce CALL	1110 <expf@plt>

      (31) 0x2dd3 VADDSS	-0x34(%RBP),%XMM0,%XMM5

      (31) 0x2dd8 VMOVSS	%XMM5,-0x34(%RBP)

      (31) 0x2ddd CMP	%RBX,%R14

      (31) 0x2de0 JNE	2dc0

    (34) 0x2de2 MOV	-0x58(%RBP),%RAX

    (34) 0x2de6 MOV	-0x48(%RBP),%RDI

    (34) 0x2dea MOV	%R12,%R15

    (34) 0x2ded LEA	(%RAX,%RDI,4),%R14

    (34) 0x2df1 NOPL	(%RAX)

      (32) 0x2df8 VMOVSS	(%R15),%XMM0

      (32) 0x2dfd ADD	$0x4,%R15

      (32) 0x2e01 ADD	$0x4,%R14

      (32) 0x2e05 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

      (32) 0x2e0a CALL	1110 <expf@plt>

      (32) 0x2e0f VDIVSS	-0x34(%RBP),%XMM0,%XMM0

      (32) 0x2e14 VMOVSS	%XMM0,-0x4(%R14)

      (32) 0x2e1a CMP	%RBX,%R15

      (32) 0x2e1d JNE	2df8

    (34) 0x2e1f MOV	-0x3c(%RBP),%EAX

    (34) 0x2e22 MOV	-0x40(%RBP),%EDI

    (34) 0x2e25 LEA	0x1(%RAX),%ECX

    (34) 0x2e28 CMP	%ECX,%EDI

    (34) 0x2e2a JE	2ea8

    (34) 0x2e2c MOV	-0x78(%RBP),%RSI

    (34) 0x2e30 MOV	-0x50(%RBP),%R15

    (34) 0x2e34 INC	%R13

    (34) 0x2e37 MOV	%EDI,%EAX

    (34) 0x2e39 SUB	%R13D,%EAX

    (34) 0x2e3c MOV	-0x70(%RBP),%R14

    (34) 0x2e40 ADD	-0x68(%RBP),%R12

    (34) 0x2e44 MOV	%ECX,-0x38(%RBP)

    (34) 0x2e47 ADD	%RSI,-0x48(%RBP)

    (34) 0x2e4b MOV	%R15,%RDI

    (34) 0x2e4e LEA	0x4(,%RAX,4),%RDX

    (34) 0x2e56 XOR	%ESI,%ESI

    (34) 0x2e58 CALL	1050 <memset@plt>

    (34) 0x2e5d MOV	-0x38(%RBP),%ECX

    (34) 0x2e60 MOV	-0x60(%RBP),%RAX

    (34) 0x2e64 ADD	%R14,%R15

    (34) 0x2e67 VMOVSS	-0x34(%RBP),%XMM2

    (34) 0x2e6c ADD	%R14,%RBX

    (34) 0x2e6f VBROADCASTSS	0x118c(%RIP),%YMM0

    (34) 0x2e78 MOV	%R15,-0x50(%RBP)

    (34) 0x2e7c MOV	%ECX,-0x3c(%RBP)

    (34) 0x2e7f VMOVSS	%XMM2,-0x8(%RAX,%R13,4)

    (34) 0x2e86 CMPL	$0x6,-0x3c(%RBP)

    (34) 0x2e8a JG	2d00

(36) 0x2e90 VMOVSS	0x116c(%RIP),%XMM1

(36) 0x2e98 XOR	%EAX,%EAX

(36) 0x2e9a XOR	%ECX,%ECX

(36) 0x2e9c JMP	2d52

0x2ea1 NOPL	(%RAX)

0x2ea8 MOV	-0x3c(%RBP),%R14D

0x2eac MOV	-0x60(%RBP),%RAX

0x2eb0 VMOVSS	-0x34(%RBP),%XMM2

0x2eb5 VMOVSS	%XMM2,(%RAX,%R14,4)

0x2ebb ADD	$0x60,%RSP

0x2ebf POP	%RBX

0x2ec0 POP	%R10

0x2ec2 POP	%R12

0x2ec4 POP	%R13

0x2ec6 POP	%R14

0x2ec8 POP	%R15

0x2eca POP	%RBP

0x2ecb LEA	-0x8(%R10),%RSP

0x2ecf RET

0x2ed0 RET

0x2ed1 NOPL	(%RAX)

0x2ed5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	main	attention_v2.cpp:283	attention-gcc-skl256
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	main	new_allocator.h:183	attention-gcc-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-skl256

The function is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.00 to 2.25 cycles (8.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.00 to 13.50 cycles (1.41x speedup).

Workaround

Write less array elements

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	53
nb uops	54
loop length	207
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.00	4.00	11.50	11.17	19.00	4.00	4.00	11.33
cycles	4.00	4.50	11.50	11.17	19.00	4.00	4.00	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	19.00
Overall L1	19.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

1% of peak load performance is reached (1.68 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JLE 2ed0 <_Z7softmaxPKfPfS1_i+0x260>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x8(%RSP),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
PUSHQ -0x8(%R10)	2	0	0	0.83	0.83	1	0	0	0.33	3	1	N/A
PUSH %RBP	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSH %R15	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %R14	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %R13	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV $0x1,%R13D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
PUSH %R12	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
PUSH %R10	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %RBX	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
LEA 0x4(%RDI),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
SUB $0x60,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RSI,-0x60(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
LEA 0x4(,%RSI,4),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VBROADCASTSS 0x1341(%RIP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
MOV %RAX,-0x70(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (,%RSI,4),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMPL $0x6,-0x3c(%RBP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
MOV %ECX,-0x40(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV %RAX,-0x68(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
MOV %RSI,-0x78(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,-0x80(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
JLE 2e90 <_Z7softmaxPKfPfS1_i+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x3c(%RBP),%R14D	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM2,(%RAX,%R14,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD $0x60,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
POP %RBX	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R10	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R12	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R13	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R14	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R15	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %RBP	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
LEA -0x8(%R10),%RSP	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-skl256

The function is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.00 to 2.25 cycles (8.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Write less array elements

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	53
nb uops	54
loop length	207
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.00	4.00	11.50	11.17	19.00	4.00	4.00	11.33
cycles	4.00	4.50	11.50	11.17	19.00	4.00	4.00	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	19.00
Overall L1	19.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

1% of peak load performance is reached (1.68 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JLE 2ed0 <_Z7softmaxPKfPfS1_i+0x260>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x8(%RSP),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
PUSHQ -0x8(%R10)	2	0	0	0.83	0.83	1	0	0	0.33	3	1	N/A
PUSH %RBP	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSH %R15	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %R14	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %R13	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV $0x1,%R13D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
PUSH %R12	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
PUSH %R10	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
PUSH %RBX	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
LEA 0x4(%RDI),%RBX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
SUB $0x60,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RSI,-0x60(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
LEA 0x4(,%RSI,4),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VBROADCASTSS 0x1341(%RIP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (6.3%)
MOV %RAX,-0x70(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (,%RSI,4),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMPL $0x6,-0x3c(%RBP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
MOV %ECX,-0x40(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV %RAX,-0x68(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	2	1	scal (6.3%)
MOV %RSI,-0x78(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDI,-0x80(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
JLE 2e90 <_Z7softmaxPKfPfS1_i+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x3c(%RBP),%R14D	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM2,(%RAX,%R14,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD $0x60,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
POP %RBX	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R10	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R12	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R13	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R14	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %R15	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %RBP	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
LEA -0x8(%R10),%RSP	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A

Name	Coverage (%)	Time (s)
▼softmax(float const, float, float*, int)–	5.40	1.48
▼Loop 36 - attention_v2.cpp:43-61 - attention-gcc-skl256–	0.00	0.00
▼Loop 35 - attention_v2.cpp:43-61 - attention-gcc-skl256–	0.04	0.01
▼Loop 34 - attention_v2.cpp:43-61 - attention-gcc-skl256–	0.18	0.05
○Loop 32 - attention_v2.cpp:55-56 - attention-gcc-skl256	4.58	1.26
○Loop 31 - attention_v2.cpp:52-53 - attention-gcc-skl256	0.53	0.15
○Loop 33 - attention_v2.cpp:47-48 - attention-gcc-skl256	0.04	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code