OV - attention-avx512 - Loop 69

	Loop Id: 69	Module: attention-avx512	Source: attention.cpp:27-33	Coverage: 0.98%

0x405580 VMOVDQU64	0x180(%RSP),%ZMM22

0x405588 VCVTSD2SS	%XMM21,%XMM21,%XMM0

0x40558e LEA	(%RCX,%RDI,1),%ESI

0x405591 VMOVSS	%XMM0,(%R14,%RSI,4)

0x405597 VCVTSD2SS	%XMM20,%XMM20,%XMM0

0x40559d LEA	0x1(%RCX,%RDI,1),%ESI

0x4055a1 VMOVSS	%XMM0,(%R14,%RSI,4)

0x4055a7 VCVTSD2SS	%XMM19,%XMM19,%XMM0

0x4055ad LEA	0x2(%RCX,%RDI,1),%ESI

0x4055b1 VMOVSS	%XMM0,(%R14,%RSI,4)

0x4055b7 VCVTSD2SS	%XMM18,%XMM18,%XMM0

0x4055bd LEA	0x3(%RCX,%RDI,1),%ESI

0x4055c1 VMOVSS	%XMM0,(%R14,%RSI,4)

0x4055c7 VCVTSD2SS	%XMM17,%XMM17,%XMM0

0x4055cd LEA	0x4(%RCX,%RDI,1),%ESI

0x4055d1 VMOVSS	%XMM0,(%R14,%RSI,4)

0x4055d7 VCVTSD2SS	%XMM16,%XMM16,%XMM0

0x4055dd LEA	0x5(%RCX,%RDI,1),%ESI

0x4055e1 VMOVSS	%XMM0,(%R14,%RSI,4)

0x4055e7 VCVTSD2SS	%XMM15,%XMM15,%XMM0

0x4055ec LEA	0x6(%RCX,%RDI,1),%ESI

0x4055f0 VMOVSS	%XMM0,(%R14,%RSI,4)

0x4055f6 VCVTSD2SS	%XMM14,%XMM14,%XMM0

0x4055fb LEA	0x7(%RCX,%RDI,1),%ESI

0x4055ff VMOVSS	%XMM0,(%R14,%RSI,4)

0x405605 ADD	$0x8,%EDX

0x405608 CMP	0x1c0(%RSP),%RAX

0x405610 LEA	0x1(%RAX),%RAX

0x405614 JE	405372

0x40561a LEA	(,%RAX,8),%EDI

0x405621 TEST	%R8,%R8

0x405624 JE	405980

0x40562a VPBROADCASTD	%EDI,%YMM22

0x405630 VXORPD	%XMM21,%XMM21,%XMM21

0x405636 XOR	%ESI,%ESI

0x405638 VXORPD	%XMM20,%XMM20,%XMM20

0x40563e VXORPD	%XMM19,%XMM19,%XMM19

0x405644 VXORPD	%XMM18,%XMM18,%XMM18

0x40564a VXORPD	%XMM17,%XMM17,%XMM17

0x405650 VXORPD	%XMM16,%XMM16,%XMM16

0x405656 VXORPD	%XMM15,%XMM15,%XMM15

0x40565b VXORPD	%XMM14,%XMM14,%XMM14

  (70) 0x405660 LEA	(%R11,%RSI,1),%EBX

  (70) 0x405664 VPBROADCASTD	%EBX,%YMM23

  (70) 0x40566a VPADDD	%YMM3,%YMM23,%YMM23

  (70) 0x405670 KXNORW	%K0,%K0,%K1

  (70) 0x405674 VXORPS	%XMM24,%XMM24,%XMM24

  (70) 0x40567a VGATHERDPS	(%R9,%YMM23,4),%YMM24{%K1}

  (70) 0x405681 VPBROADCASTD	%ESI,%YMM23

  (70) 0x405687 VPADDD	%YMM1,%YMM23,%YMM23

  (70) 0x40568d VPMULLD	%YMM23,%YMM26,%YMM23

  (70) 0x405693 VPADDD	%YMM22,%YMM23,%YMM23

  (70) 0x405699 VPSUBD	%YMM2,%YMM23,%YMM25

  (70) 0x40569f KXNORW	%K0,%K0,%K1

  (70) 0x4056a3 VPXORD	%XMM26,%XMM26,%XMM26

  (70) 0x4056a9 VGATHERDPS	(%R10,%YMM25,4),%YMM26{%K1}

  (70) 0x4056b0 VPADDD	%YMM7,%YMM23,%YMM25

  (70) 0x4056b6 KXNORW	%K0,%K0,%K1

  (70) 0x4056ba VXORPS	%XMM27,%XMM27,%XMM27

  (70) 0x4056c0 VGATHERDPS	(%R10,%YMM25,4),%YMM27{%K1}

  (70) 0x4056c7 VPADDD	%YMM8,%YMM23,%YMM25

  (70) 0x4056cd KXNORW	%K0,%K0,%K1

  (70) 0x4056d1 VXORPS	%XMM28,%XMM28,%XMM28

  (70) 0x4056d7 VGATHERDPS	(%R10,%YMM25,4),%YMM28{%K1}

  (70) 0x4056de VPADDD	%YMM9,%YMM23,%YMM25

  (70) 0x4056e4 KXNORW	%K0,%K0,%K1

  (70) 0x4056e8 VXORPS	%XMM29,%XMM29,%XMM29

  (70) 0x4056ee VGATHERDPS	(%R10,%YMM25,4),%YMM29{%K1}

  (70) 0x4056f5 VPADDD	%YMM10,%YMM23,%YMM25

  (70) 0x4056fb KXNORW	%K0,%K0,%K1

  (70) 0x4056ff VXORPS	%XMM30,%XMM30,%XMM30

  (70) 0x405705 VGATHERDPS	(%R10,%YMM25,4),%YMM30{%K1}

  (70) 0x40570c VPADDD	%YMM11,%YMM23,%YMM25

  (70) 0x405712 KXNORW	%K0,%K0,%K1

  (70) 0x405716 VXORPS	%XMM31,%XMM31,%XMM31

  (70) 0x40571c VGATHERDPS	(%R10,%YMM25,4),%YMM31{%K1}

  (70) 0x405723 VPADDD	%YMM12,%YMM23,%YMM25

  (70) 0x405729 KXNORW	%K0,%K0,%K1

  (70) 0x40572d VXORPS	%XMM0,%XMM0,%XMM0

  (70) 0x405731 VGATHERDPS	(%R10,%YMM25,4),%YMM0{%K1}

  (70) 0x405738 VCVTPS2PD	%YMM24,%ZMM24

  (70) 0x40573e VCVTPS2PD	%YMM26,%ZMM25

  (70) 0x405744 VCVTPS2PD	%YMM27,%ZMM26

  (70) 0x40574a VFMADD231PD	%ZMM25,%ZMM24,%ZMM21

  (70) 0x405750 VFMADD231PD	%ZMM26,%ZMM24,%ZMM20

  (70) 0x405756 VCVTPS2PD	%YMM28,%ZMM25

  (70) 0x40575c VCVTPS2PD	%YMM29,%ZMM26

  (70) 0x405762 VFMADD231PD	%ZMM25,%ZMM24,%ZMM19

  (70) 0x405768 VFMADD231PD	%ZMM26,%ZMM24,%ZMM18

  (70) 0x40576e VCVTPS2PD	%YMM30,%ZMM25

  (70) 0x405774 VCVTPS2PD	%YMM31,%ZMM26

  (70) 0x40577a VFMADD231PD	%ZMM25,%ZMM24,%ZMM17

  (70) 0x405780 VFMADD231PD	%ZMM26,%ZMM24,%ZMM16

  (70) 0x405786 VMOVDQU64	0x120(%RSP),%YMM26

  (70) 0x40578e VCVTPS2PD	%YMM0,%ZMM0

  (70) 0x405794 VPADDD	%YMM13,%YMM23,%YMM23

  (70) 0x40579a KXNORW	%K0,%K0,%K1

  (70) 0x40579e VXORPD	%XMM25,%XMM25,%XMM25

  (70) 0x4057a4 VGATHERDPS	(%R10,%YMM23,4),%YMM25{%K1}

  (70) 0x4057ab VFMADD231PD	%ZMM0,%ZMM24,%ZMM15

  (70) 0x4057b1 VCVTPS2PD	%YMM25,%ZMM0

  (70) 0x4057b7 VFMADD231PD	%ZMM0,%ZMM24,%ZMM14

  (70) 0x4057bd ADD	$0x8,%RSI

  (70) 0x4057c1 CMP	%R8,%RSI

  (70) 0x4057c4 JB	405660

0x4057ca VEXTRACTF64X4	$0x1,%ZMM21,%YMM0

0x4057d1 VADDPD	%ZMM0,%ZMM21,%ZMM0

0x4057d7 VMOVAPD	%XMM0,%XMM21

0x4057dd VEXTRACTF128	$0x1,%YMM0,%XMM0

0x4057e3 VADDPD	%XMM0,%XMM21,%XMM0

0x4057e9 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM21

0x4057f0 VADDSD	%XMM21,%XMM0,%XMM21

0x4057f6 VEXTRACTF64X4	$0x1,%ZMM20,%YMM0

0x4057fd VADDPD	%ZMM0,%ZMM20,%ZMM0

0x405803 VMOVAPD	%XMM0,%XMM20

0x405809 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x40580f VADDPD	%XMM0,%XMM20,%XMM0

0x405815 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM20

0x40581c VADDSD	%XMM20,%XMM0,%XMM20

0x405822 VEXTRACTF64X4	$0x1,%ZMM19,%YMM0

0x405829 VADDPD	%ZMM0,%ZMM19,%ZMM0

0x40582f VMOVAPD	%XMM0,%XMM19

0x405835 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x40583b VADDPD	%XMM0,%XMM19,%XMM0

0x405841 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM19

0x405848 VADDSD	%XMM19,%XMM0,%XMM19

0x40584e VEXTRACTF64X4	$0x1,%ZMM18,%YMM0

0x405855 VADDPD	%ZMM0,%ZMM18,%ZMM0

0x40585b VMOVAPD	%XMM0,%XMM18

0x405861 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x405867 VADDPD	%XMM0,%XMM18,%XMM0

0x40586d VSHUFPD	$0x1,%XMM0,%XMM0,%XMM18

0x405874 VADDSD	%XMM18,%XMM0,%XMM18

0x40587a VEXTRACTF64X4	$0x1,%ZMM17,%YMM0

0x405881 VADDPD	%ZMM0,%ZMM17,%ZMM0

0x405887 VMOVAPD	%XMM0,%XMM17

0x40588d VEXTRACTF128	$0x1,%YMM0,%XMM0

0x405893 VADDPD	%XMM0,%XMM17,%XMM0

0x405899 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM17

0x4058a0 VADDSD	%XMM17,%XMM0,%XMM17

0x4058a6 VEXTRACTF64X4	$0x1,%ZMM16,%YMM0

0x4058ad VADDPD	%ZMM0,%ZMM16,%ZMM0

0x4058b3 VMOVAPD	%XMM0,%XMM16

0x4058b9 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x4058bf VADDPD	%XMM0,%XMM16,%XMM0

0x4058c5 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM16

0x4058cc VADDSD	%XMM16,%XMM0,%XMM16

0x4058d2 VEXTRACTF64X4	$0x1,%ZMM15,%YMM0

0x4058d9 VADDPD	%ZMM0,%ZMM15,%ZMM0

0x4058df VMOVAPD	%XMM0,%XMM15

0x4058e3 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x4058e9 VADDPD	%XMM0,%XMM15,%XMM0

0x4058ed VSHUFPD	$0x1,%XMM0,%XMM0,%XMM15

0x4058f2 VADDSD	%XMM0,%XMM15,%XMM15

0x4058f6 VEXTRACTF64X4	$0x1,%ZMM14,%YMM0

0x4058fd VADDPD	%ZMM0,%ZMM14,%ZMM0

0x405903 VMOVAPD	%XMM0,%XMM14

0x405907 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x40590d VADDPD	%XMM0,%XMM14,%XMM0

0x405911 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM14

0x405916 VADDSD	%XMM0,%XMM14,%XMM14

0x40591a CMP	%R8D,%R15D

0x40591d JE	405580

0x405923 VPUNPCKLQDQ	%XMM21,%XMM20,%XMM0

0x405929 VPUNPCKLQDQ	%XMM19,%XMM18,%XMM18

0x40592f VINSERTF32X4	$0x1,%XMM0,%YMM18,%YMM0

0x405936 VPUNPCKLQDQ	%XMM17,%XMM16,%XMM16

0x40593c VPUNPCKLQDQ	%XMM15,%XMM14,%XMM14

0x405941 VINSERTF32X4	$0x1,%XMM16,%YMM14,%YMM14

0x405948 VINSERTF64X4	$0x1,%YMM0,%ZMM14,%ZMM14

0x40594f MOV	%R8,%RSI

0x405952 VMOVDQU64	0x180(%RSP),%ZMM22

0x40595a JMP	405987

0x405980 VXORPD	%XMM14,%XMM14,%XMM14

0x405985 XOR	%ESI,%ESI

0x405987 MOV	0x40(%RSP),%R15

0x40598c MOV	%R15D,%EBX

0x40598f IMUL	%ESI,%EBX

0x405992 MOV	%RDX,0x30(%RSP)

0x405997 ADD	%EDX,%EBX

0x405999 MOV	0x88(%RSP),%RDX

0x4059a1 NOPW	%CS:(%RAX,%RAX,1)

  (64) 0x4059b0 LEA	(%R11,%RSI,1),%R14D

  (64) 0x4059b4 VMOVSS	(%R12,%R14,4),%XMM0

  (64) 0x4059ba VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (64) 0x4059be LEA	0x3(%RBX),%R14D

  (64) 0x4059c2 VPBROADCASTD	%EBX,%YMM15

  (64) 0x4059c8 VPADDD	%YMM4,%YMM15,%YMM7

  (64) 0x4059cc VPBROADCASTD	%R14D,%YMM8

  (64) 0x4059d2 VPBLENDD	$0x10,%YMM8,%YMM7,%YMM7

  (64) 0x4059d8 VPADDD	%YMM5,%YMM15,%YMM8

  (64) 0x4059dc VPERMT2D	%YMM8,%YMM6,%YMM7

  (64) 0x4059e2 VPBLENDD	$-0x80,%YMM15,%YMM7,%YMM7

  (64) 0x4059e8 VPSUBD	%YMM2,%YMM7,%YMM7

  (64) 0x4059ec KXNORW	%K0,%K0,%K1

  (64) 0x4059f0 VPXOR	%XMM8,%XMM8,%XMM8

  (64) 0x4059f5 VGATHERDPS	(%R10,%YMM7,4),%YMM8{%K1}

  (64) 0x4059fc VCVTPS2PD	%YMM8,%ZMM7

  (64) 0x405a02 VBROADCASTSD	%XMM0,%ZMM0

  (64) 0x405a08 VFMADD231PD	%ZMM0,%ZMM7,%ZMM14

  (64) 0x405a0e INC	%RSI

  (64) 0x405a11 ADD	%R15D,%EBX

  (64) 0x405a14 CMP	%RSI,%RDX

  (64) 0x405a17 JNE	4059b0

0x405a19 VEXTRACTF32X4	$0x3,%ZMM14,%XMM20

0x405a20 VSHUFPD	$0x1,%XMM20,%XMM20,%XMM21

0x405a27 VEXTRACTF32X4	$0x2,%ZMM14,%XMM18

0x405a2e VSHUFPD	$0x1,%XMM18,%XMM18,%XMM19

0x405a35 VMOVAPD	%YMM14,%YMM0

0x405a39 VEXTRACTF32X4	$0x1,%YMM14,%XMM16

0x405a40 VSHUFPD	$0x1,%XMM16,%XMM16,%XMM17

0x405a47 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM15

0x405a4c MOV	0xc0(%RSP),%R14

0x405a54 MOV	%RDX,%R15

0x405a57 VPBROADCASTD	0xa984(%RIP),%YMM7

0x405a60 VPBROADCASTD	0xa97f(%RIP),%YMM8

0x405a69 MOV	0x30(%RSP),%RDX

0x405a6e JMP	405588

/home/eoseret/llm-attention/attention.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.12
CQA speedup if fully vectorized	3.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.17
CQA cycles if no scalar integer	23.83
CQA cycles if FP arith vectorized	22.50
CQA cycles if fully vectorized	7.81
Front-end cycles	17.06
P0 cycles	13.17
P1 cycles	25.17
P2 cycles	1.89
P3 cycles	1.89
P4 cycles	4.33
P5 cycles	25.00
P6 cycles	4.33
P7 cycles	4.33
P8 cycles	4.33
P9 cycles	4.33
P10 cycles	4.33
P11 cycles	1.89
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.67
Nb uops	102.33
Nb loads	5.67
Nb stores	8.67
Nb stack references	4.33
FLOP/cycle	2.33
Nb FLOP add-sub	58.67
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.19
Bytes prefetched	0.00
Bytes loaded	77.33
Bytes stored	37.33
Stride 0	0.67
Stride 1	0.00
Stride n	0.00
Stride unknown	0.67
Stride indirect	2.00
Vectorization ratio all	53.32
Vectorization ratio load	23.33
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	65.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	64.07
Vector-efficiency ratio all	24.66
Vector-efficiency ratio load	31.04
Vector-efficiency ratio store	6.71
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	45.04
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.04

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P1, P5,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	1.75
Front-end cycles	10.33
P0 cycles	8.00
P1 cycles	11.50
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	4.50
P5 cycles	11.50
P6 cycles	4.00
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	4.00
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.00
Nb uops	62.00
Nb loads	7.00
Nb stores	9.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.65
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	40.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	28.13
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.91
Vector-efficiency ratio all	14.84
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	6.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.18

Metric	Value
CQA speedup if no scalar integer	1.04
CQA speedup if FP arith vectorized	1.15
CQA speedup if fully vectorized	2.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P1, P5,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	35.50
CQA cycles if no scalar integer	34.00
CQA cycles if FP arith vectorized	31.00
CQA cycles if fully vectorized	12.12
Front-end cycles	23.00
P0 cycles	16.00
P1 cycles	35.50
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	4.50
P5 cycles	35.50
P6 cycles	5.00
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	5.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	130.00
Nb uops	138.00
Nb loads	8.00
Nb stores	9.00
Nb stack references	6.00
FLOP/cycle	2.48
Nb FLOP add-sub	88.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.28
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	40.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	3.00
Vectorization ratio all	64.76
Vectorization ratio load	20.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	72.86
Vector-efficiency ratio all	28.69
Vector-efficiency ratio load	27.50
Vector-efficiency ratio store	6.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	24.82

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	1.14
CQA speedup if fully vectorized	2.98
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P1,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.50
CQA cycles if no scalar integer	26.50
CQA cycles if FP arith vectorized	25.00
CQA cycles if fully vectorized	9.56
Front-end cycles	17.83
P0 cycles	15.50
P1 cycles	28.50
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	4.00
P5 cycles	28.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	107.00
Nb loads	2.00
Nb stores	8.00
Nb stack references	2.00
FLOP/cycle	3.09
Nb FLOP add-sub	88.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.65
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	67.06
Vectorization ratio load	50.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	64.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	78.43
Vector-efficiency ratio all	30.44
Vector-efficiency ratio load	56.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	44.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	26.10

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:27,30-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 25.17 to 7.81 cycles (3.22x speedup).

Details

53% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

23% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
65% of SSE/AVX addition or subtraction instructions are used in vector version.
64% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 0 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 5 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58.666666666667 FP arithmetical operations:

58.67: addition or subtraction

The binary loop is loading 77 bytes (9 double precision FP elements). The binary loop is storing 37 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.51 FP operations per loaded or stored byte.

General properties

nb instructions	94.67
nb uops	102.33
loop length	539.33
used x86 registers	9.67
used mmx registers	0
used xmm registers	9
used ymm registers	4
used zmm registers	7
nb stack references	4.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	17.06 cycles
front end	17.06 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.17	25.17	1.89	1.89	4.33	25.00	4.33	4.33	4.33	4.33	4.33	1.89
cycles	13.17	25.17	1.89	1.89	4.33	25.00	4.33	4.33	4.33	4.33	4.33	1.89

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	17.06
Dispatch	25.17
Data deps.	0.00
Overall L1	25.17

Vectorization ratios

INT

all	9%
load	23%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	59%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	74%

INT+FP

all	53%
load	23%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	64%

Vector efficiency ratios

INT

all	18%
load	31%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	24%
load	31%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.17 cycles. At this rate:

1% of peak load performance is reached (3.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.50 to 1.75 cycles (6.57x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 48 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	54
nb uops	62
loop length	300
used x86 registers	10
used mmx registers	0
used xmm registers	9
used ymm registers	4
used zmm registers	1
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.33 cycles
front end	10.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	11.50	2.33	2.33	4.50	11.50	4.00	4.50	4.50	4.50	4.00	2.33
cycles	8.00	11.50	2.33	2.33	4.50	11.50	4.00	4.50	4.50	4.50	4.00	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	10.33
Dispatch	11.50
Data deps.	0.00
Overall L1	11.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	36%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	52%

INT+FP

all	28%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	10%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	14%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

2% of peak load performance is reached (4.17 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40561a

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM21,%XMM21,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RCX,%RDI,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM20,%XMM20,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x1(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM19,%XMM19,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x2(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM18,%XMM18,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x3(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM17,%XMM17,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x4(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM16,%XMM16,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x5(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM15,%XMM15,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x6(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM14,%XMM14,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x7(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP 0x1c0(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RAX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 405372 <main+0x9f2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RAX,8),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 405980 <main+0x1000>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R15D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x88(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF32X4 $0x3,%ZMM14,%XMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM20,%XMM20,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VEXTRACTF32X4 $0x2,%ZMM14,%XMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM18,%XMM18,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM14,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM14,%XMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM16,%XMM16,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV 0xc0(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VPBROADCASTD 0xa984(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VPBROADCASTD 0xa97f(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 405588 <main+0xc08>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 28% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 35.50 to 12.12 cycles (2.93x speedup).

Details

64% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
72% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 35.50 to 23.00 cycles (1.54x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 88 FP arithmetical operations:

88: addition or subtraction

The binary loop is loading 112 bytes (14 double precision FP elements). The binary loop is storing 40 bytes (5 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.58 FP operations per loaded or stored byte.

General properties

nb instructions	130
nb uops	138
loop length	749
used x86 registers	10
used mmx registers	0
used xmm registers	9
used ymm registers	6
used zmm registers	10
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.00 cycles
front end	23.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.00	35.50	2.67	2.67	4.50	35.50	5.00	4.50	4.50	4.50	5.00	2.67
cycles	16.00	35.50	2.67	2.67	4.50	35.50	5.00	4.50	4.50	4.50	5.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	23.00
Dispatch	35.50
Data deps.	0.00
Overall L1	35.50

Vectorization ratios

INT

all	7%
load	20%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	73%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	86%

INT+FP

all	64%
load	20%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	72%

Vector efficiency ratios

INT

all	16%
load	27%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	30%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	28%
load	27%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 35.50 cycles. At this rate:

1% of peak load performance is reached (3.15 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40561a

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM21,%XMM21,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RCX,%RDI,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM20,%XMM20,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x1(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM19,%XMM19,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x2(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM18,%XMM18,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x3(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM17,%XMM17,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x4(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM16,%XMM16,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x5(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM15,%XMM15,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x6(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM14,%XMM14,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x7(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP 0x1c0(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RAX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 405372 <main+0x9f2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RAX,8),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 405980 <main+0x1000>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %EDI,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VEXTRACTF64X4 $0x1,%ZMM21,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM21,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM21,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM21,%XMM0,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM20,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM20,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM20,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM20,%XMM0,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM19,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM19,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM19,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM18,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM18,%XMM0,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM17,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM17,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM17,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM17,%XMM0,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM16,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM16,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM16,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM16,%XMM0,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM15,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM15,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM15,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM0,%XMM15,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM14,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM14,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM14,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM0,%XMM14,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %R8D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 405580 <main+0xc00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPUNPCKLQDQ %XMM21,%XMM20,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM19,%XMM18,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM0,%YMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKLQDQ %XMM17,%XMM16,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM15,%XMM14,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM16,%YMM14,%YMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VINSERTF64X4 $0x1,%YMM0,%ZMM14,%ZMM14	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU64 0x180(%RSP),%ZMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
JMP 405987 <main+0x1007>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x40(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R15D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %EDX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x88(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF32X4 $0x3,%ZMM14,%XMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM20,%XMM20,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VEXTRACTF32X4 $0x2,%ZMM14,%XMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM18,%XMM18,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM14,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM14,%XMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM16,%XMM16,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV 0xc0(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VPBROADCASTD 0xa984(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VPBROADCASTD 0xa97f(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 405588 <main+0xc08>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.50 to 26.50 cycles (1.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 28.50 to 9.56 cycles (2.98x speedup).

Details

67% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
64% of SSE/AVX addition or subtraction instructions are used in vector version.
78% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 88 FP arithmetical operations:

88: addition or subtraction

The binary loop is loading 72 bytes (9 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.85 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	107
loop length	569
used x86 registers	9
used mmx registers	0
used xmm registers	9
used ymm registers	2
used zmm registers	10
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	17.83 cycles
front end	17.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.50	28.50	0.67	0.67	4.00	28.00	4.00	4.00	4.00	4.00	4.00	0.67
cycles	15.50	28.50	0.67	0.67	4.00	28.00	4.00	4.00	4.00	4.00	4.00	0.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	17.83
Dispatch	28.50
Data deps.	0.00
Overall L1	28.50

Vectorization ratios

INT

all	20%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	70%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	83%

INT+FP

all	67%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	64%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	78%

Vector efficiency ratios

INT

all	27%
load	56%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	30%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	30%
load	56%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

1% of peak load performance is reached (2.53 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40561a

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVDQU64 0x180(%RSP),%ZMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCVTSD2SS %XMM21,%XMM21,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RCX,%RDI,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM20,%XMM20,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x1(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM19,%XMM19,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x2(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM18,%XMM18,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x3(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM17,%XMM17,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x4(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM16,%XMM16,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x5(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM15,%XMM15,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x6(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM14,%XMM14,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x7(%RCX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM0,(%R14,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP 0x1c0(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RAX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 405372 <main+0x9f2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RAX,8),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 405980 <main+0x1000>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %EDI,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VEXTRACTF64X4 $0x1,%ZMM21,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM21,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM21,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM21,%XMM0,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM20,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM20,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM20,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM20,%XMM0,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM19,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM19,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM19,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM18,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM18,%XMM0,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM17,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM17,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM17,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM17,%XMM0,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM16,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM16,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM16,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM16,%XMM0,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM15,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM15,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM15,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM0,%XMM15,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM14,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM0,%ZMM14,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM0,%XMM14,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM0,%XMM14,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %R8D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JE 405580 <main+0xc00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

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Vectorization

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Complex instructions

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Slow data structures access

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Conversion instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

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Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

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Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround