OV - attention-avx512 - Loop 63

	Loop Id: 63	Module: attention-avx512	Source: attention.cpp:30-31	Coverage: 8.79%

0x405f70 LEA	(%R11,%RSI,1),%EBX

0x405f74 VPBROADCASTD	%EBX,%YMM23

0x405f7a VPADDD	%YMM3,%YMM23,%YMM23

0x405f80 VXORPD	%XMM24,%XMM24,%XMM24

0x405f86 KXNORW	%K0,%K0,%K1

0x405f8a VGATHERDPS	(%R9,%YMM23,4),%YMM24{%K1}    [1]

0x405f91 VPBROADCASTD	%ESI,%YMM23

0x405f97 VPADDD	%YMM1,%YMM23,%YMM23

0x405f9d VPMULLD	%YMM23,%YMM26,%YMM23

0x405fa3 VPADDD	%YMM22,%YMM23,%YMM23

0x405fa9 VPSUBD	%YMM2,%YMM23,%YMM25

0x405faf VPXORD	%XMM26,%XMM26,%XMM26

0x405fb5 KXNORW	%K0,%K0,%K1

0x405fb9 VGATHERDPS	(%R10,%YMM25,4),%YMM26{%K1}    [2]

0x405fc0 VPADDD	%YMM7,%YMM23,%YMM25

0x405fc6 VXORPS	%XMM27,%XMM27,%XMM27

0x405fcc KXNORW	%K0,%K0,%K1

0x405fd0 VGATHERDPS	(%R10,%YMM25,4),%YMM27{%K1}    [2]

0x405fd7 VPADDD	%YMM8,%YMM23,%YMM25

0x405fdd VXORPS	%XMM28,%XMM28,%XMM28

0x405fe3 KXNORW	%K0,%K0,%K1

0x405fe7 VGATHERDPS	(%R10,%YMM25,4),%YMM28{%K1}    [2]

0x405fee VPADDD	%YMM9,%YMM23,%YMM25

0x405ff4 VXORPS	%XMM29,%XMM29,%XMM29

0x405ffa KXNORW	%K0,%K0,%K1

0x405ffe VGATHERDPS	(%R10,%YMM25,4),%YMM29{%K1}    [2]

0x406005 VPADDD	%YMM10,%YMM23,%YMM25

0x40600b VXORPS	%XMM30,%XMM30,%XMM30

0x406011 KXNORW	%K0,%K0,%K1

0x406015 VGATHERDPS	(%R10,%YMM25,4),%YMM30{%K1}    [2]

0x40601c VPADDD	%YMM11,%YMM23,%YMM25

0x406022 VXORPS	%XMM31,%XMM31,%XMM31

0x406028 KXNORW	%K0,%K0,%K1

0x40602c VGATHERDPS	(%R10,%YMM25,4),%YMM31{%K1}    [2]

0x406033 VPADDD	%YMM12,%YMM23,%YMM25

0x406039 VXORPS	%XMM0,%XMM0,%XMM0

0x40603d KXNORW	%K0,%K0,%K1

0x406041 VGATHERDPS	(%R10,%YMM25,4),%YMM0{%K1}    [2]

0x406048 VCVTPS2PD	%YMM24,%ZMM24

0x40604e VCVTPS2PD	%YMM26,%ZMM25

0x406054 VCVTPS2PD	%YMM27,%ZMM26

0x40605a VFMADD231PD	%ZMM25,%ZMM24,%ZMM21

0x406060 VFMADD231PD	%ZMM26,%ZMM24,%ZMM20

0x406066 VCVTPS2PD	%YMM28,%ZMM25

0x40606c VCVTPS2PD	%YMM29,%ZMM26

0x406072 VFMADD231PD	%ZMM25,%ZMM24,%ZMM19

0x406078 VFMADD231PD	%ZMM26,%ZMM24,%ZMM18

0x40607e VCVTPS2PD	%YMM30,%ZMM25

0x406084 VCVTPS2PD	%YMM31,%ZMM26

0x40608a VFMADD231PD	%ZMM25,%ZMM24,%ZMM17

0x406090 VFMADD231PD	%ZMM26,%ZMM24,%ZMM16

0x406096 VMOVDQU64	0x120(%RSP),%YMM26    [3]

0x40609e VCVTPS2PD	%YMM0,%ZMM0

0x4060a4 VPADDD	%YMM13,%YMM23,%YMM23

0x4060aa VXORPD	%XMM25,%XMM25,%XMM25

0x4060b0 KXNORW	%K0,%K0,%K1

0x4060b4 VGATHERDPS	(%R10,%YMM23,4),%YMM25{%K1}    [2]

0x4060bb VFMADD231PD	%ZMM0,%ZMM24,%ZMM15

0x4060c1 VCVTPS2PD	%YMM25,%ZMM0

0x4060c7 VFMADD231PD	%ZMM0,%ZMM24,%ZMM14

0x4060cd ADD	$0x8,%RSI

0x4060d1 CMP	%R8,%RSI

0x4060d4 JB	405f70

/home/eoseret/llm-attention/attention.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P0,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.00
CQA cycles if no scalar integer	24.33
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	18.00
Front-end cycles	18.00
P0 cycles	27.00
P1 cycles	25.50
P2 cycles	24.33
P3 cycles	24.33
P4 cycles	0.00
P5 cycles	25.50
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	24.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	108.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	4.74
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.85
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	96.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	93.10
Vector-efficiency ratio all	51.75
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	39.22

Metric	Value
CQA speedup if no scalar integer	1.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P0,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.00
CQA cycles if no scalar integer	24.33
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	18.00
Front-end cycles	18.00
P0 cycles	27.00
P1 cycles	25.50
P2 cycles	24.33
P3 cycles	24.33
P4 cycles	0.00
P5 cycles	25.50
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	24.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	108.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	4.74
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.85
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	96.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	93.10
Vector-efficiency ratio all	51.75
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	39.22

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.00 to 24.33 cycles (1.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 51% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 27.00 to 18.00 cycles (1.50x speedup).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.00 to 25.50 cycles (1.06x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.40 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	108
loop length	362
used x86 registers	7
used mmx registers	0
used xmm registers	9
used ymm registers	21
used zmm registers	12
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	27.00	25.50	24.33	24.33	0.00	25.50	1.00	0.00	0.00	0.00	1.00	24.33
cycles	27.00	25.50	24.33	24.33	0.00	25.50	1.00	0.00	0.00	0.00	1.00	24.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	18.00
Dispatch	27.00
Data deps.	4.00
Overall L1	27.00

Vectorization ratios

INT

all	87%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	96%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

Vector efficiency ratios

INT

all	42%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	55%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

INT+FP

all	51%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

6% of peak load performance is reached (11.85 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405f70

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R11,%RSI,1),%EBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %EBX,%YMM23	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM3,%YMM23,%YMM23	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM23,4),%YMM24{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPBROADCASTD %ESI,%YMM23	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM1,%YMM23,%YMM23	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM23,%YMM26,%YMM23	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM22,%YMM23,%YMM23	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM2,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXORD %XMM26,%XMM26,%XMM26	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM26{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM7,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM27{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM8,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM28{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM9,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM29{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM10,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM30{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM11,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM31,%XMM31,%XMM31	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM31{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM12,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM0{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM24,%ZMM24	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM26,%ZMM25	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM27,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM25,%ZMM24,%ZMM21	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM24,%ZMM20	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM28,%ZMM25	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM29,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM25,%ZMM24,%ZMM19	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM24,%ZMM18	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM30,%ZMM25	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM31,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM25,%ZMM24,%ZMM17	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM24,%ZMM16	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVDQU64 0x120(%RSP),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VCVTPS2PD %YMM0,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VPADDD %YMM13,%YMM23,%YMM23	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM23,4),%YMM25{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM24,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM25,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM24,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 405f70 <main+0x15f0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.40 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	108
loop length	362
used x86 registers	7
used mmx registers	0
used xmm registers	9
used ymm registers	21
used zmm registers	12
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	27.00	25.50	24.33	24.33	0.00	25.50	1.00	0.00	0.00	0.00	1.00	24.33
cycles	27.00	25.50	24.33	24.33	0.00	25.50	1.00	0.00	0.00	0.00	1.00	24.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	18.00
Dispatch	27.00
Data deps.	4.00
Overall L1	27.00

Vectorization ratios

INT

all	87%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	96%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

Vector efficiency ratios

INT

all	42%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	55%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

INT+FP

all	51%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

6% of peak load performance is reached (11.85 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405f70

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R11,%RSI,1),%EBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %EBX,%YMM23	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM3,%YMM23,%YMM23	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPD %XMM24,%XMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM23,4),%YMM24{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPBROADCASTD %ESI,%YMM23	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM1,%YMM23,%YMM23	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM23,%YMM26,%YMM23	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM22,%YMM23,%YMM23	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM2,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXORD %XMM26,%XMM26,%XMM26	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM26{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM7,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM27{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM8,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM28{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM9,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM29{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM10,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM30{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM11,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM31,%XMM31,%XMM31	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM31{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM12,%YMM23,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM25,4),%YMM0{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM24,%ZMM24	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM26,%ZMM25	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM27,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM25,%ZMM24,%ZMM21	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM24,%ZMM20	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM28,%ZMM25	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM29,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM25,%ZMM24,%ZMM19	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM24,%ZMM18	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM30,%ZMM25	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM31,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM25,%ZMM24,%ZMM17	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM26,%ZMM24,%ZMM16	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVDQU64 0x120(%RSP),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VCVTPS2PD %YMM0,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VPADDD %YMM13,%YMM23,%YMM23	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPD %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM23,4),%YMM25{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM24,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM25,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM24,%ZMM14	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 405f70 <main+0x15f0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code