| Loop Id: 62 | Module: attention-avx512 | Source: attention.cpp:27-33 | Coverage: 0.98% |
|---|
| Loop Id: 62 | Module: attention-avx512 | Source: attention.cpp:27-33 | Coverage: 0.98% |
|---|
0x405e80 VMOVDQU64 0x180(%RSP),%ZMM22 |
0x405e88 VCVTSD2SS %XMM21,%XMM21,%XMM0 |
0x405e8e LEA (%RCX,%RDI,1),%ESI |
0x405e91 VMOVSS %XMM0,(%R13,%RSI,4) |
0x405e98 VCVTSD2SS %XMM20,%XMM20,%XMM0 |
0x405e9e LEA 0x1(%RCX,%RDI,1),%ESI |
0x405ea2 VMOVSS %XMM0,(%R13,%RSI,4) |
0x405ea9 VCVTSD2SS %XMM19,%XMM19,%XMM0 |
0x405eaf LEA 0x2(%RCX,%RDI,1),%ESI |
0x405eb3 VMOVSS %XMM0,(%R13,%RSI,4) |
0x405eba VCVTSD2SS %XMM18,%XMM18,%XMM0 |
0x405ec0 LEA 0x3(%RCX,%RDI,1),%ESI |
0x405ec4 VMOVSS %XMM0,(%R13,%RSI,4) |
0x405ecb VCVTSD2SS %XMM17,%XMM17,%XMM0 |
0x405ed1 LEA 0x4(%RCX,%RDI,1),%ESI |
0x405ed5 VMOVSS %XMM0,(%R13,%RSI,4) |
0x405edc VCVTSD2SS %XMM16,%XMM16,%XMM0 |
0x405ee2 LEA 0x5(%RCX,%RDI,1),%ESI |
0x405ee6 VMOVSS %XMM0,(%R13,%RSI,4) |
0x405eed VCVTSD2SS %XMM15,%XMM15,%XMM0 |
0x405ef2 LEA 0x6(%RCX,%RDI,1),%ESI |
0x405ef6 VMOVSS %XMM0,(%R13,%RSI,4) |
0x405efd VCVTSD2SS %XMM14,%XMM14,%XMM0 |
0x405f02 LEA 0x7(%RCX,%RDI,1),%ESI |
0x405f06 VMOVSS %XMM0,(%R13,%RSI,4) |
0x405f0d ADD $0x8,%EDX |
0x405f10 CMP 0x1c0(%RSP),%RAX |
0x405f18 LEA 0x1(%RAX),%RAX |
0x405f1c JE 405c72 |
0x405f22 LEA (,%RAX,8),%EDI |
0x405f29 TEST %R8,%R8 |
0x405f2c JE 406280 |
0x405f32 VPBROADCASTD %EDI,%YMM22 |
0x405f38 VXORPD %XMM21,%XMM21,%XMM21 |
0x405f3e XOR %ESI,%ESI |
0x405f40 VXORPD %XMM20,%XMM20,%XMM20 |
0x405f46 VXORPD %XMM19,%XMM19,%XMM19 |
0x405f4c VXORPD %XMM18,%XMM18,%XMM18 |
0x405f52 VXORPD %XMM17,%XMM17,%XMM17 |
0x405f58 VXORPD %XMM16,%XMM16,%XMM16 |
0x405f5e VXORPD %XMM15,%XMM15,%XMM15 |
0x405f63 VXORPD %XMM14,%XMM14,%XMM14 |
0x405f68 NOPL (%RAX,%RAX,1) |
(63) 0x405f70 LEA (%R11,%RSI,1),%EBX |
(63) 0x405f74 VPBROADCASTD %EBX,%YMM23 |
(63) 0x405f7a VPADDD %YMM3,%YMM23,%YMM23 |
(63) 0x405f80 VXORPD %XMM24,%XMM24,%XMM24 |
(63) 0x405f86 KXNORW %K0,%K0,%K1 |
(63) 0x405f8a VGATHERDPS (%R9,%YMM23,4),%YMM24{%K1} |
(63) 0x405f91 VPBROADCASTD %ESI,%YMM23 |
(63) 0x405f97 VPADDD %YMM1,%YMM23,%YMM23 |
(63) 0x405f9d VPMULLD %YMM23,%YMM26,%YMM23 |
(63) 0x405fa3 VPADDD %YMM22,%YMM23,%YMM23 |
(63) 0x405fa9 VPSUBD %YMM2,%YMM23,%YMM25 |
(63) 0x405faf VPXORD %XMM26,%XMM26,%XMM26 |
(63) 0x405fb5 KXNORW %K0,%K0,%K1 |
(63) 0x405fb9 VGATHERDPS (%R10,%YMM25,4),%YMM26{%K1} |
(63) 0x405fc0 VPADDD %YMM7,%YMM23,%YMM25 |
(63) 0x405fc6 VXORPS %XMM27,%XMM27,%XMM27 |
(63) 0x405fcc KXNORW %K0,%K0,%K1 |
(63) 0x405fd0 VGATHERDPS (%R10,%YMM25,4),%YMM27{%K1} |
(63) 0x405fd7 VPADDD %YMM8,%YMM23,%YMM25 |
(63) 0x405fdd VXORPS %XMM28,%XMM28,%XMM28 |
(63) 0x405fe3 KXNORW %K0,%K0,%K1 |
(63) 0x405fe7 VGATHERDPS (%R10,%YMM25,4),%YMM28{%K1} |
(63) 0x405fee VPADDD %YMM9,%YMM23,%YMM25 |
(63) 0x405ff4 VXORPS %XMM29,%XMM29,%XMM29 |
(63) 0x405ffa KXNORW %K0,%K0,%K1 |
(63) 0x405ffe VGATHERDPS (%R10,%YMM25,4),%YMM29{%K1} |
(63) 0x406005 VPADDD %YMM10,%YMM23,%YMM25 |
(63) 0x40600b VXORPS %XMM30,%XMM30,%XMM30 |
(63) 0x406011 KXNORW %K0,%K0,%K1 |
(63) 0x406015 VGATHERDPS (%R10,%YMM25,4),%YMM30{%K1} |
(63) 0x40601c VPADDD %YMM11,%YMM23,%YMM25 |
(63) 0x406022 VXORPS %XMM31,%XMM31,%XMM31 |
(63) 0x406028 KXNORW %K0,%K0,%K1 |
(63) 0x40602c VGATHERDPS (%R10,%YMM25,4),%YMM31{%K1} |
(63) 0x406033 VPADDD %YMM12,%YMM23,%YMM25 |
(63) 0x406039 VXORPS %XMM0,%XMM0,%XMM0 |
(63) 0x40603d KXNORW %K0,%K0,%K1 |
(63) 0x406041 VGATHERDPS (%R10,%YMM25,4),%YMM0{%K1} |
(63) 0x406048 VCVTPS2PD %YMM24,%ZMM24 |
(63) 0x40604e VCVTPS2PD %YMM26,%ZMM25 |
(63) 0x406054 VCVTPS2PD %YMM27,%ZMM26 |
(63) 0x40605a VFMADD231PD %ZMM25,%ZMM24,%ZMM21 |
(63) 0x406060 VFMADD231PD %ZMM26,%ZMM24,%ZMM20 |
(63) 0x406066 VCVTPS2PD %YMM28,%ZMM25 |
(63) 0x40606c VCVTPS2PD %YMM29,%ZMM26 |
(63) 0x406072 VFMADD231PD %ZMM25,%ZMM24,%ZMM19 |
(63) 0x406078 VFMADD231PD %ZMM26,%ZMM24,%ZMM18 |
(63) 0x40607e VCVTPS2PD %YMM30,%ZMM25 |
(63) 0x406084 VCVTPS2PD %YMM31,%ZMM26 |
(63) 0x40608a VFMADD231PD %ZMM25,%ZMM24,%ZMM17 |
(63) 0x406090 VFMADD231PD %ZMM26,%ZMM24,%ZMM16 |
(63) 0x406096 VMOVDQU64 0x120(%RSP),%YMM26 |
(63) 0x40609e VCVTPS2PD %YMM0,%ZMM0 |
(63) 0x4060a4 VPADDD %YMM13,%YMM23,%YMM23 |
(63) 0x4060aa VXORPD %XMM25,%XMM25,%XMM25 |
(63) 0x4060b0 KXNORW %K0,%K0,%K1 |
(63) 0x4060b4 VGATHERDPS (%R10,%YMM23,4),%YMM25{%K1} |
(63) 0x4060bb VFMADD231PD %ZMM0,%ZMM24,%ZMM15 |
(63) 0x4060c1 VCVTPS2PD %YMM25,%ZMM0 |
(63) 0x4060c7 VFMADD231PD %ZMM0,%ZMM24,%ZMM14 |
(63) 0x4060cd ADD $0x8,%RSI |
(63) 0x4060d1 CMP %R8,%RSI |
(63) 0x4060d4 JB 405f70 |
0x4060da VEXTRACTF64X4 $0x1,%ZMM21,%YMM0 |
0x4060e1 VADDPD %ZMM0,%ZMM21,%ZMM0 |
0x4060e7 VMOVAPD %XMM0,%XMM21 |
0x4060ed VEXTRACTF128 $0x1,%YMM0,%XMM0 |
0x4060f3 VADDPD %XMM0,%XMM21,%XMM0 |
0x4060f9 VSHUFPD $0x1,%XMM0,%XMM0,%XMM21 |
0x406100 VADDSD %XMM21,%XMM0,%XMM21 |
0x406106 VEXTRACTF64X4 $0x1,%ZMM20,%YMM0 |
0x40610d VADDPD %ZMM0,%ZMM20,%ZMM0 |
0x406113 VMOVAPD %XMM0,%XMM20 |
0x406119 VEXTRACTF128 $0x1,%YMM0,%XMM0 |
0x40611f VADDPD %XMM0,%XMM20,%XMM0 |
0x406125 VSHUFPD $0x1,%XMM0,%XMM0,%XMM20 |
0x40612c VADDSD %XMM20,%XMM0,%XMM20 |
0x406132 VEXTRACTF64X4 $0x1,%ZMM19,%YMM0 |
0x406139 VADDPD %ZMM0,%ZMM19,%ZMM0 |
0x40613f VMOVAPD %XMM0,%XMM19 |
0x406145 VEXTRACTF128 $0x1,%YMM0,%XMM0 |
0x40614b VADDPD %XMM0,%XMM19,%XMM0 |
0x406151 VSHUFPD $0x1,%XMM0,%XMM0,%XMM19 |
0x406158 VADDSD %XMM19,%XMM0,%XMM19 |
0x40615e VEXTRACTF64X4 $0x1,%ZMM18,%YMM0 |
0x406165 VADDPD %ZMM0,%ZMM18,%ZMM0 |
0x40616b VMOVAPD %XMM0,%XMM18 |
0x406171 VEXTRACTF128 $0x1,%YMM0,%XMM0 |
0x406177 VADDPD %XMM0,%XMM18,%XMM0 |
0x40617d VSHUFPD $0x1,%XMM0,%XMM0,%XMM18 |
0x406184 VADDSD %XMM18,%XMM0,%XMM18 |
0x40618a VEXTRACTF64X4 $0x1,%ZMM17,%YMM0 |
0x406191 VADDPD %ZMM0,%ZMM17,%ZMM0 |
0x406197 VMOVAPD %XMM0,%XMM17 |
0x40619d VEXTRACTF128 $0x1,%YMM0,%XMM0 |
0x4061a3 VADDPD %XMM0,%XMM17,%XMM0 |
0x4061a9 VSHUFPD $0x1,%XMM0,%XMM0,%XMM17 |
0x4061b0 VADDSD %XMM17,%XMM0,%XMM17 |
0x4061b6 VEXTRACTF64X4 $0x1,%ZMM16,%YMM0 |
0x4061bd VADDPD %ZMM0,%ZMM16,%ZMM0 |
0x4061c3 VMOVAPD %XMM0,%XMM16 |
0x4061c9 VEXTRACTF128 $0x1,%YMM0,%XMM0 |
0x4061cf VADDPD %XMM0,%XMM16,%XMM0 |
0x4061d5 VSHUFPD $0x1,%XMM0,%XMM0,%XMM16 |
0x4061dc VADDSD %XMM16,%XMM0,%XMM16 |
0x4061e2 VEXTRACTF64X4 $0x1,%ZMM15,%YMM0 |
0x4061e9 VADDPD %ZMM0,%ZMM15,%ZMM0 |
0x4061ef VMOVAPD %XMM0,%XMM15 |
0x4061f3 VEXTRACTF128 $0x1,%YMM0,%XMM0 |
0x4061f9 VADDPD %XMM0,%XMM15,%XMM0 |
0x4061fd VSHUFPD $0x1,%XMM0,%XMM0,%XMM15 |
0x406202 VADDSD %XMM0,%XMM15,%XMM15 |
0x406206 VEXTRACTF64X4 $0x1,%ZMM14,%YMM0 |
0x40620d VADDPD %ZMM0,%ZMM14,%ZMM0 |
0x406213 VMOVAPD %XMM0,%XMM14 |
0x406217 VEXTRACTF128 $0x1,%YMM0,%XMM0 |
0x40621d VADDPD %XMM0,%XMM14,%XMM0 |
0x406221 VSHUFPD $0x1,%XMM0,%XMM0,%XMM14 |
0x406226 VADDSD %XMM0,%XMM14,%XMM14 |
0x40622a CMP %R8D,%R15D |
0x40622d JE 405e80 |
0x406233 VPUNPCKLQDQ %XMM21,%XMM20,%XMM0 |
0x406239 VPUNPCKLQDQ %XMM19,%XMM18,%XMM18 |
0x40623f VINSERTF32X4 $0x1,%XMM0,%YMM18,%YMM0 |
0x406246 VPUNPCKLQDQ %XMM17,%XMM16,%XMM16 |
0x40624c VPUNPCKLQDQ %XMM15,%XMM14,%XMM14 |
0x406251 VINSERTF32X4 $0x1,%XMM16,%YMM14,%YMM14 |
0x406258 VINSERTF64X4 $0x1,%YMM0,%ZMM14,%ZMM14 |
0x40625f MOV %R8,%RSI |
0x406262 VMOVDQU64 0x180(%RSP),%ZMM22 |
0x40626a JMP 406287 |
0x406280 VXORPD %XMM14,%XMM14,%XMM14 |
0x406285 XOR %ESI,%ESI |
0x406287 MOV 0x40(%RSP),%R15 |
0x40628c MOV %R15D,%EBX |
0x40628f IMUL %ESI,%EBX |
0x406292 MOV %RDX,0x30(%RSP) |
0x406297 ADD %EDX,%EBX |
0x406299 MOV 0x88(%RSP),%RDX |
0x4062a1 NOPW %CS:(%RAX,%RAX,1) |
(57) 0x4062b0 LEA (%R11,%RSI,1),%R14D |
(57) 0x4062b4 VMOVSS (%R12,%R14,4),%XMM0 |
(57) 0x4062ba VCVTSS2SD %XMM0,%XMM0,%XMM0 |
(57) 0x4062be LEA 0x3(%RBX),%R14D |
(57) 0x4062c2 VPBROADCASTD %EBX,%YMM15 |
(57) 0x4062c8 VPADDD %YMM4,%YMM15,%YMM7 |
(57) 0x4062cc VPBROADCASTD %R14D,%YMM8 |
(57) 0x4062d2 VPBLENDD $0x10,%YMM8,%YMM7,%YMM7 |
(57) 0x4062d8 VPADDD %YMM5,%YMM15,%YMM8 |
(57) 0x4062dc VPERMT2D %YMM8,%YMM6,%YMM7 |
(57) 0x4062e2 VPBLENDD $-0x80,%YMM15,%YMM7,%YMM7 |
(57) 0x4062e8 VPSUBD %YMM2,%YMM7,%YMM7 |
(57) 0x4062ec VPXOR %XMM8,%XMM8,%XMM8 |
(57) 0x4062f1 KXNORW %K0,%K0,%K1 |
(57) 0x4062f5 VGATHERDPS (%R10,%YMM7,4),%YMM8{%K1} |
(57) 0x4062fc VCVTPS2PD %YMM8,%ZMM7 |
(57) 0x406302 VBROADCASTSD %XMM0,%ZMM0 |
(57) 0x406308 VFMADD231PD %ZMM0,%ZMM7,%ZMM14 |
(57) 0x40630e INC %RSI |
(57) 0x406311 ADD %R15D,%EBX |
(57) 0x406314 CMP %RSI,%RDX |
(57) 0x406317 JNE 4062b0 |
0x406319 VEXTRACTF32X4 $0x3,%ZMM14,%XMM20 |
0x406320 VSHUFPD $0x1,%XMM20,%XMM20,%XMM21 |
0x406327 VEXTRACTF32X4 $0x2,%ZMM14,%XMM18 |
0x40632e VSHUFPD $0x1,%XMM18,%XMM18,%XMM19 |
0x406335 VMOVAPD %YMM14,%YMM0 |
0x406339 VEXTRACTF32X4 $0x1,%YMM14,%XMM16 |
0x406340 VSHUFPD $0x1,%XMM16,%XMM16,%XMM17 |
0x406347 VSHUFPD $0x1,%XMM0,%XMM0,%XMM15 |
0x40634c MOV 0x98(%RSP),%R14 |
0x406354 MOV %RDX,%R15 |
0x406357 VPBROADCASTD 0xa084(%RIP),%YMM7 |
0x406360 VPBROADCASTD 0xa07f(%RIP),%YMM8 |
0x406369 MOV 0x30(%RSP),%RDX |
0x40636e JMP 405e88 |
/home/eoseret/llm-attention/attention.cpp: 27 - 33 |
-------------------------------------------------------------------------------- |
27: for (unsigned int j = 0; j < N; ++j) { //vectorized |
28: double sum = 0.0; |
29: #pragma clang loop vectorize(enable) |
30: for (unsigned int k = 0; k < K; ++k) { //vectorized |
31: sum += (double)A[i * K + k] * (double)B[k * N + j]; |
32: } |
33: C[i * N + j] = alpha * static_cast<float>(sum); |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.06 |
| CQA speedup if FP arith vectorized | 1.12 |
| CQA speedup if fully vectorized | 3.21 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | |
| Function | main |
| Source | attention.cpp:27-27,attention.cpp:30-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 25.17 |
| CQA cycles if no scalar integer | 23.83 |
| CQA cycles if FP arith vectorized | 22.50 |
| CQA cycles if fully vectorized | 7.83 |
| Front-end cycles | 17.17 |
| P0 cycles | 13.17 |
| P1 cycles | 25.17 |
| P2 cycles | 1.89 |
| P3 cycles | 1.89 |
| P4 cycles | 4.33 |
| P5 cycles | 25.00 |
| P6 cycles | 4.33 |
| P7 cycles | 4.33 |
| P8 cycles | 4.33 |
| P9 cycles | 4.33 |
| P10 cycles | 4.33 |
| P11 cycles | 1.89 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 95.33 |
| Nb uops | 103.00 |
| Nb loads | 5.67 |
| Nb stores | 8.67 |
| Nb stack references | 4.33 |
| FLOP/cycle | 2.33 |
| Nb FLOP add-sub | 58.67 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 5.19 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 77.33 |
| Bytes stored | 37.33 |
| Stride 0 | 0.67 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.67 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 52.83 |
| Vectorization ratio load | 22.22 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 65.33 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 64.07 |
| Vector-efficiency ratio all | 24.58 |
| Vector-efficiency ratio load | 30.42 |
| Vector-efficiency ratio store | 6.71 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 45.04 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 23.04 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.05 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 6.57 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.11 |
| Bottlenecks | P1, P5, |
| Function | main |
| Source | attention.cpp:27-27,attention.cpp:30-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 11.50 |
| CQA cycles if no scalar integer | 11.00 |
| CQA cycles if FP arith vectorized | 11.50 |
| CQA cycles if fully vectorized | 1.75 |
| Front-end cycles | 10.33 |
| P0 cycles | 8.00 |
| P1 cycles | 11.50 |
| P2 cycles | 2.33 |
| P3 cycles | 2.33 |
| P4 cycles | 4.50 |
| P5 cycles | 11.50 |
| P6 cycles | 4.00 |
| P7 cycles | 4.50 |
| P8 cycles | 4.50 |
| P9 cycles | 4.50 |
| P10 cycles | 4.00 |
| P11 cycles | 2.33 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 54.00 |
| Nb uops | 62.00 |
| Nb loads | 7.00 |
| Nb stores | 9.00 |
| Nb stack references | 5.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 7.65 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 48.00 |
| Bytes stored | 40.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 1.00 |
| Vectorization ratio all | 27.27 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 40.91 |
| Vector-efficiency ratio all | 14.77 |
| Vector-efficiency ratio load | 10.00 |
| Vector-efficiency ratio store | 6.94 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.18 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.04 |
| CQA speedup if FP arith vectorized | 1.15 |
| CQA speedup if fully vectorized | 2.93 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.53 |
| Bottlenecks | P1, P5, |
| Function | main |
| Source | attention.cpp:27-27,attention.cpp:30-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 35.50 |
| CQA cycles if no scalar integer | 34.00 |
| CQA cycles if FP arith vectorized | 31.00 |
| CQA cycles if fully vectorized | 12.14 |
| Front-end cycles | 23.17 |
| P0 cycles | 16.00 |
| P1 cycles | 35.50 |
| P2 cycles | 2.67 |
| P3 cycles | 2.67 |
| P4 cycles | 4.50 |
| P5 cycles | 35.50 |
| P6 cycles | 5.00 |
| P7 cycles | 4.50 |
| P8 cycles | 4.50 |
| P9 cycles | 4.50 |
| P10 cycles | 5.00 |
| P11 cycles | 2.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 131.00 |
| Nb uops | 139.00 |
| Nb loads | 8.00 |
| Nb stores | 9.00 |
| Nb stack references | 6.00 |
| FLOP/cycle | 2.48 |
| Nb FLOP add-sub | 88.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.28 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 112.00 |
| Bytes stored | 40.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 3.00 |
| Vectorization ratio all | 64.15 |
| Vectorization ratio load | 16.67 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 66.67 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 72.86 |
| Vector-efficiency ratio all | 28.54 |
| Vector-efficiency ratio load | 25.00 |
| Vector-efficiency ratio store | 6.94 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 45.83 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 24.82 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.08 |
| CQA speedup if FP arith vectorized | 1.14 |
| CQA speedup if fully vectorized | 2.97 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.02 |
| Bottlenecks | P1, |
| Function | main |
| Source | attention.cpp:27-27,attention.cpp:30-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 28.50 |
| CQA cycles if no scalar integer | 26.50 |
| CQA cycles if FP arith vectorized | 25.00 |
| CQA cycles if fully vectorized | 9.60 |
| Front-end cycles | 18.00 |
| P0 cycles | 15.50 |
| P1 cycles | 28.50 |
| P2 cycles | 0.67 |
| P3 cycles | 0.67 |
| P4 cycles | 4.00 |
| P5 cycles | 28.00 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 4.00 |
| P10 cycles | 4.00 |
| P11 cycles | 0.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 101.00 |
| Nb uops | 108.00 |
| Nb loads | 2.00 |
| Nb stores | 8.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 3.09 |
| Nb FLOP add-sub | 88.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 3.65 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 72.00 |
| Bytes stored | 32.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 67.06 |
| Vectorization ratio load | 50.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 64.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 78.43 |
| Vector-efficiency ratio all | 30.44 |
| Vector-efficiency ratio load | 56.25 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 44.25 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 26.10 |
| Path / |
| Function | main |
| Source file and lines | attention.cpp:27-33 |
| Module | attention-avx512 |
| nb instructions | 95.33 |
| nb uops | 103 |
| loop length | 552.67 |
| used x86 registers | 10.33 |
| used mmx registers | 0 |
| used xmm registers | 9 |
| used ymm registers | 4 |
| used zmm registers | 7 |
| nb stack references | 4.33 |
| micro-operation queue | 17.17 cycles |
| front end | 17.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 13.17 | 25.17 | 1.89 | 1.89 | 4.33 | 25.00 | 4.33 | 4.33 | 4.33 | 4.33 | 4.33 | 1.89 |
| cycles | 13.17 | 25.17 | 1.89 | 1.89 | 4.33 | 25.00 | 4.33 | 4.33 | 4.33 | 4.33 | 4.33 | 1.89 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 17.17 |
| Dispatch | 25.17 |
| Data deps. | 0.00 |
| Overall L1 | 25.17 |
| all | 8% |
| load | 22% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 59% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 74% |
| all | 52% |
| load | 22% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 65% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 64% |
| all | 18% |
| load | 30% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 45% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 24% |
| load | 30% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 45% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 23% |
| Function | main |
| Source file and lines | attention.cpp:27-33 |
| Module | attention-avx512 |
| nb instructions | 54 |
| nb uops | 62 |
| loop length | 308 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 9 |
| used ymm registers | 4 |
| used zmm registers | 1 |
| nb stack references | 5 |
| micro-operation queue | 10.33 cycles |
| front end | 10.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 11.50 | 2.33 | 2.33 | 4.50 | 11.50 | 4.00 | 4.50 | 4.50 | 4.50 | 4.00 | 2.33 |
| cycles | 8.00 | 11.50 | 2.33 | 2.33 | 4.50 | 11.50 | 4.00 | 4.50 | 4.50 | 4.50 | 4.00 | 2.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 10.33 |
| Dispatch | 11.50 |
| Data deps. | 0.00 |
| Overall L1 | 11.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 36% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 52% |
| all | 27% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 40% |
| all | 10% |
| load | 10% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 16% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| all | 14% |
| load | 10% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCVTSD2SS %XMM21,%XMM21,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA (%RCX,%RDI,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM20,%XMM20,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x1(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM19,%XMM19,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x2(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM18,%XMM18,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x3(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM17,%XMM17,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x4(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM16,%XMM16,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x5(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM15,%XMM15,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x6(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM14,%XMM14,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x7(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| ADD $0x8,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| CMP 0x1c0(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| LEA 0x1(%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JE 405c72 <main+0x12f2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| LEA (,%RAX,8),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | scal (12.5%) |
| JE 406280 <main+0x1900> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VXORPD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x40(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %R15D,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| IMUL %ESI,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %RDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| ADD %EDX,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x88(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VEXTRACTF32X4 $0x3,%ZMM14,%XMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VSHUFPD $0x1,%XMM20,%XMM20,%XMM21 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VEXTRACTF32X4 $0x2,%ZMM14,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VSHUFPD $0x1,%XMM18,%XMM18,%XMM19 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VMOVAPD %YMM14,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (50.0%) |
| VEXTRACTF32X4 $0x1,%YMM14,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VSHUFPD $0x1,%XMM16,%XMM16,%XMM17 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| MOV 0x98(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| VPBROADCASTD 0xa084(%RIP),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (6.3%) |
| VPBROADCASTD 0xa07f(%RIP),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (6.3%) |
| MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| JMP 405e88 <main+0x1508> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| Function | main |
| Source file and lines | attention.cpp:27-33 |
| Module | attention-avx512 |
| nb instructions | 131 |
| nb uops | 139 |
| loop length | 765 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 9 |
| used ymm registers | 6 |
| used zmm registers | 10 |
| nb stack references | 6 |
| micro-operation queue | 23.17 cycles |
| front end | 23.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 16.00 | 35.50 | 2.67 | 2.67 | 4.50 | 35.50 | 5.00 | 4.50 | 4.50 | 4.50 | 5.00 | 2.67 |
| cycles | 16.00 | 35.50 | 2.67 | 2.67 | 4.50 | 35.50 | 5.00 | 4.50 | 4.50 | 4.50 | 5.00 | 2.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 23.17 |
| Dispatch | 35.50 |
| Data deps. | 0.00 |
| Overall L1 | 35.50 |
| all | 6% |
| load | 16% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 73% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 86% |
| all | 64% |
| load | 16% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 72% |
| all | 16% |
| load | 25% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 30% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 45% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 27% |
| all | 28% |
| load | 25% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 45% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 24% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCVTSD2SS %XMM21,%XMM21,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA (%RCX,%RDI,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM20,%XMM20,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x1(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM19,%XMM19,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x2(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM18,%XMM18,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x3(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM17,%XMM17,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x4(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM16,%XMM16,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x5(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM15,%XMM15,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x6(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM14,%XMM14,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x7(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| ADD $0x8,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| CMP 0x1c0(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| LEA 0x1(%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JE 405c72 <main+0x12f2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| LEA (,%RAX,8),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | scal (12.5%) |
| JE 406280 <main+0x1900> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VPBROADCASTD %EDI,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| VXORPD %XMM21,%XMM21,%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VXORPD %XMM20,%XMM20,%XMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM19,%XMM19,%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM18,%XMM18,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM17,%XMM17,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM16,%XMM16,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM15,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VEXTRACTF64X4 $0x1,%ZMM21,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM21,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM21,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM21 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM21,%XMM0,%XMM21 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM20,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM20,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM20,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM20 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM20,%XMM0,%XMM20 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM19,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM19,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM19,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM19 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM19,%XMM0,%XMM19 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM18,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM18,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM18,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM18 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM18,%XMM0,%XMM18 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM17,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM17,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM17,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM17 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM17,%XMM0,%XMM17 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM16,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM16,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM16,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM16 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM16,%XMM0,%XMM16 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM15,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM15,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM0,%XMM15,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM14,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM14,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM0,%XMM14,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| JE 405e80 <main+0x1500> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VPUNPCKLQDQ %XMM21,%XMM20,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VPUNPCKLQDQ %XMM19,%XMM18,%XMM18 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VINSERTF32X4 $0x1,%XMM0,%YMM18,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VPUNPCKLQDQ %XMM17,%XMM16,%XMM16 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VPUNPCKLQDQ %XMM15,%XMM14,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| VINSERTF32X4 $0x1,%XMM16,%YMM14,%YMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VINSERTF64X4 $0x1,%YMM0,%ZMM14,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVDQU64 0x180(%RSP),%ZMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 | vect (100.0%) |
| JMP 406287 <main+0x1907> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 | N/A |
| MOV 0x40(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %R15D,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| IMUL %ESI,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| MOV %RDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| ADD %EDX,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x88(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VEXTRACTF32X4 $0x3,%ZMM14,%XMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VSHUFPD $0x1,%XMM20,%XMM20,%XMM21 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VEXTRACTF32X4 $0x2,%ZMM14,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VSHUFPD $0x1,%XMM18,%XMM18,%XMM19 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VMOVAPD %YMM14,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (50.0%) |
| VEXTRACTF32X4 $0x1,%YMM14,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VSHUFPD $0x1,%XMM16,%XMM16,%XMM17 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| MOV 0x98(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %RDX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| VPBROADCASTD 0xa084(%RIP),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (6.3%) |
| VPBROADCASTD 0xa07f(%RIP),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (6.3%) |
| MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| JMP 405e88 <main+0x1508> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| Function | main |
| Source file and lines | attention.cpp:27-33 |
| Module | attention-avx512 |
| nb instructions | 101 |
| nb uops | 108 |
| loop length | 585 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 9 |
| used ymm registers | 2 |
| used zmm registers | 10 |
| nb stack references | 2 |
| micro-operation queue | 18.00 cycles |
| front end | 18.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 15.50 | 28.50 | 0.67 | 0.67 | 4.00 | 28.00 | 4.00 | 4.00 | 4.00 | 4.00 | 4.00 | 0.67 |
| cycles | 15.50 | 28.50 | 0.67 | 0.67 | 4.00 | 28.00 | 4.00 | 4.00 | 4.00 | 4.00 | 4.00 | 0.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 18.00 |
| Dispatch | 28.50 |
| Data deps. | 0.00 |
| Overall L1 | 28.50 |
| all | 20% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 70% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 83% |
| all | 67% |
| load | 50% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 64% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 78% |
| all | 27% |
| load | 56% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 30% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 45% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 27% |
| all | 30% |
| load | 56% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 44% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 26% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQU64 0x180(%RSP),%ZMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 | vect (100.0%) |
| VCVTSD2SS %XMM21,%XMM21,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA (%RCX,%RDI,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM20,%XMM20,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x1(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM19,%XMM19,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x2(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM18,%XMM18,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x3(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM17,%XMM17,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x4(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM16,%XMM16,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x5(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM15,%XMM15,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x6(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VCVTSD2SS %XMM14,%XMM14,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| LEA 0x7(%RCX,%RDI,1),%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
| VMOVSS %XMM0,(%R13,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| ADD $0x8,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| CMP 0x1c0(%RSP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| LEA 0x1(%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JE 405c72 <main+0x12f2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| LEA (,%RAX,8),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| TEST %R8,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | scal (12.5%) |
| JE 406280 <main+0x1900> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VPBROADCASTD %EDI,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| VXORPD %XMM21,%XMM21,%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VXORPD %XMM20,%XMM20,%XMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM19,%XMM19,%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM18,%XMM18,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM17,%XMM17,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM16,%XMM16,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM15,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| VXORPD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VEXTRACTF64X4 $0x1,%ZMM21,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM21,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM21,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM21 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM21,%XMM0,%XMM21 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM20,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM20,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM20,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM20 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM20,%XMM0,%XMM20 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM19,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM19,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM19,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM19 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM19,%XMM0,%XMM19 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM18,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM18,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM18,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM18 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM18,%XMM0,%XMM18 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM17,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM17,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM17,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM17 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM17,%XMM0,%XMM17 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM16,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM16,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM16,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM16 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM16,%XMM0,%XMM16 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM15,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM15,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM0,%XMM15,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| VEXTRACTF64X4 $0x1,%ZMM14,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM0,%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVAPD %XMM0,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 | vect (25.0%) |
| VEXTRACTF128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM0,%XMM14,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM0,%XMM0,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VADDSD %XMM0,%XMM14,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
| CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| JE 405e80 <main+0x1500> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
