OV - attention-avx512 - Loop 56

	Loop Id: 56	Module: attention-avx512	Source: attention.cpp:30-31	Coverage: 9.21%

0x406870 LEA	(%R11,%RSI,1),%EBX

0x406874 VPBROADCASTD	%EBX,%YMM24

0x40687a VPADDD	%YMM3,%YMM24,%YMM24

0x406880 VXORPS	%XMM25,%XMM25,%XMM25

0x406886 KXNORW	%K0,%K0,%K1

0x40688a VGATHERDPS	(%R9,%YMM24,4),%YMM25{%K1}    [1]

0x406891 VPBROADCASTD	%ESI,%YMM24

0x406897 VPADDD	%YMM1,%YMM24,%YMM24

0x40689d VPMULLD	%YMM24,%YMM26,%YMM24

0x4068a3 VPADDD	%YMM22,%YMM24,%YMM24

0x4068a9 VPSUBD	%YMM2,%YMM24,%YMM26

0x4068af VMOVAPS	%YMM27,%YMM4

0x4068b5 VXORPS	%XMM27,%XMM27,%XMM27

0x4068bb KXNORW	%K0,%K0,%K1

0x4068bf VGATHERDPS	(%R10,%YMM26,4),%YMM27{%K1}    [2]

0x4068c6 VPADDD	%YMM10,%YMM24,%YMM26

0x4068cc VXORPS	%XMM28,%XMM28,%XMM28

0x4068d2 KXNORW	%K0,%K0,%K1

0x4068d6 VGATHERDPS	(%R10,%YMM26,4),%YMM28{%K1}    [2]

0x4068dd VPADDD	%YMM9,%YMM24,%YMM26

0x4068e3 VXORPS	%XMM29,%XMM29,%XMM29

0x4068e9 KXNORW	%K0,%K0,%K1

0x4068ed VGATHERDPS	(%R10,%YMM26,4),%YMM29{%K1}    [2]

0x4068f4 VPADDD	%YMM30,%YMM24,%YMM26

0x4068fa VMOVDQA64	%YMM30,%YMM11

0x406900 VPXORD	%XMM30,%XMM30,%XMM30

0x406906 KXNORW	%K0,%K0,%K1

0x40690a VGATHERDPS	(%R10,%YMM26,4),%YMM30{%K1}    [2]

0x406911 VPADDD	%YMM31,%YMM24,%YMM26

0x406917 VMOVDQA64	%YMM31,%YMM12

0x40691d VPXORD	%XMM31,%XMM31,%XMM31

0x406923 KXNORW	%K0,%K0,%K1

0x406927 VGATHERDPS	(%R10,%YMM26,4),%YMM31{%K1}    [2]

0x40692e VPADDD	%YMM13,%YMM24,%YMM26

0x406934 VXORPS	%XMM0,%XMM0,%XMM0

0x406938 KXNORW	%K0,%K0,%K1

0x40693c VGATHERDPS	(%R10,%YMM26,4),%YMM0{%K1}    [2]

0x406943 VPADDD	%YMM14,%YMM24,%YMM26

0x406949 VPXOR	%XMM8,%XMM8,%XMM8

0x40694e KXNORW	%K0,%K0,%K1

0x406952 VGATHERDPS	(%R10,%YMM26,4),%YMM8{%K1}    [2]

0x406959 VCVTPS2PD	%YMM25,%ZMM25

0x40695f VCVTPS2PD	%YMM27,%ZMM26

0x406965 VCVTPS2PD	%YMM28,%ZMM27

0x40696b VFMADD231PD	%ZMM26,%ZMM25,%ZMM23

0x406971 VFMADD231PD	%ZMM27,%ZMM25,%ZMM21

0x406977 VCVTPS2PD	%YMM29,%ZMM26

0x40697d VCVTPS2PD	%YMM30,%ZMM27

0x406983 VMOVDQA64	%YMM11,%YMM30

0x406989 VFMADD231PD	%ZMM26,%ZMM25,%ZMM20

0x40698f VFMADD231PD	%ZMM27,%ZMM25,%ZMM19

0x406995 VMOVAPS	%YMM4,%YMM27

0x40699b VCVTPS2PD	%YMM31,%ZMM26

0x4069a1 VMOVDQA64	%YMM12,%YMM31

0x4069a7 VCVTPS2PD	%YMM0,%ZMM0

0x4069ad VFMADD231PD	%ZMM26,%ZMM25,%ZMM18

0x4069b3 VMOVDQU64	0x120(%RSP),%YMM26    [3]

0x4069bb VFMADD231PD	%ZMM0,%ZMM25,%ZMM17

0x4069c1 VCVTPS2PD	%YMM8,%ZMM0

0x4069c7 VPADDD	%YMM4,%YMM24,%YMM8

0x4069cd VPXORD	%XMM24,%XMM24,%XMM24

0x4069d3 KXNORW	%K0,%K0,%K1

0x4069d7 VGATHERDPS	(%R10,%YMM8,4),%YMM24{%K1}    [2]

0x4069de VFMADD231PD	%ZMM0,%ZMM25,%ZMM16

0x4069e4 VCVTPS2PD	%YMM24,%ZMM0

0x4069ea VFMADD231PD	%ZMM0,%ZMM25,%ZMM15

0x4069f0 ADD	$0x8,%RSI

0x4069f4 CMP	%R8,%RSI

0x4069f7 JB	406870

/home/eoseret/llm-attention/attention.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P0,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.00
CQA cycles if no scalar integer	24.33
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	18.00
Front-end cycles	19.00
P0 cycles	27.00
P1 cycles	26.50
P2 cycles	24.33
P3 cycles	24.33
P4 cycles	0.00
P5 cycles	26.50
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	24.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	114.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	4.74
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.85
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	96.43
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	94.29
Vector-efficiency ratio all	51.56
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	41.07

Metric	Value
CQA speedup if no scalar integer	1.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P0,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.00
CQA cycles if no scalar integer	24.33
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	18.00
Front-end cycles	19.00
P0 cycles	27.00
P1 cycles	26.50
P2 cycles	24.33
P3 cycles	24.33
P4 cycles	0.00
P5 cycles	26.50
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	24.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	114.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	4.74
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.85
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	96.43
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	94.29
Vector-efficiency ratio all	51.56
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	41.07

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.00 to 24.33 cycles (1.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 51% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 27.00 to 18.00 cycles (1.50x speedup).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.40 FP operations per loaded or stored byte.

General properties

nb instructions	69
nb uops	114
loop length	397
used x86 registers	7
used mmx registers	0
used xmm registers	9
used ymm registers	21
used zmm registers	12
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	19.00 cycles
front end	19.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	27.00	26.50	24.33	24.33	0.00	26.50	1.00	0.00	0.00	0.00	1.00	24.33
cycles	27.00	26.50	24.33	24.33	0.00	26.50	1.00	0.00	0.00	0.00	1.00	24.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	19.00
Dispatch	27.00
Data deps.	4.00
Overall L1	27.00

Vectorization ratios

INT

all	91%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	96%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Vector efficiency ratios

INT

all	41%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	58%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	51%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	41%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

6% of peak load performance is reached (11.85 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 406870

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R11,%RSI,1),%EBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %EBX,%YMM24	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM3,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM24,4),%YMM25{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPBROADCASTD %ESI,%YMM24	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM1,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM24,%YMM26,%YMM24	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM22,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM2,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VMOVAPS %YMM27,%YMM4	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VXORPS %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM27{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM10,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM28{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM9,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM29{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM30,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMOVDQA64 %YMM30,%YMM11	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPXORD %XMM30,%XMM30,%XMM30	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM30{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM31,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMOVDQA64 %YMM31,%YMM12	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPXORD %XMM31,%XMM31,%XMM31	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM31{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM13,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM0{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM14,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPXOR %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM8{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM25,%ZMM25	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM27,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM28,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM23	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM21	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM29,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM30,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VMOVDQA64 %YMM11,%YMM30	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM20	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM19	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVAPS %YMM4,%YMM27	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VCVTPS2PD %YMM31,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VMOVDQA64 %YMM12,%YMM31	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VCVTPS2PD %YMM0,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM18	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVDQU64 0x120(%RSP),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM25,%ZMM17	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM8,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VPADDD %YMM4,%YMM24,%YMM8	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPXORD %XMM24,%XMM24,%XMM24	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM8,4),%YMM24{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM25,%ZMM16	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM24,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM25,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 406870 <main+0x1ef0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.40 FP operations per loaded or stored byte.

General properties

nb instructions	69
nb uops	114
loop length	397
used x86 registers	7
used mmx registers	0
used xmm registers	9
used ymm registers	21
used zmm registers	12
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	19.00 cycles
front end	19.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	27.00	26.50	24.33	24.33	0.00	26.50	1.00	0.00	0.00	0.00	1.00	24.33
cycles	27.00	26.50	24.33	24.33	0.00	26.50	1.00	0.00	0.00	0.00	1.00	24.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	19.00
Dispatch	27.00
Data deps.	4.00
Overall L1	27.00

Vectorization ratios

INT

all	91%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	96%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Vector efficiency ratios

INT

all	41%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	58%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	51%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	41%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

6% of peak load performance is reached (11.85 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 406870

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R11,%RSI,1),%EBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %EBX,%YMM24	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM3,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM24,4),%YMM25{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPBROADCASTD %ESI,%YMM24	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM1,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM24,%YMM26,%YMM24	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM22,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM2,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VMOVAPS %YMM27,%YMM4	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VXORPS %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM27{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM10,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM28{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM9,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM29{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM30,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMOVDQA64 %YMM30,%YMM11	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPXORD %XMM30,%XMM30,%XMM30	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM30{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM31,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VMOVDQA64 %YMM31,%YMM12	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPXORD %XMM31,%XMM31,%XMM31	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM31{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM13,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM0{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM14,%YMM24,%YMM26	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPXOR %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM26,4),%YMM8{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM25,%ZMM25	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM27,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM28,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM23	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM21	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM29,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM30,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VMOVDQA64 %YMM11,%YMM30	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM20	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM19	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVAPS %YMM4,%YMM27	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VCVTPS2PD %YMM31,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VMOVDQA64 %YMM12,%YMM31	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VCVTPS2PD %YMM0,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM18	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVDQU64 0x120(%RSP),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM25,%ZMM17	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM8,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VPADDD %YMM4,%YMM24,%YMM8	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPXORD %XMM24,%XMM24,%XMM24	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R10,%YMM8,4),%YMM24{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM25,%ZMM16	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM24,%ZMM0	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM0,%ZMM25,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 406870 <main+0x1ef0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code