OV - attention-avx512 - Loop 42

	Loop Id: 42	Module: attention-avx512	Source: attention.cpp:27-33	Coverage: 5.02%

0x4074c0 VMOVSS	0x58(%RSP),%XMM25

0x4074c8 VPMOVSXBD	0x8faf(%RIP),%YMM7

0x4074d1 VCVTSD2SS	%XMM24,%XMM24,%XMM1

0x4074d7 VMULSS	%XMM25,%XMM1,%XMM1

0x4074dd LEA	(%RAX,%RDI,1),%ESI

0x4074e0 MOV	0x90(%RSP),%R9

0x4074e8 VMOVSS	%XMM1,(%R9,%RSI,4)

0x4074ee VCVTSD2SS	%XMM23,%XMM23,%XMM1

0x4074f4 VMULSS	%XMM25,%XMM1,%XMM1

0x4074fa LEA	0x1(%RAX,%RDI,1),%ESI

0x4074fe VMOVSS	%XMM1,(%R9,%RSI,4)

0x407504 VCVTSD2SS	%XMM22,%XMM22,%XMM1

0x40750a VMULSS	%XMM25,%XMM1,%XMM1

0x407510 LEA	0x2(%RAX,%RDI,1),%ESI

0x407514 VMOVSS	%XMM1,(%R9,%RSI,4)

0x40751a VCVTSD2SS	%XMM21,%XMM21,%XMM1

0x407520 VMULSS	%XMM25,%XMM1,%XMM1

0x407526 LEA	0x3(%RAX,%RDI,1),%ESI

0x40752a VMOVSS	%XMM1,(%R9,%RSI,4)

0x407530 VCVTSD2SS	%XMM20,%XMM20,%XMM1

0x407536 VMULSS	%XMM25,%XMM1,%XMM1

0x40753c LEA	0x4(%RAX,%RDI,1),%ESI

0x407540 VMOVSS	%XMM1,(%R9,%RSI,4)

0x407546 VCVTSD2SS	%XMM19,%XMM19,%XMM1

0x40754c VMULSS	%XMM25,%XMM1,%XMM1

0x407552 LEA	0x5(%RAX,%RDI,1),%ESI

0x407556 VMOVSS	%XMM1,(%R9,%RSI,4)

0x40755c VCVTSD2SS	%XMM18,%XMM18,%XMM1

0x407562 VMULSS	%XMM25,%XMM1,%XMM1

0x407568 LEA	0x6(%RAX,%RDI,1),%ESI

0x40756c VMOVSS	%XMM1,(%R9,%RSI,4)

0x407572 VCVTSD2SS	%XMM17,%XMM17,%XMM1

0x407578 VMULSS	%XMM25,%XMM1,%XMM1

0x40757e LEA	0x7(%RAX,%RDI,1),%ESI

0x407582 VMOVSS	%XMM1,(%R9,%RSI,4)

0x407588 MOV	0x30(%RSP),%R9

0x40758d ADD	$0x8,%R9D

0x407591 CMP	0x38(%RSP),%RDX

0x407596 LEA	0x1(%RDX),%RDX

0x40759a JE	4072a6

0x4075a0 LEA	(,%RDX,8),%EDI

0x4075a7 TEST	%R8,%R8

0x4075aa MOV	%R9,0x30(%RSP)

0x4075af JE	407900

0x4075b5 VPBROADCASTD	%EDI,%YMM24

0x4075bb VXORPD	%XMM17,%XMM17,%XMM17

0x4075c1 VXORPD	%XMM18,%XMM18,%XMM18

0x4075c7 VXORPD	%XMM19,%XMM19,%XMM19

0x4075cd VXORPD	%XMM20,%XMM20,%XMM20

0x4075d3 VXORPD	%XMM21,%XMM21,%XMM21

0x4075d9 VPXORD	%XMM22,%XMM22,%XMM22

0x4075df VXORPS	%XMM23,%XMM23,%XMM23

0x4075e5 VXORPS	%XMM25,%XMM25,%XMM25

0x4075eb XOR	%ESI,%ESI

0x4075ed VPBROADCASTD	0x8e0e(%RIP),%YMM6

0x4075f6 NOPW	%CS:(%RAX,%RAX,1)

  (43) 0x407600 LEA	(%RCX,%RSI,1),%EBX

  (43) 0x407603 VPBROADCASTD	%EBX,%YMM26

  (43) 0x407609 VPADDD	%YMM5,%YMM26,%YMM26

  (43) 0x40760f VXORPS	%XMM27,%XMM27,%XMM27

  (43) 0x407615 KXNORW	%K0,%K0,%K1

  (43) 0x407619 VGATHERDPS	(%R10,%YMM26,4),%YMM27{%K1}

  (43) 0x407620 VPBROADCASTD	%ESI,%YMM26

  (43) 0x407626 VPADDD	%YMM3,%YMM26,%YMM26

  (43) 0x40762c VPMULLD	%YMM26,%YMM0,%YMM26

  (43) 0x407632 VPADDD	%YMM24,%YMM26,%YMM26

  (43) 0x407638 VPSUBD	%YMM4,%YMM26,%YMM28

  (43) 0x40763e VXORPS	%XMM29,%XMM29,%XMM29

  (43) 0x407644 KXNORW	%K0,%K0,%K1

  (43) 0x407648 VGATHERDPS	(%R11,%YMM28,4),%YMM29{%K1}

  (43) 0x40764f VPADDD	%YMM30,%YMM26,%YMM28

  (43) 0x407655 VMOVDQA64	%YMM30,%YMM7

  (43) 0x40765b VPXORD	%XMM30,%XMM30,%XMM30

  (43) 0x407661 KXNORW	%K0,%K0,%K1

  (43) 0x407665 VGATHERDPS	(%R11,%YMM28,4),%YMM30{%K1}

  (43) 0x40766c VPADDD	%YMM13,%YMM26,%YMM28

  (43) 0x407672 VXORPS	%XMM31,%XMM31,%XMM31

  (43) 0x407678 KXNORW	%K0,%K0,%K1

  (43) 0x40767c VGATHERDPS	(%R11,%YMM28,4),%YMM31{%K1}

  (43) 0x407683 VPADDD	%YMM14,%YMM26,%YMM28

  (43) 0x407689 VXORPS	%XMM2,%XMM2,%XMM2

  (43) 0x40768d KXNORW	%K0,%K0,%K1

  (43) 0x407691 VGATHERDPS	(%R11,%YMM28,4),%YMM2{%K1}

  (43) 0x407698 VPADDD	%YMM15,%YMM26,%YMM28

  (43) 0x40769e VXORPS	%XMM1,%XMM1,%XMM1

  (43) 0x4076a2 KXNORW	%K0,%K0,%K1

  (43) 0x4076a6 VGATHERDPS	(%R11,%YMM28,4),%YMM1{%K1}

  (43) 0x4076ad VPADDD	%YMM16,%YMM26,%YMM28

  (43) 0x4076b3 VPXOR	%XMM10,%XMM10,%XMM10

  (43) 0x4076b8 KXNORW	%K0,%K0,%K1

  (43) 0x4076bc VGATHERDPS	(%R11,%YMM28,4),%YMM10{%K1}

  (43) 0x4076c3 VPADDD	%YMM6,%YMM26,%YMM28

  (43) 0x4076c9 VPXOR	%XMM11,%XMM11,%XMM11

  (43) 0x4076ce KXNORW	%K0,%K0,%K1

  (43) 0x4076d2 VGATHERDPS	(%R11,%YMM28,4),%YMM11{%K1}

  (43) 0x4076d9 VCVTPS2PD	%YMM27,%ZMM27

  (43) 0x4076df VCVTPS2PD	%YMM29,%ZMM28

  (43) 0x4076e5 VCVTPS2PD	%YMM30,%ZMM29

  (43) 0x4076eb VMOVDQA64	%YMM7,%YMM30

  (43) 0x4076f1 VFMADD231PD	%ZMM28,%ZMM27,%ZMM25

  (43) 0x4076f7 VFMADD231PD	%ZMM29,%ZMM27,%ZMM23

  (43) 0x4076fd VCVTPS2PD	%YMM31,%ZMM28

  (43) 0x407703 VCVTPS2PD	%YMM2,%ZMM2

  (43) 0x407709 VFMADD231PD	%ZMM28,%ZMM27,%ZMM22

  (43) 0x40770f VFMADD231PD	%ZMM2,%ZMM27,%ZMM21

  (43) 0x407715 VCVTPS2PD	%YMM1,%ZMM1

  (43) 0x40771b VCVTPS2PD	%YMM10,%ZMM2

  (43) 0x407721 VFMADD231PD	%ZMM1,%ZMM27,%ZMM20

  (43) 0x407727 VFMADD231PD	%ZMM2,%ZMM27,%ZMM19

  (43) 0x40772d VCVTPS2PD	%YMM11,%ZMM1

  (43) 0x407733 VPADDD	%YMM12,%YMM26,%YMM2

  (43) 0x407739 VXORPS	%XMM10,%XMM10,%XMM10

  (43) 0x40773e KXNORW	%K0,%K0,%K1

  (43) 0x407742 VGATHERDPS	(%R11,%YMM2,4),%YMM10{%K1}

  (43) 0x407749 VFMADD231PD	%ZMM1,%ZMM27,%ZMM18

  (43) 0x40774f VCVTPS2PD	%YMM10,%ZMM1

  (43) 0x407755 VFMADD231PD	%ZMM1,%ZMM27,%ZMM17

  (43) 0x40775b ADD	$0x8,%RSI

  (43) 0x40775f CMP	%R8,%RSI

  (43) 0x407762 JB	407600

0x407768 VEXTRACTF64X4	$0x1,%ZMM25,%YMM1

0x40776f VADDPD	%ZMM1,%ZMM25,%ZMM1

0x407775 VMOVAPD	%XMM1,%XMM2

0x407779 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x40777f VADDPD	%XMM1,%XMM2,%XMM1

0x407783 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x407788 VADDSD	%XMM2,%XMM1,%XMM24

0x40778e VEXTRACTF64X4	$0x1,%ZMM23,%YMM1

0x407795 VADDPD	%ZMM1,%ZMM23,%ZMM1

0x40779b VMOVAPD	%XMM1,%XMM2

0x40779f VEXTRACTF128	$0x1,%YMM1,%XMM1

0x4077a5 VADDPD	%XMM1,%XMM2,%XMM1

0x4077a9 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x4077ae VADDSD	%XMM2,%XMM1,%XMM23

0x4077b4 VEXTRACTF64X4	$0x1,%ZMM22,%YMM1

0x4077bb VADDPD	%ZMM1,%ZMM22,%ZMM1

0x4077c1 VMOVAPD	%XMM1,%XMM2

0x4077c5 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x4077cb VADDPD	%XMM1,%XMM2,%XMM1

0x4077cf VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x4077d4 VADDSD	%XMM2,%XMM1,%XMM22

0x4077da VEXTRACTF64X4	$0x1,%ZMM21,%YMM1

0x4077e1 VADDPD	%ZMM1,%ZMM21,%ZMM1

0x4077e7 VMOVAPD	%XMM1,%XMM2

0x4077eb VEXTRACTF128	$0x1,%YMM1,%XMM1

0x4077f1 VADDPD	%XMM1,%XMM2,%XMM1

0x4077f5 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x4077fa VADDSD	%XMM2,%XMM1,%XMM21

0x407800 VEXTRACTF64X4	$0x1,%ZMM20,%YMM1

0x407807 VADDPD	%ZMM1,%ZMM20,%ZMM1

0x40780d VMOVAPD	%XMM1,%XMM2

0x407811 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x407817 VADDPD	%XMM1,%XMM2,%XMM1

0x40781b VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x407820 VADDSD	%XMM2,%XMM1,%XMM20

0x407826 VEXTRACTF64X4	$0x1,%ZMM19,%YMM1

0x40782d VADDPD	%ZMM1,%ZMM19,%ZMM1

0x407833 VMOVAPD	%XMM1,%XMM2

0x407837 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x40783d VADDPD	%XMM1,%XMM2,%XMM1

0x407841 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x407846 VADDSD	%XMM2,%XMM1,%XMM19

0x40784c VEXTRACTF64X4	$0x1,%ZMM18,%YMM1

0x407853 VADDPD	%ZMM1,%ZMM18,%ZMM1

0x407859 VMOVAPD	%XMM1,%XMM2

0x40785d VEXTRACTF128	$0x1,%YMM1,%XMM1

0x407863 VADDPD	%XMM1,%XMM2,%XMM1

0x407867 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x40786c VADDSD	%XMM2,%XMM1,%XMM18

0x407872 VEXTRACTF64X4	$0x1,%ZMM17,%YMM1

0x407879 VADDPD	%ZMM1,%ZMM17,%ZMM1

0x40787f VMOVAPD	%XMM1,%XMM2

0x407883 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x407889 VADDPD	%XMM1,%XMM2,%XMM1

0x40788d VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x407892 VADDSD	%XMM2,%XMM1,%XMM17

0x407898 CMP	%R8D,%R15D

0x40789b VPMOVSXBD	0x8bd4(%RIP),%YMM6

0x4078a4 JE	4074c0

0x4078aa MOV	%RDX,0x1c0(%RSP)

0x4078b2 VPUNPCKLQDQ	%XMM17,%XMM18,%XMM1

0x4078b8 VPUNPCKLQDQ	%XMM19,%XMM20,%XMM2

0x4078be VINSERTF128	$0x1,%XMM1,%YMM2,%YMM1

0x4078c4 VPUNPCKLQDQ	%XMM21,%XMM22,%XMM2

0x4078ca VPUNPCKLQDQ	%XMM23,%XMM24,%XMM10

0x4078d0 VINSERTF128	$0x1,%XMM2,%YMM10,%YMM2

0x4078d6 VINSERTF64X4	$0x1,%YMM1,%ZMM2,%ZMM24

0x4078dd MOV	%R8,%RSI

0x4078e0 VMOVSS	0x58(%RSP),%XMM25

0x4078e8 VPMOVSXBD	0x8b8f(%RIP),%YMM7

0x4078f1 JMP	407910

0x407900 MOV	%RDX,0x1c0(%RSP)

0x407908 VPXORD	%XMM24,%XMM24,%XMM24

0x40790e XOR	%ESI,%ESI

0x407910 MOV	0x70(%RSP),%RDX

0x407915 MOV	%EDX,%EBX

0x407917 IMUL	%ESI,%EBX

0x40791a ADD	%R9D,%EBX

0x40791d MOV	%RDX,%R9

0x407920 MOV	0xc0(%RSP),%R15

0x407928 MOV	0x88(%RSP),%RDX

  (37) 0x407930 LEA	(%RCX,%RSI,1),%R14D

  (37) 0x407934 VMOVSS	(%R15,%R14,4),%XMM1

  (37) 0x40793a VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (37) 0x40793e LEA	0x5(%RBX),%R14D

  (37) 0x407942 VPBROADCASTD	%EBX,%XMM2

  (37) 0x407948 VPADDD	%YMM6,%YMM2,%YMM10

  (37) 0x40794c VPERMT2D	%YMM2,%YMM7,%YMM10

  (37) 0x407952 VPBROADCASTD	%R14D,%YMM11

  (37) 0x407958 VPBLENDD	$0x20,%YMM11,%YMM10,%YMM10

  (37) 0x40795e VPADDD	%YMM2,%YMM8,%YMM2

  (37) 0x407962 VPERMT2Q	%YMM2,%YMM9,%YMM10

  (37) 0x407968 VPSUBD	%YMM4,%YMM10,%YMM2

  (37) 0x40796c VPXOR	%XMM10,%XMM10,%XMM10

  (37) 0x407971 KXNORW	%K0,%K0,%K1

  (37) 0x407975 VGATHERDPS	(%R11,%YMM2,4),%YMM10{%K1}

  (37) 0x40797c VCVTPS2PD	%YMM10,%ZMM2

  (37) 0x407982 VBROADCASTSD	%XMM1,%ZMM1

  (37) 0x407988 VFMADD231PD	%ZMM1,%ZMM2,%ZMM24

  (37) 0x40798e INC	%RSI

  (37) 0x407991 ADD	%R9D,%EBX

  (37) 0x407994 CMP	%RSI,%RDX

  (37) 0x407997 JNE	407930

0x407999 VEXTRACTF32X4	$0x3,%ZMM24,%XMM18

0x4079a0 VSHUFPD	$0x1,%XMM18,%XMM18,%XMM17

0x4079a7 VEXTRACTF32X4	$0x2,%ZMM24,%XMM20

0x4079ae VSHUFPD	$0x1,%XMM20,%XMM20,%XMM19

0x4079b5 VMOVAPD	%YMM24,%YMM1

0x4079bb VEXTRACTF32X4	$0x1,%YMM24,%XMM22

0x4079c2 VSHUFPD	$0x1,%XMM22,%XMM22,%XMM21

0x4079c9 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM23

0x4079d0 MOV	0x98(%RSP),%R14

0x4079d8 MOV	%RDX,%R15

0x4079db MOV	0x1c0(%RSP),%RDX

0x4079e3 JMP	4074d1

/home/eoseret/llm-attention/attention.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.18
CQA speedup if fully vectorized	3.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.83
CQA cycles if no scalar integer	26.17
CQA cycles if FP arith vectorized	23.67
CQA cycles if fully vectorized	8.30
Front-end cycles	19.50
P0 cycles	18.17
P1 cycles	27.83
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	4.83
P5 cycles	27.67
P6 cycles	4.53
P7 cycles	4.83
P8 cycles	4.83
P9 cycles	4.83
P10 cycles	4.47
P11 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	107.67
Nb uops	117.00
Nb loads	9.00
Nb stores	9.67
Nb stack references	7.00
FLOP/cycle	2.40
Nb FLOP add-sub	58.67
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.87
Bytes prefetched	0.00
Bytes loaded	66.67
Bytes stored	45.33
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.67
Stride indirect	2.00
Vectorization ratio all	47.47
Vectorization ratio load	22.86
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	65.28
Vector-efficiency ratio all	22.10
Vector-efficiency ratio load	11.07
Vector-efficiency ratio store	7.31
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.40

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	7.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P1, P5,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	1.88
Front-end cycles	12.00
P0 cycles	13.00
P1 cycles	13.50
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	5.00
P5 cycles	13.50
P6 cycles	4.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	4.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	72.00
Nb loads	8.00
Nb stores	10.00
Nb stack references	8.00
FLOP/cycle	0.59
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.30
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	48.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	22.50
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	45.00
Vector-efficiency ratio all	13.44
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	7.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.38

Metric	Value
CQA speedup if no scalar integer	1.04
CQA speedup if FP arith vectorized	1.17
CQA speedup if fully vectorized	3.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P1, P5,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	38.50
CQA cycles if no scalar integer	37.00
CQA cycles if FP arith vectorized	33.00
CQA cycles if fully vectorized	12.74
Front-end cycles	25.67
P0 cycles	21.00
P1 cycles	38.50
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	5.00
P5 cycles	38.50
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	144.00
Nb uops	154.00
Nb loads	12.00
Nb stores	10.00
Nb stack references	9.00
FLOP/cycle	2.49
Nb FLOP add-sub	88.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.53
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	48.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	3.00
Vectorization ratio all	59.48
Vectorization ratio load	28.57
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	73.91
Vector-efficiency ratio all	25.97
Vector-efficiency ratio load	10.71
Vector-efficiency ratio store	7.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.09

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.17
CQA speedup if fully vectorized	3.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P1,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	31.50
CQA cycles if no scalar integer	29.50
CQA cycles if FP arith vectorized	27.00
CQA cycles if fully vectorized	10.29
Front-end cycles	20.83
P0 cycles	20.50
P1 cycles	31.50
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	4.50
P5 cycles	31.00
P6 cycles	4.60
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	4.40
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	115.00
Nb uops	125.00
Nb loads	7.00
Nb stores	9.00
Nb stack references	4.00
FLOP/cycle	3.05
Nb FLOP add-sub	88.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.79
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	40.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	60.42
Vectorization ratio load	40.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	76.92
Vector-efficiency ratio all	26.89
Vector-efficiency ratio load	10.00
Vector-efficiency ratio store	6.94
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.72

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:27,30-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 27.83 to 8.30 cycles (3.35x speedup).

Details

47% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

22% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
65% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 0 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 5 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 66.666666666667 FP arithmetical operations:

58.67: addition or subtraction
8: multiply

The binary loop is loading 66 bytes (16 single precision FP elements). The binary loop is storing 45 bytes (11 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.60 FP operations per loaded or stored byte.

General properties

nb instructions	107.67
nb uops	117
loop length	602
used x86 registers	9.33
used mmx registers	0
used xmm registers	11
used ymm registers	4
used zmm registers	7
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	19.50 cycles
front end	19.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.17	27.83	3.00	3.00	4.83	27.67	4.53	4.83	4.83	4.83	4.47	3.00
cycles	18.17	27.83	3.00	3.00	4.83	27.67	4.53	4.83	4.83	4.83	4.47	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	19.50
Dispatch	27.83
Data deps.	0.00
Overall L1	27.83

Vectorization ratios

INT

all	22%
load	27%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	51%
load	0%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	73%

INT+FP

all	47%
load	22%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	65%

Vector efficiency ratios

INT

all	12%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	23%
load	6%
store	6%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	22%
load	11%
store	7%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.83 cycles. At this rate:

1% of peak load performance is reached (2.85 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.02 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 12.00 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.50 to 1.87 cycles (7.20x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: multiply

The binary loop is loading 64 bytes (16 single precision FP elements). The binary loop is storing 48 bytes (12 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	64
nb uops	72
loop length	355
used x86 registers	10
used mmx registers	0
used xmm registers	10
used ymm registers	2
used zmm registers	1
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.00	13.50	2.67	2.67	5.00	13.50	4.00	5.00	5.00	5.00	4.00	2.67
cycles	13.00	13.50	2.67	2.67	5.00	13.50	4.00	5.00	5.00	5.00	4.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	12.00
Dispatch	13.50
Data deps.	0.00
Overall L1	13.50

Vectorization ratios

INT

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	22%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	13%
load	12%
store	7%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

2% of peak load performance is reached (4.74 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.56 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4075a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM24,%XMM24,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA (%RAX,%RDI,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x90(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM23,%XMM23,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x1(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM22,%XMM22,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x2(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM21,%XMM21,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x3(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM20,%XMM20,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x4(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM19,%XMM19,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x5(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM18,%XMM18,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x6(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM17,%XMM17,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x7(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x30(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP 0x38(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4072a6 <main+0x2926>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RDX,8),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 407900 <main+0x2f80>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPXORD %XMM24,%XMM24,%XMM24	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R9D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xc0(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VEXTRACTF32X4 $0x3,%ZMM24,%XMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM18,%XMM18,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VEXTRACTF32X4 $0x2,%ZMM24,%XMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM20,%XMM20,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM24,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM24,%XMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM22,%XMM22,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV 0x98(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x1c0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4074d1 <main+0x2b51>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 38.50 to 12.74 cycles (3.02x speedup).

Details

59% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 38.50 to 25.67 cycles (1.50x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:30
- /home/eoseret/llm-attention/attention.cpp:30

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 10 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VINSERTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:30
- /home/eoseret/llm-attention/attention.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:30
- /home/eoseret/llm-attention/attention.cpp:30

Workaround

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

88: addition or subtraction
8: multiply

The binary loop is loading 88 bytes (22 single precision FP elements). The binary loop is storing 48 bytes (12 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.71 FP operations per loaded or stored byte.

General properties

nb instructions	144
nb uops	154
loop length	809
used x86 registers	10
used mmx registers	0
used xmm registers	12
used ymm registers	6
used zmm registers	11
nb stack references	9
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.67 cycles
front end	25.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	21.00	38.50	4.00	4.00	5.00	38.50	5.00	5.00	5.00	5.00	5.00	4.00
cycles	21.00	38.50	4.00	4.00	5.00	38.50	5.00	5.00	5.00	5.00	5.00	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	25.67
Dispatch	38.50
Data deps.	0.00
Overall L1	38.50

Vectorization ratios

INT

all	17%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	66%
load	0%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	86%

INT+FP

all	59%
load	28%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	73%

Vector efficiency ratios

INT

all	12%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	28%
load	6%
store	6%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	25%
load	10%
store	7%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 38.50 cycles. At this rate:

1% of peak load performance is reached (2.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4075a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM24,%XMM24,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA (%RAX,%RDI,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x90(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM23,%XMM23,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x1(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM22,%XMM22,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x2(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM21,%XMM21,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x3(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM20,%XMM20,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x4(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM19,%XMM19,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x5(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM18,%XMM18,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x6(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM17,%XMM17,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x7(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x30(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP 0x38(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4072a6 <main+0x2926>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RDX,8),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 407900 <main+0x2f80>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %EDI,%YMM24	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPXORD %XMM22,%XMM22,%XMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VXORPS %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTD 0x8e0e(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF64X4 $0x1,%ZMM25,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM25,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM23,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM23,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM22,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM22,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM21,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM21,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM20,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM20,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM19,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM18,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM17,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM17,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %R8D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VPMOVSXBD 0x8bd4(%RIP),%YMM6	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
JE 4074c0 <main+0x2b40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM17,%XMM18,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM19,%XMM20,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM1,%YMM2,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKLQDQ %XMM21,%XMM22,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM23,%XMM24,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM2,%YMM10,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VINSERTF64X4 $0x1,%YMM1,%ZMM2,%ZMM24	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS 0x58(%RSP),%XMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBD 0x8b8f(%RIP),%YMM7	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
JMP 407910 <main+0x2f90>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R9D,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xc0(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VEXTRACTF32X4 $0x3,%ZMM24,%XMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM18,%XMM18,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VEXTRACTF32X4 $0x2,%ZMM24,%XMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM20,%XMM20,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM24,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM24,%XMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM22,%XMM22,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
MOV 0x98(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x1c0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4074d1 <main+0x2b51>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.50 to 29.50 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 31.50 to 10.29 cycles (3.06x speedup).

Details

60% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
76% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:30

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:30

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

88: addition or subtraction
8: multiply

The binary loop is loading 48 bytes (12 single precision FP elements). The binary loop is storing 40 bytes (10 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.09 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	125
loop length	642
used x86 registers	8
used mmx registers	0
used xmm registers	11
used ymm registers	4
used zmm registers	9
nb stack references	4
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.83 cycles
front end	20.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	20.50	31.50	2.33	2.33	4.50	31.00	4.60	4.50	4.50	4.50	4.40	2.33
cycles	20.50	31.50	2.33	2.33	4.50	31.00	4.60	4.50	4.50	4.50	4.40	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	20.83
Dispatch	31.50
Data deps.	0.00
Overall L1	31.50

Vectorization ratios

INT

all	37%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	62%
load	0%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	82%

INT+FP

all	60%
load	40%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	76%

Vector efficiency ratios

INT

all	12%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	28%
load	6%
store	6%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	26%
load	10%
store	6%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.50 cycles. At this rate:

0% of peak load performance is reached (1.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4075a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSS 0x58(%RSP),%XMM25	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBD 0x8faf(%RIP),%YMM7	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VCVTSD2SS %XMM24,%XMM24,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA (%RAX,%RDI,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x90(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM23,%XMM23,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x1(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM22,%XMM22,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x2(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM21,%XMM21,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x3(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM20,%XMM20,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x4(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM19,%XMM19,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x5(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM18,%XMM18,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x6(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM17,%XMM17,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM25,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x7(%RAX,%RDI,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%R9,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x30(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP 0x38(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4072a6 <main+0x2926>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RDX,8),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 407900 <main+0x2f80>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %EDI,%YMM24	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPXORD %XMM22,%XMM22,%XMM22	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VXORPS %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM25,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTD 0x8e0e(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF64X4 $0x1,%ZMM25,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM25,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM24	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM23,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM23,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM22,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM22,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM21,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM21,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM20,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM20,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM19,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM18,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM17,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM17,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %R8D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPMOVSXBD 0x8bd4(%RIP),%YMM6	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
JE 4074c0 <main+0x2b40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

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ASM code

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FMA

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Complex instructions

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Slow data structures access

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Vector unaligned load/store instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks