OV - attention-avx512 - Loop 33

	Loop Id: 33	Module: attention-avx512	Source: attention.cpp:43-284 [...]	Coverage: 0.84%

0x407bc0 MOV	0xf8(%RSP),%RAX

0x407bc8 MOV	0x30(%RSP),%RCX

0x407bcd VMOVSS	%XMM19,(%RAX,%RCX,4)

0x407bd4 MOV	0x108(%RSP),%RAX

0x407bdc MOV	0x48(%RSP),%RDI

0x407be1 ADD	%RAX,%RDI

0x407be4 MOV	0x58(%RSP),%RDX

0x407be9 INC	%RDX

0x407bec ADD	%RAX,%RSI

0x407bef MOV	%RSI,0x38(%RSP)

0x407bf4 MOV	0x1c0(%RSP),%RSI

0x407bfc ADD	%RAX,%RSI

0x407bff CMP	0x68(%RSP),%RCX

0x407c04 MOV	%RBX,%R8

0x407c07 MOV	0x80(%RSP),%RAX

0x407c0f JE	407b40

0x407c15 LEA	0x1(%R8),%RBX

0x407c19 VMOVAPS	%XMM21,%XMM16

0x407c1f CMP	$0x8,%RBX

0x407c23 JB	407c74

0x407c25 MOV	%RDX,%RAX

0x407c28 SHR	$0x3,%RAX

0x407c2c MOV	%RDI,%RCX

0x407c2f VMOVAPS	%XMM21,%XMM16

0x407c35 NOPW	%CS:(%RAX,%RAX,1)

  (36) 0x407c40 VMAXSS	-0x1c(%RCX),%XMM16,%XMM0

  (36) 0x407c47 VMAXSS	-0x18(%RCX),%XMM0,%XMM0

  (36) 0x407c4c VMAXSS	-0x14(%RCX),%XMM0,%XMM0

  (36) 0x407c51 VMAXSS	-0x10(%RCX),%XMM0,%XMM0

  (36) 0x407c56 VMAXSS	-0xc(%RCX),%XMM0,%XMM0

  (36) 0x407c5b VMAXSS	-0x8(%RCX),%XMM0,%XMM0

  (36) 0x407c60 VMAXSS	-0x4(%RCX),%XMM0,%XMM0

  (36) 0x407c65 VMAXSS	(%RCX),%XMM0,%XMM16

  (36) 0x407c6b ADD	$0x20,%RCX

  (36) 0x407c6f DEC	%RAX

  (36) 0x407c72 JNE	407c40

0x407c74 MOV	%RBX,%RAX

0x407c77 AND	$-0x8,%RAX

0x407c7b CMP	%RBX,%RAX

0x407c7e MOV	%RSI,0x1c0(%RSP)

0x407c86 JNE	407cc0

0x407c88 MOV	0x38(%RSP),%RSI

0x407c8d JMP	407cdf

0x407cc0 MOV	0x38(%RSP),%RSI

0x407cc5 NOPW	%CS:(%RAX,%RAX,1)

  (31) 0x407cd0 VMAXSS	(%RSI,%RAX,4),%XMM16,%XMM16

  (31) 0x407cd7 INC	%RAX

  (31) 0x407cda CMP	%RAX,%RDX

  (31) 0x407cdd JNE	407cd0

0x407cdf MOV	%RDI,0x48(%RSP)

0x407ce4 MOV	%RDX,0x58(%RSP)

0x407ce9 MOV	%RBX,%RAX

0x407cec AND	$-0x10,%RAX

0x407cf0 VPBROADCASTQ	%RAX,%ZMM17

0x407cf6 MOV	%R8,0x30(%RSP)

0x407cfb MOV	%RAX,0x180(%RSP)

0x407d03 MOV	%RBX,0x28(%RSP)

0x407d08 JE	407dc0

0x407d0e VPBROADCASTQ	%RBX,%ZMM19

0x407d14 LEA	-0x1(%RAX),%RBX

0x407d18 MOV	0x60(%RSP),%RDI

0x407d1d IMUL	%R8,%RDI

0x407d21 VBROADCASTSS	%XMM16,%ZMM20

0x407d27 VXORPS	%XMM18,%XMM18,%XMM18

0x407d2d XOR	%R14D,%R14D

0x407d30 MOV	$0x4099b0,%R15

0x407d37 NOPW	(%RAX,%RAX,1)

  (35) 0x407d40 VMOVUPS	(%RSI,%R14,4),%ZMM0

  (35) 0x407d47 VSUBPS	%ZMM20,%ZMM0,%ZMM0

  (35) 0x407d4d CALL	%R15

  (35) 0x407d50 VADDPS	%ZMM18,%ZMM0,%ZMM18

  (35) 0x407d56 ADD	$0x10,%R14

  (35) 0x407d5a CMP	%RBX,%R14

  (35) 0x407d5d JLE	407d40

0x407d5f VPCMPEQQ	%ZMM17,%ZMM19,%K0

0x407d65 KMOVD	%K0,%ECX

0x407d69 MOV	0x180(%RSP),%RDX

0x407d71 MOV	%RDX,%RAX

0x407d74 TEST	$0x1,%CL

0x407d77 MOV	0x98(%RSP),%R14

0x407d7f MOV	0x88(%RSP),%R15

0x407d87 MOV	0x28(%RSP),%RBX

0x407d8c JE	407ddd

0x407d8e JMP	407e39

0x407dc0 VPBROADCASTQ	%RBX,%ZMM19

0x407dc6 MOV	0x60(%RSP),%RDI

0x407dcb IMUL	%R8,%RDI

0x407dcf VBROADCASTSS	%XMM16,%ZMM20

0x407dd5 VXORPS	%XMM18,%XMM18,%XMM18

0x407ddb XOR	%EAX,%EAX

0x407ddd VPBROADCASTQ	%RAX,%ZMM0

0x407de3 VPSUBQ	%ZMM0,%ZMM19,%ZMM1

0x407de9 VPSUBQ	%ZMM0,%ZMM19,%ZMM0

0x407def VPCMPNLEUQ	%ZMM22,%ZMM0,%K0

0x407df6 VPCMPNLEUQ	%ZMM23,%ZMM1,%K1

0x407dfd KUNPCKBW	%K0,%K1,%K1

0x407e01 KMOVW	%K1,0x50(%RSP)

0x407e07 ADD	%RAX,%RDI

0x407e0a MOV	0x90(%RSP),%RAX

0x407e12 VMOVUPS	(%RAX,%RDI,4),%ZMM0{%K1}{z}

0x407e19 VSUBPS	%ZMM20,%ZMM0,%ZMM1

0x407e1f CALL	409a50 <__svml_expf16_mask_z0>

0x407e25 MOV	0x180(%RSP),%RDX

0x407e2d KMOVW	0x50(%RSP),%K1

0x407e33 VADDPS	%ZMM0,%ZMM18,%ZMM18{%K1}

0x407e39 VEXTRACTF64X4	$0x1,%ZMM18,%YMM0

0x407e40 VADDPS	%ZMM0,%ZMM18,%ZMM0

0x407e46 VMOVAPS	%XMM0,%XMM1

0x407e4a VEXTRACTF128	$0x1,%YMM0,%XMM0

0x407e50 VADDPS	%XMM0,%XMM1,%XMM0

0x407e54 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x407e59 VADDPS	%XMM1,%XMM0,%XMM0

0x407e5d VMOVSHDUP	%XMM0,%XMM1

0x407e61 VADDSS	%XMM1,%XMM0,%XMM19

0x407e67 VDIVSS	%XMM19,%XMM24,%XMM1

0x407e6d TEST	%RDX,%RDX

0x407e70 JE	407f40

0x407e76 LEA	-0x1(%RDX),%RBX

0x407e7a MOV	0x60(%RSP),%RAX

0x407e7f IMUL	0x30(%RSP),%RAX

0x407e85 MOV	%RAX,0x50(%RSP)

0x407e8a VBROADCASTSS	%XMM16,%ZMM18

0x407e90 VBROADCASTSS	%XMM1,%ZMM16

0x407e96 XOR	%R14D,%R14D

0x407e99 MOV	$0x4099b0,%R15

0x407ea0 MOV	%RSI,%RDI

0x407ea3 MOV	0x1c0(%RSP),%RSI

0x407eab NOPL	(%RAX,%RAX,1)

  (34) 0x407eb0 VMOVUPS	(%RDI,%R14,4),%ZMM0

  (34) 0x407eb7 VSUBPS	%ZMM18,%ZMM0,%ZMM0

  (34) 0x407ebd CALL	%R15

  (34) 0x407ec0 VMULPS	%ZMM16,%ZMM0,%ZMM0

  (34) 0x407ec6 VMOVUPS	%ZMM0,(%RSI,%R14,4)

  (34) 0x407ecd ADD	$0x10,%R14

  (34) 0x407ed1 CMP	%RBX,%R14

  (34) 0x407ed4 JLE	407eb0

0x407ed6 MOV	0x28(%RSP),%RBX

0x407edb VPBROADCASTQ	%RBX,%ZMM0

0x407ee1 VPCMPEQQ	%ZMM17,%ZMM0,%K0

0x407ee7 KMOVD	%K0,%EAX

0x407eeb TEST	$0x1,%AL

0x407eed MOV	0x98(%RSP),%R14

0x407ef5 MOV	0x88(%RSP),%R15

0x407efd MOV	%RDI,%RSI

0x407f00 MOV	0x180(%RSP),%RAX

0x407f08 MOV	0x50(%RSP),%RDI

0x407f0d JE	407f5f

0x407f0f CMP	0xb8(%RSP),%RBX

0x407f17 JAE	407bc0

0x407f1d JMP	407fd6

0x407f40 VPBROADCASTQ	%RBX,%ZMM0

0x407f46 MOV	0x60(%RSP),%RDI

0x407f4b IMUL	0x30(%RSP),%RDI

0x407f51 VBROADCASTSS	%XMM16,%ZMM18

0x407f57 VBROADCASTSS	%XMM1,%ZMM16

0x407f5d XOR	%EAX,%EAX

0x407f5f VPBROADCASTQ	%RAX,%ZMM1

0x407f65 VPSUBQ	%ZMM1,%ZMM0,%ZMM2

0x407f6b VPSUBQ	%ZMM1,%ZMM0,%ZMM0

0x407f71 VPCMPNLEUQ	%ZMM22,%ZMM0,%K0

0x407f78 VPCMPNLEUQ	%ZMM23,%ZMM2,%K1

0x407f7f KUNPCKBW	%K0,%K1,%K1

0x407f83 KMOVW	%K1,0x180(%RSP)

0x407f8c ADD	%RAX,%RDI

0x407f8f MOV	0x90(%RSP),%RAX

0x407f97 VMOVUPS	(%RAX,%RDI,4),%ZMM0{%K1}{z}

0x407f9e VSUBPS	%ZMM18,%ZMM0,%ZMM1

0x407fa4 CALL	409a50 <__svml_expf16_mask_z0>

0x407faa VMULPS	%ZMM16,%ZMM0,%ZMM0

0x407fb0 MOV	0x80(%RSP),%RAX

0x407fb8 KMOVW	0x180(%RSP),%K1

0x407fc1 VMOVUPS	%ZMM0,(%RAX,%RDI,4){%K1}

0x407fc8 CMP	0xb8(%RSP),%RBX

0x407fd0 JAE	407bc0

0x407fd6 MOV	0xe8(%RSP),%RDI

0x407fde MOV	0x30(%RSP),%RAX

0x407fe3 IMUL	%RAX,%RDI

0x407fe7 ADD	$0x4,%RDI

0x407feb MOV	0xf0(%RSP),%RDX

0x407ff3 SUB	%RAX,%RDX

0x407ff6 MOV	$0x3fffffffc,%RAX

0x408000 AND	%RAX,%RDI

0x408003 ADD	0x80(%RSP),%RDI

0x40800b SAL	$0x2,%RDX

0x40800f AND	%RAX,%RDX

0x408012 ADD	$0x4,%RDX

0x408016 XOR	%ESI,%ESI

0x408018 VMOVSS	%XMM19,0x180(%RSP)

0x408020 VZEROUPPER

0x408023 CALL	40a9c0 <_intel_fast_memset>

0x408028 VMOVSS	0x180(%RSP),%XMM19

0x408030 MOV	0x38(%RSP),%RSI

0x408035 VMOVSS	0x83b5(%RIP),%XMM24

0x40803f VPMOVSXBQ	0x83df(%RIP),%ZMM23

0x408049 VPMOVSXBQ	0x83cd(%RIP),%ZMM22

0x408053 VMOVSS	0x8393(%RIP),%XMM21

0x40805d JMP	407bc0

/home/eoseret/llm-attention/attention.cpp: 43 - 284

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

[...]

98:    if (argc < 4) {

[...]

284:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.52
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-61,attention.cpp:98-98,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.83
CQA cycles if no scalar integer	19.00
CQA cycles if FP arith vectorized	28.25
CQA cycles if fully vectorized	20.56
Front-end cycles	28.83
P0 cycles	13.70
P1 cycles	13.80
P2 cycles	15.33
P3 cycles	15.33
P4 cycles	8.00
P5 cycles	23.00
P6 cycles	13.70
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	13.80
P11 cycles	15.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	167.00
Nb uops	173.00
Nb loads	46.00
Nb stores	13.00
Nb stack references	19.00
FLOP/cycle	3.12
Nb FLOP add-sub	73.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.67
Bytes prefetched	0.00
Bytes loaded	456.00
Bytes stored	140.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	37.65
Vectorization ratio load	19.05
Vectorization ratio store	9.09
Vectorization ratio mul	100.00
Vectorization ratio add_sub	76.92
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	39.02
Vector-efficiency ratio all	31.62
Vector-efficiency ratio load	19.94
Vector-efficiency ratio store	19.32
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	67.79
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	26.98

Metric	Value
CQA speedup if no scalar integer	1.52
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-61,attention.cpp:98-98,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.83
CQA cycles if no scalar integer	19.00
CQA cycles if FP arith vectorized	28.25
CQA cycles if fully vectorized	20.56
Front-end cycles	28.83
P0 cycles	13.70
P1 cycles	13.80
P2 cycles	15.33
P3 cycles	15.33
P4 cycles	8.00
P5 cycles	23.00
P6 cycles	13.70
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	13.80
P11 cycles	15.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	167.00
Nb uops	173.00
Nb loads	46.00
Nb stores	13.00
Nb stack references	19.00
FLOP/cycle	3.12
Nb FLOP add-sub	73.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.67
Bytes prefetched	0.00
Bytes loaded	456.00
Bytes stored	140.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	37.65
Vectorization ratio load	19.05
Vectorization ratio store	9.09
Vectorization ratio mul	100.00
Vectorization ratio add_sub	76.92
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	39.02
Vector-efficiency ratio all	31.62
Vector-efficiency ratio load	19.94
Vector-efficiency ratio store	19.32
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	67.79
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	26.98

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,98,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52-61,98,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 72 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.83 to 19.00 cycles (1.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 31% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 28.83 to 20.56 cycles (1.40x speedup).

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

19% of SSE/AVX loads are used in vector version.
9% of SSE/AVX stores are used in vector version.
76% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_expf16_mask_z0: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
VPMOVSXBQ: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
- /home/eoseret/llm-attention/attention.cpp:59
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
- /home/eoseret/llm-attention/attention.cpp:59

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 5 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

73: addition or subtraction
16: multiply
1: divide

The binary loop is loading 456 bytes (114 single precision FP elements). The binary loop is storing 140 bytes (35 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	167
nb uops	173
loop length	926
used x86 registers	10
used mmx registers	0
used xmm registers	7
used ymm registers	1
used zmm registers	10
nb stack references	19
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.83 cycles
front end	28.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.70	13.80	15.33	15.33	8.00	23.00	13.70	8.00	8.00	8.00	13.80	15.33
cycles	13.70	13.80	15.33	15.33	8.00	23.00	13.70	8.00	8.00	8.00	13.80	15.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	28.83
Dispatch	23.00
DIV/SQRT	3.00
Overall L1	28.83

Vectorization ratios

INT

all	24%
load	12%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	59%
load	40%
store	33%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	60%

INT+FP

all	37%
load	19%
store	9%
mul	100%
add-sub	76%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	39%

Vector efficiency ratios

INT

all	28%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	70%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	36%
load	43%
store	37%
mul	100%
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

INT+FP

all	31%
load	19%
store	19%
mul	100%
add-sub	67%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	26%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.83 cycles. At this rate:

8% of peak load performance is reached (15.82 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 28.83 to 23.00 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 407c15

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xf8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM19,(%RAX,%RCX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x108(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x1c0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP 0x68(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x80(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 407b40 <main+0x31c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMP $0x8,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 407c74 <main+0x32f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JNE 407cc0 <main+0x3340>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 407cdf <main+0x335f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %RAX,%ZMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 407dc0 <main+0x3440>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTQ %RBX,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA -0x1(%RAX),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x4099b0,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %ZMM17,%ZMM19,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x180(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x98(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 407ddd <main+0x345d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 407e39 <main+0x34b9>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPBROADCASTQ %RBX,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM0,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM1,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x90(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RDI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM20,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 409a50 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x180(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW 0x50(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %ZMM0,%ZMM18,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPS %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VDIVSS %XMM19,%XMM24,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 407f40 <main+0x35c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RDX),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x4099b0,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %RBX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %ZMM17,%ZMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x98(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x180(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 407f5f <main+0x35df>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0xb8(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 407bc0 <main+0x3240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 407fd6 <main+0x3656>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPBROADCASTQ %RBX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM2,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x90(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RDI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM18,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 409a50 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMULPS %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x80(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW 0x180(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %ZMM0,(%RAX,%RDI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP 0xb8(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 407bc0 <main+0x3240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xe8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xf0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3fffffffc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD 0x80(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSS %XMM19,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 40a9c0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x180(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x38(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSS 0x83b5(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBQ 0x83df(%RIP),%ZMM23	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBQ 0x83cd(%RIP),%ZMM22	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VMOVSS 0x8393(%RIP),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 407bc0 <main+0x3240>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,98,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52-61,98,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

19% of SSE/AVX loads are used in vector version.
9% of SSE/AVX stores are used in vector version.
76% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

__svml_expf16_mask_z0: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
VPMOVSXBQ: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
- /home/eoseret/llm-attention/attention.cpp:59
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
- /home/eoseret/llm-attention/attention.cpp:59

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

73: addition or subtraction
16: multiply
1: divide

The binary loop is loading 456 bytes (114 single precision FP elements). The binary loop is storing 140 bytes (35 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	167
nb uops	173
loop length	926
used x86 registers	10
used mmx registers	0
used xmm registers	7
used ymm registers	1
used zmm registers	10
nb stack references	19
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.83 cycles
front end	28.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.70	13.80	15.33	15.33	8.00	23.00	13.70	8.00	8.00	8.00	13.80	15.33
cycles	13.70	13.80	15.33	15.33	8.00	23.00	13.70	8.00	8.00	8.00	13.80	15.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	28.83
Dispatch	23.00
DIV/SQRT	3.00
Overall L1	28.83

Vectorization ratios

INT

all	24%
load	12%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	59%
load	40%
store	33%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	60%

INT+FP

all	37%
load	19%
store	9%
mul	100%
add-sub	76%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	39%

Vector efficiency ratios

INT

all	28%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	70%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	36%
load	43%
store	37%
mul	100%
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

INT+FP

all	31%
load	19%
store	19%
mul	100%
add-sub	67%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	26%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.83 cycles. At this rate:

8% of peak load performance is reached (15.82 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 407c15

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xf8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM19,(%RAX,%RCX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x108(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x1c0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP 0x68(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x80(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 407b40 <main+0x31c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMP $0x8,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 407c74 <main+0x32f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JNE 407cc0 <main+0x3340>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 407cdf <main+0x335f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %RAX,%ZMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 407dc0 <main+0x3440>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTQ %RBX,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA -0x1(%RAX),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x4099b0,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %ZMM17,%ZMM19,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x180(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x98(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 407ddd <main+0x345d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 407e39 <main+0x34b9>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPBROADCASTQ %RBX,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM0,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM1,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x90(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RDI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM20,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 409a50 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x180(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW 0x50(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %ZMM0,%ZMM18,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPS %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VDIVSS %XMM19,%XMM24,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 407f40 <main+0x35c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RDX),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x4099b0,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %RBX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %ZMM17,%ZMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x98(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x180(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 407f5f <main+0x35df>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0xb8(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 407bc0 <main+0x3240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 407fd6 <main+0x3656>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPBROADCASTQ %RBX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM2,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x90(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RDI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM18,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 409a50 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMULPS %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
MOV 0x80(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW 0x180(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %ZMM0,(%RAX,%RDI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP 0xb8(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 407bc0 <main+0x3240>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xe8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xf0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3fffffffc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD 0x80(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSS %XMM19,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 40a9c0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x180(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x38(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSS 0x83b5(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBQ 0x83df(%RIP),%ZMM23	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBQ 0x83cd(%RIP),%ZMM22	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VMOVSS 0x8393(%RIP),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 407bc0 <main+0x3240>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code