OV - attention-avx512 - Loop 30

	Loop Id: 30	Module: attention-avx512	Source: attention.cpp:30-31	Coverage: 29.99%

0x408580 VPBROADCASTD	%EDX,%YMM24

0x408586 VPADDD	%YMM2,%YMM24,%YMM24

0x40858c VPMULLD	%YMM24,%YMM26,%YMM24

0x408592 VPADDD	%YMM22,%YMM24,%YMM24

0x408598 VPSUBD	%YMM3,%YMM24,%YMM25

0x40859e VPXORD	%XMM26,%XMM26,%XMM26

0x4085a4 KXNORW	%K0,%K0,%K1

0x4085a8 VGATHERDPS	(%R9,%YMM25,4),%YMM26{%K1}    [1]

0x4085af VPADDD	%YMM0,%YMM24,%YMM25

0x4085b5 VXORPS	%XMM27,%XMM27,%XMM27

0x4085bb KXNORW	%K0,%K0,%K1

0x4085bf VGATHERDPS	(%R9,%YMM25,4),%YMM27{%K1}    [1]

0x4085c6 VPADDD	%YMM9,%YMM24,%YMM25

0x4085cc VXORPS	%XMM28,%XMM28,%XMM28

0x4085d2 KXNORW	%K0,%K0,%K1

0x4085d6 VGATHERDPS	(%R9,%YMM25,4),%YMM28{%K1}    [1]

0x4085dd VPADDD	%YMM10,%YMM24,%YMM25

0x4085e3 VXORPS	%XMM29,%XMM29,%XMM29

0x4085e9 KXNORW	%K0,%K0,%K1

0x4085ed VGATHERDPS	(%R9,%YMM25,4),%YMM29{%K1}    [1]

0x4085f4 VPADDD	%YMM11,%YMM24,%YMM25

0x4085fa VXORPS	%XMM30,%XMM30,%XMM30

0x408600 KXNORW	%K0,%K0,%K1

0x408604 VGATHERDPS	(%R9,%YMM25,4),%YMM30{%K1}    [1]

0x40860b VPADDD	%YMM12,%YMM24,%YMM25

0x408611 VXORPS	%XMM31,%XMM31,%XMM31

0x408617 KXNORW	%K0,%K0,%K1

0x40861b VGATHERDPS	(%R9,%YMM25,4),%YMM31{%K1}    [1]

0x408622 VPADDD	%YMM13,%YMM24,%YMM25

0x408628 VXORPS	%XMM1,%XMM1,%XMM1

0x40862c KXNORW	%K0,%K0,%K1

0x408630 VGATHERDPS	(%R9,%YMM25,4),%YMM1{%K1}    [1]

0x408637 LEA	(%R11,%RDX,1),%EBX

0x40863b VCVTPS2PD	(%R15,%RBX,4),%ZMM25    [3]

0x408642 VCVTPS2PD	%YMM26,%ZMM26

0x408648 VCVTPS2PD	%YMM27,%ZMM27

0x40864e VFMADD231PD	%ZMM26,%ZMM25,%ZMM23

0x408654 VFMADD231PD	%ZMM27,%ZMM25,%ZMM21

0x40865a VCVTPS2PD	%YMM28,%ZMM26

0x408660 VCVTPS2PD	%YMM29,%ZMM27

0x408666 VFMADD231PD	%ZMM26,%ZMM25,%ZMM20

0x40866c VFMADD231PD	%ZMM27,%ZMM25,%ZMM19

0x408672 VCVTPS2PD	%YMM30,%ZMM26

0x408678 VCVTPS2PD	%YMM31,%ZMM27

0x40867e VFMADD231PD	%ZMM26,%ZMM25,%ZMM18

0x408684 VFMADD231PD	%ZMM27,%ZMM25,%ZMM17

0x40868a VCVTPS2PD	%YMM1,%ZMM1

0x408690 VPADDD	%YMM14,%YMM24,%YMM24

0x408696 VXORPD	%XMM26,%XMM26,%XMM26

0x40869c KXNORW	%K0,%K0,%K1

0x4086a0 VGATHERDPS	(%R9,%YMM24,4),%YMM26{%K1}    [1]

0x4086a7 VFMADD231PD	%ZMM1,%ZMM25,%ZMM16

0x4086ad VCVTPS2PD	%YMM26,%ZMM1

0x4086b3 VMOVDQU64	0x120(%RSP),%YMM26    [2]

0x4086bb VFMADD231PD	%ZMM1,%ZMM25,%ZMM15

0x4086c1 ADD	$0x8,%RDX

0x4086c5 CMP	%RDI,%RDX

0x4086c8 JB	408580

/home/eoseret/llm-attention/attention.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P0,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	25.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	25.00
CQA cycles if fully vectorized	16.50
Front-end cycles	16.50
P0 cycles	25.00
P1 cycles	23.67
P2 cycles	22.00
P3 cycles	22.00
P4 cycles	0.00
P5 cycles	23.33
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	22.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	99.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	5.12
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.80
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	97.83
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	96.15
Vector-efficiency ratio all	53.40
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	40.63

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P0,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	25.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	25.00
CQA cycles if fully vectorized	16.50
Front-end cycles	16.50
P0 cycles	25.00
P1 cycles	23.67
P2 cycles	22.00
P3 cycles	22.00
P4 cycles	0.00
P5 cycles	23.33
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	22.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	99.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	5.12
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.80
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	97.83
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	96.15
Vector-efficiency ratio all	53.40
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	40.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 22.00 cycles (1.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is highly vectorized. Only 53% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 25.00 to 16.50 cycles (1.52x speedup).

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.00 to 23.67 cycles (1.06x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.40 FP operations per loaded or stored byte.

General properties

nb instructions	58
nb uops	99
loop length	334
used x86 registers	7
used mmx registers	0
used xmm registers	7
used ymm registers	19
used zmm registers	12
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	25.00	23.67	22.00	22.00	0.00	23.33	1.00	0.00	0.00	0.00	1.00	22.00
cycles	25.00	23.67	22.00	22.00	0.00	23.33	1.00	0.00	0.00	0.00	1.00	22.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	16.50
Dispatch	25.00
Data deps.	4.00
Overall L1	25.00

Vectorization ratios

INT

all	92%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Vector efficiency ratios

INT

all	45%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	57%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

INT+FP

all	53%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.00 cycles. At this rate:

6% of peak load performance is reached (12.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 408580

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTD %EDX,%YMM24	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM2,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM24,%YMM26,%YMM24	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM22,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM3,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXORD %XMM26,%XMM26,%XMM26	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM26{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM0,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM27{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM9,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM28{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM10,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM29{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM11,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM30{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM12,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM31,%XMM31,%XMM31	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM31{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM13,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM1{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
LEA (%R11,%RDX,1),%EBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VCVTPS2PD (%R15,%RBX,4),%ZMM25	2	1	0	0.33	0.33	1	0	0	0.33	7	1	vect (50.0%)
VCVTPS2PD %YMM26,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM27,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM23	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM21	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM28,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM29,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM20	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM19	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM30,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM31,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM18	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM17	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM1,%ZMM1	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VPADDD %YMM14,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM24,4),%YMM26{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VFMADD231PD %ZMM1,%ZMM25,%ZMM16	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM26,%ZMM1	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VMOVDQU64 0x120(%RSP),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %ZMM1,%ZMM25,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 408580 <main+0x3c00>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.40 FP operations per loaded or stored byte.

General properties

nb instructions	58
nb uops	99
loop length	334
used x86 registers	7
used mmx registers	0
used xmm registers	7
used ymm registers	19
used zmm registers	12
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	25.00	23.67	22.00	22.00	0.00	23.33	1.00	0.00	0.00	0.00	1.00	22.00
cycles	25.00	23.67	22.00	22.00	0.00	23.33	1.00	0.00	0.00	0.00	1.00	22.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	16.50
Dispatch	25.00
Data deps.	4.00
Overall L1	25.00

Vectorization ratios

INT

all	92%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	97%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Vector efficiency ratios

INT

all	45%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	57%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

INT+FP

all	53%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.00 cycles. At this rate:

6% of peak load performance is reached (12.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 408580

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTD %EDX,%YMM24	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM2,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM24,%YMM26,%YMM24	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM22,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM3,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXORD %XMM26,%XMM26,%XMM26	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM26{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM0,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM27,%XMM27,%XMM27	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM27{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM9,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM28,%XMM28,%XMM28	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM28{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM10,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM29,%XMM29,%XMM29	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM29{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM11,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM30,%XMM30,%XMM30	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM30{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM12,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM31,%XMM31,%XMM31	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM31{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VPADDD %YMM13,%YMM24,%YMM25	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM25,4),%YMM1{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
LEA (%R11,%RDX,1),%EBX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VCVTPS2PD (%R15,%RBX,4),%ZMM25	2	1	0	0.33	0.33	1	0	0	0.33	7	1	vect (50.0%)
VCVTPS2PD %YMM26,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM27,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM23	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM21	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM28,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM29,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM20	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM19	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM30,%ZMM26	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM31,%ZMM27	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM26,%ZMM25,%ZMM18	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM27,%ZMM25,%ZMM17	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM1,%ZMM1	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VPADDD %YMM14,%YMM24,%YMM24	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VXORPD %XMM26,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R9,%YMM24,4),%YMM26{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VFMADD231PD %ZMM1,%ZMM25,%ZMM16	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VCVTPS2PD %YMM26,%ZMM1	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VMOVDQU64 0x120(%RSP),%YMM26	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD231PD %ZMM1,%ZMM25,%ZMM15	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 408580 <main+0x3c00>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code