OV - attention-avx512 - Loop 29

	Loop Id: 29	Module: attention-avx512	Source: attention.cpp:27-33	Coverage: 0.70%

0x408480 MOV	0x88(%RSP),%R15

0x408488 VCVTSD2SS	%XMM22,%XMM22,%XMM1

0x40848e LEA	(%RAX,%R8,1),%EDX

0x408492 MOV	0x100(%RSP),%RBX

0x40849a VMOVSS	%XMM1,(%RBX,%RDX,4)

0x40849f VCVTSD2SS	%XMM21,%XMM21,%XMM1

0x4084a5 LEA	0x1(%RAX,%R8,1),%EDX

0x4084aa VMOVSS	%XMM1,(%RBX,%RDX,4)

0x4084af VCVTSD2SS	%XMM20,%XMM20,%XMM1

0x4084b5 LEA	0x2(%RAX,%R8,1),%EDX

0x4084ba VMOVSS	%XMM1,(%RBX,%RDX,4)

0x4084bf VCVTSD2SS	%XMM19,%XMM19,%XMM1

0x4084c5 LEA	0x3(%RAX,%R8,1),%EDX

0x4084ca VMOVSS	%XMM1,(%RBX,%RDX,4)

0x4084cf VCVTSD2SS	%XMM18,%XMM18,%XMM1

0x4084d5 LEA	0x4(%RAX,%R8,1),%EDX

0x4084da VMOVSS	%XMM1,(%RBX,%RDX,4)

0x4084df VCVTSD2SS	%XMM17,%XMM17,%XMM1

0x4084e5 LEA	0x5(%RAX,%R8,1),%EDX

0x4084ea VMOVSS	%XMM1,(%RBX,%RDX,4)

0x4084ef VCVTSD2SS	%XMM16,%XMM16,%XMM1

0x4084f5 LEA	0x6(%RAX,%R8,1),%EDX

0x4084fa VMOVSS	%XMM1,(%RBX,%RDX,4)

0x4084ff VCVTSD2SS	%XMM23,%XMM23,%XMM1

0x408505 LEA	0x7(%RAX,%R8,1),%EDX

0x40850a VMOVSS	%XMM1,(%RBX,%RDX,4)

0x40850f ADD	$0x8,%ESI

0x408512 CMP	0x180(%RSP),%RCX

0x40851a LEA	0x1(%RCX),%RCX

0x40851e JE	4082ab

0x408524 LEA	(,%RCX,8),%R8D

0x40852c TEST	%RDI,%RDI

0x40852f JE	408880

0x408535 VPBROADCASTD	%R8D,%YMM22

0x40853b VXORPD	%XMM15,%XMM15,%XMM15

0x408540 VXORPD	%XMM16,%XMM16,%XMM16

0x408546 VXORPD	%XMM17,%XMM17,%XMM17

0x40854c VXORPD	%XMM18,%XMM18,%XMM18

0x408552 VXORPD	%XMM19,%XMM19,%XMM19

0x408558 VXORPD	%XMM20,%XMM20,%XMM20

0x40855e VXORPD	%XMM21,%XMM21,%XMM21

0x408564 VXORPS	%XMM23,%XMM23,%XMM23

0x40856a XOR	%EDX,%EDX

0x40856c MOV	0x80(%RSP),%R15

0x408574 NOPW	%CS:(%RAX,%RAX,1)

  (30) 0x408580 VPBROADCASTD	%EDX,%YMM24

  (30) 0x408586 VPADDD	%YMM2,%YMM24,%YMM24

  (30) 0x40858c VPMULLD	%YMM24,%YMM26,%YMM24

  (30) 0x408592 VPADDD	%YMM22,%YMM24,%YMM24

  (30) 0x408598 VPSUBD	%YMM3,%YMM24,%YMM25

  (30) 0x40859e VPXORD	%XMM26,%XMM26,%XMM26

  (30) 0x4085a4 KXNORW	%K0,%K0,%K1

  (30) 0x4085a8 VGATHERDPS	(%R9,%YMM25,4),%YMM26{%K1}

  (30) 0x4085af VPADDD	%YMM0,%YMM24,%YMM25

  (30) 0x4085b5 VXORPS	%XMM27,%XMM27,%XMM27

  (30) 0x4085bb KXNORW	%K0,%K0,%K1

  (30) 0x4085bf VGATHERDPS	(%R9,%YMM25,4),%YMM27{%K1}

  (30) 0x4085c6 VPADDD	%YMM9,%YMM24,%YMM25

  (30) 0x4085cc VXORPS	%XMM28,%XMM28,%XMM28

  (30) 0x4085d2 KXNORW	%K0,%K0,%K1

  (30) 0x4085d6 VGATHERDPS	(%R9,%YMM25,4),%YMM28{%K1}

  (30) 0x4085dd VPADDD	%YMM10,%YMM24,%YMM25

  (30) 0x4085e3 VXORPS	%XMM29,%XMM29,%XMM29

  (30) 0x4085e9 KXNORW	%K0,%K0,%K1

  (30) 0x4085ed VGATHERDPS	(%R9,%YMM25,4),%YMM29{%K1}

  (30) 0x4085f4 VPADDD	%YMM11,%YMM24,%YMM25

  (30) 0x4085fa VXORPS	%XMM30,%XMM30,%XMM30

  (30) 0x408600 KXNORW	%K0,%K0,%K1

  (30) 0x408604 VGATHERDPS	(%R9,%YMM25,4),%YMM30{%K1}

  (30) 0x40860b VPADDD	%YMM12,%YMM24,%YMM25

  (30) 0x408611 VXORPS	%XMM31,%XMM31,%XMM31

  (30) 0x408617 KXNORW	%K0,%K0,%K1

  (30) 0x40861b VGATHERDPS	(%R9,%YMM25,4),%YMM31{%K1}

  (30) 0x408622 VPADDD	%YMM13,%YMM24,%YMM25

  (30) 0x408628 VXORPS	%XMM1,%XMM1,%XMM1

  (30) 0x40862c KXNORW	%K0,%K0,%K1

  (30) 0x408630 VGATHERDPS	(%R9,%YMM25,4),%YMM1{%K1}

  (30) 0x408637 LEA	(%R11,%RDX,1),%EBX

  (30) 0x40863b VCVTPS2PD	(%R15,%RBX,4),%ZMM25

  (30) 0x408642 VCVTPS2PD	%YMM26,%ZMM26

  (30) 0x408648 VCVTPS2PD	%YMM27,%ZMM27

  (30) 0x40864e VFMADD231PD	%ZMM26,%ZMM25,%ZMM23

  (30) 0x408654 VFMADD231PD	%ZMM27,%ZMM25,%ZMM21

  (30) 0x40865a VCVTPS2PD	%YMM28,%ZMM26

  (30) 0x408660 VCVTPS2PD	%YMM29,%ZMM27

  (30) 0x408666 VFMADD231PD	%ZMM26,%ZMM25,%ZMM20

  (30) 0x40866c VFMADD231PD	%ZMM27,%ZMM25,%ZMM19

  (30) 0x408672 VCVTPS2PD	%YMM30,%ZMM26

  (30) 0x408678 VCVTPS2PD	%YMM31,%ZMM27

  (30) 0x40867e VFMADD231PD	%ZMM26,%ZMM25,%ZMM18

  (30) 0x408684 VFMADD231PD	%ZMM27,%ZMM25,%ZMM17

  (30) 0x40868a VCVTPS2PD	%YMM1,%ZMM1

  (30) 0x408690 VPADDD	%YMM14,%YMM24,%YMM24

  (30) 0x408696 VXORPD	%XMM26,%XMM26,%XMM26

  (30) 0x40869c KXNORW	%K0,%K0,%K1

  (30) 0x4086a0 VGATHERDPS	(%R9,%YMM24,4),%YMM26{%K1}

  (30) 0x4086a7 VFMADD231PD	%ZMM1,%ZMM25,%ZMM16

  (30) 0x4086ad VCVTPS2PD	%YMM26,%ZMM1

  (30) 0x4086b3 VMOVDQU64	0x120(%RSP),%YMM26

  (30) 0x4086bb VFMADD231PD	%ZMM1,%ZMM25,%ZMM15

  (30) 0x4086c1 ADD	$0x8,%RDX

  (30) 0x4086c5 CMP	%RDI,%RDX

  (30) 0x4086c8 JB	408580

0x4086ce VEXTRACTF64X4	$0x1,%ZMM23,%YMM1

0x4086d5 VADDPD	%ZMM1,%ZMM23,%ZMM1

0x4086db VMOVAPD	%XMM1,%XMM22

0x4086e1 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x4086e7 VADDPD	%XMM1,%XMM22,%XMM1

0x4086ed VSHUFPD	$0x1,%XMM1,%XMM1,%XMM22

0x4086f4 VADDSD	%XMM22,%XMM1,%XMM22

0x4086fa VEXTRACTF64X4	$0x1,%ZMM21,%YMM1

0x408701 VADDPD	%ZMM1,%ZMM21,%ZMM1

0x408707 VMOVAPD	%XMM1,%XMM21

0x40870d VEXTRACTF128	$0x1,%YMM1,%XMM1

0x408713 VADDPD	%XMM1,%XMM21,%XMM1

0x408719 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM21

0x408720 VADDSD	%XMM21,%XMM1,%XMM21

0x408726 VEXTRACTF64X4	$0x1,%ZMM20,%YMM1

0x40872d VADDPD	%ZMM1,%ZMM20,%ZMM1

0x408733 VMOVAPD	%XMM1,%XMM20

0x408739 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x40873f VADDPD	%XMM1,%XMM20,%XMM1

0x408745 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM20

0x40874c VADDSD	%XMM20,%XMM1,%XMM20

0x408752 VEXTRACTF64X4	$0x1,%ZMM19,%YMM1

0x408759 VADDPD	%ZMM1,%ZMM19,%ZMM1

0x40875f VMOVAPD	%XMM1,%XMM19

0x408765 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x40876b VADDPD	%XMM1,%XMM19,%XMM1

0x408771 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM19

0x408778 VADDSD	%XMM19,%XMM1,%XMM19

0x40877e VEXTRACTF64X4	$0x1,%ZMM18,%YMM1

0x408785 VADDPD	%ZMM1,%ZMM18,%ZMM1

0x40878b VMOVAPD	%XMM1,%XMM18

0x408791 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x408797 VADDPD	%XMM1,%XMM18,%XMM1

0x40879d VSHUFPD	$0x1,%XMM1,%XMM1,%XMM18

0x4087a4 VADDSD	%XMM18,%XMM1,%XMM18

0x4087aa VEXTRACTF64X4	$0x1,%ZMM17,%YMM1

0x4087b1 VADDPD	%ZMM1,%ZMM17,%ZMM1

0x4087b7 VMOVAPD	%XMM1,%XMM17

0x4087bd VEXTRACTF128	$0x1,%YMM1,%XMM1

0x4087c3 VADDPD	%XMM1,%XMM17,%XMM1

0x4087c9 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM17

0x4087d0 VADDSD	%XMM17,%XMM1,%XMM17

0x4087d6 VEXTRACTF64X4	$0x1,%ZMM16,%YMM1

0x4087dd VADDPD	%ZMM1,%ZMM16,%ZMM1

0x4087e3 VMOVAPD	%XMM1,%XMM16

0x4087e9 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x4087ef VADDPD	%XMM1,%XMM16,%XMM1

0x4087f5 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM16

0x4087fc VADDSD	%XMM16,%XMM1,%XMM16

0x408802 VEXTRACTF64X4	$0x1,%ZMM15,%YMM1

0x408809 VADDPD	%ZMM1,%ZMM15,%ZMM1

0x40880f VMOVAPD	%XMM1,%XMM15

0x408813 VEXTRACTF128	$0x1,%YMM1,%XMM1

0x408819 VADDPD	%XMM1,%XMM15,%XMM1

0x40881d VSHUFPD	$0x1,%XMM1,%XMM1,%XMM15

0x408822 VADDSD	%XMM15,%XMM1,%XMM23

0x408828 CMP	%EDI,0x60(%RSP)

0x40882c JE	408480

0x408832 VPUNPCKLQDQ	%XMM23,%XMM16,%XMM1

0x408838 VPUNPCKLQDQ	%XMM17,%XMM18,%XMM15

0x40883e VINSERTF128	$0x1,%XMM1,%YMM15,%YMM1

0x408844 VPUNPCKLQDQ	%XMM19,%XMM20,%XMM15

0x40884a VPUNPCKLQDQ	%XMM21,%XMM22,%XMM16

0x408850 VINSERTF32X4	$0x1,%XMM15,%YMM16,%YMM15

0x408857 VINSERTF64X4	$0x1,%YMM1,%ZMM15,%ZMM15

0x40885e MOV	%RDI,%RDX

0x408861 JMP	408887

0x408880 VXORPD	%XMM15,%XMM15,%XMM15

0x408885 XOR	%EDX,%EDX

0x408887 MOV	0x40(%RSP),%R15

0x40888c MOV	%R15D,%EBX

0x40888f IMUL	%EDX,%EBX

0x408892 MOV	%RSI,0x30(%RSP)

0x408897 ADD	%ESI,%EBX

0x408899 MOV	0x80(%RSP),%RSI

0x4088a1 MOV	0x60(%RSP),%R10

0x4088a6 NOPW	%CS:(%RAX,%RAX,1)

  (24) 0x4088b0 LEA	(%R11,%RDX,1),%R14D

  (24) 0x4088b4 VMOVSS	(%RSI,%R14,4),%XMM1

  (24) 0x4088ba VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (24) 0x4088be LEA	0x5(%RBX),%R14D

  (24) 0x4088c2 VPBROADCASTD	%EBX,%XMM16

  (24) 0x4088c8 VPADDD	%YMM4,%YMM16,%YMM0

  (24) 0x4088ce VPERMT2D	%YMM16,%YMM5,%YMM0

  (24) 0x4088d4 VPBROADCASTD	%R14D,%YMM8

  (24) 0x4088da VPBLENDD	$0x20,%YMM8,%YMM0,%YMM0

  (24) 0x4088e0 VPADDD	%YMM6,%YMM16,%YMM8

  (24) 0x4088e6 VPERMT2Q	%YMM8,%YMM7,%YMM0

  (24) 0x4088ec VPSUBD	%YMM3,%YMM0,%YMM0

  (24) 0x4088f0 VPXOR	%XMM8,%XMM8,%XMM8

  (24) 0x4088f5 KXNORW	%K0,%K0,%K1

  (24) 0x4088f9 VGATHERDPS	(%R9,%YMM0,4),%YMM8{%K1}

  (24) 0x408900 VCVTPS2PD	%YMM8,%ZMM0

  (24) 0x408906 VBROADCASTSD	%XMM1,%ZMM1

  (24) 0x40890c VFMADD231PD	%ZMM1,%ZMM0,%ZMM15

  (24) 0x408912 INC	%RDX

  (24) 0x408915 ADD	%R15D,%EBX

  (24) 0x408918 CMP	%RDX,%R10

  (24) 0x40891b JNE	4088b0

0x40891d VEXTRACTF32X4	$0x3,%ZMM15,%XMM16

0x408924 VSHUFPD	$0x1,%XMM16,%XMM16,%XMM23

0x40892b VEXTRACTF32X4	$0x2,%ZMM15,%XMM18

0x408932 VSHUFPD	$0x1,%XMM18,%XMM18,%XMM17

0x408939 VMOVAPD	%YMM15,%YMM1

0x40893d VEXTRACTF32X4	$0x1,%YMM15,%XMM20

0x408944 VSHUFPD	$0x1,%XMM20,%XMM20,%XMM19

0x40894b VSHUFPD	$0x1,%XMM1,%XMM1,%XMM21

0x408952 VMOVAPD	%XMM15,%XMM22

0x408958 MOV	0x98(%RSP),%R14

0x408960 MOV	0x88(%RSP),%R15

0x408968 VPBROADCASTD	0x7a73(%RIP),%YMM0

0x408971 MOV	0x30(%RSP),%RSI

0x408976 JMP	408488

/home/eoseret/llm-attention/attention.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.12
CQA speedup if fully vectorized	3.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.17
CQA cycles if no scalar integer	23.83
CQA cycles if FP arith vectorized	22.50
CQA cycles if fully vectorized	7.85
Front-end cycles	17.50
P0 cycles	13.17
P1 cycles	25.17
P2 cycles	2.78
P3 cycles	2.78
P4 cycles	4.33
P5 cycles	25.00
P6 cycles	4.33
P7 cycles	4.33
P8 cycles	4.33
P9 cycles	4.33
P10 cycles	4.33
P11 cycles	2.78
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	97.33
Nb uops	105.00
Nb loads	8.33
Nb stores	8.67
Nb stack references	7.00
FLOP/cycle	2.33
Nb FLOP add-sub	58.67
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.05
Bytes prefetched	0.00
Bytes loaded	61.33
Bytes stored	37.33
Stride 0	0.67
Stride 1	0.00
Stride n	0.00
Stride unknown	1.33
Stride indirect	1.33
Vectorization ratio all	52.69
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	65.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	67.14
Vector-efficiency ratio all	24.07
Vector-efficiency ratio load	11.63
Vector-efficiency ratio store	6.71
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	45.04
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.57

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P1, P5,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	1.75
Front-end cycles	10.67
P0 cycles	8.00
P1 cycles	11.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	4.50
P5 cycles	11.50
P6 cycles	4.00
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	4.00
P11 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	64.00
Nb loads	9.00
Nb stores	9.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.39
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	40.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	29.41
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.62
Vector-efficiency ratio all	15.26
Vector-efficiency ratio load	11.46
Vector-efficiency ratio store	6.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.35

Metric	Value
CQA speedup if no scalar integer	1.04
CQA speedup if FP arith vectorized	1.15
CQA speedup if fully vectorized	2.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.51
Bottlenecks	P1, P5,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	35.50
CQA cycles if no scalar integer	34.00
CQA cycles if FP arith vectorized	31.00
CQA cycles if fully vectorized	12.18
Front-end cycles	23.50
P0 cycles	16.00
P1 cycles	35.50
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	4.50
P5 cycles	35.50
P6 cycles	5.00
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	5.00
P11 cycles	3.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	133.00
Nb uops	141.00
Nb loads	11.00
Nb stores	9.00
Nb stack references	8.00
FLOP/cycle	2.48
Nb FLOP add-sub	88.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.38
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	40.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	2.00
Vectorization ratio all	63.55
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	75.36
Vector-efficiency ratio all	27.75
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	6.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.27

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	1.14
CQA speedup if fully vectorized	2.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P1,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.50
CQA cycles if no scalar integer	26.50
CQA cycles if FP arith vectorized	25.00
CQA cycles if fully vectorized	9.63
Front-end cycles	18.33
P0 cycles	15.50
P1 cycles	28.50
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	4.00
P5 cycles	28.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	103.00
Nb uops	110.00
Nb loads	5.00
Nb stores	8.00
Nb stack references	5.00
FLOP/cycle	3.09
Nb FLOP add-sub	88.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.39
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	65.12
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	64.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	78.43
Vector-efficiency ratio all	29.22
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	44.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	26.10

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:27,30-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 25.17 to 7.85 cycles (3.20x speedup).

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
65% of SSE/AVX addition or subtraction instructions are used in vector version.
67% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 5 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 58.666666666667 FP arithmetical operations:

58.67: addition or subtraction

The binary loop is loading 61 bytes (7 double precision FP elements). The binary loop is storing 37 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.59 FP operations per loaded or stored byte.

General properties

nb instructions	97.33
nb uops	105
loop length	571.67
used x86 registers	10.33
used mmx registers	0
used xmm registers	10
used ymm registers	3.33
used zmm registers	6.33
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	17.50 cycles
front end	17.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.17	25.17	2.78	2.78	4.33	25.00	4.33	4.33	4.33	4.33	4.33	2.78
cycles	13.17	25.17	2.78	2.78	4.33	25.00	4.33	4.33	4.33	4.33	4.33	2.78

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	17.50
Dispatch	25.17
Data deps.	0.00
Overall L1	25.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	60%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

INT+FP

all	52%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	67%

Vector efficiency ratios

INT

all	11%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	24%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.17 cycles. At this rate:

1% of peak load performance is reached (3.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.50 to 1.75 cycles (6.57x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	56
nb uops	64
loop length	315
used x86 registers	11
used mmx registers	0
used xmm registers	10
used ymm registers	3
used zmm registers	1
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.67 cycles
front end	10.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	11.50	3.00	3.00	4.50	11.50	4.00	4.50	4.50	4.50	4.00	3.00
cycles	8.00	11.50	3.00	3.00	4.50	11.50	4.00	4.50	4.50	4.50	4.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	10.67
Dispatch	11.50
Data deps.	0.00
Overall L1	11.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	38%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	55%

INT+FP

all	29%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	11%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	15%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

3% of peak load performance is reached (5.91 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 408524

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM22,%XMM22,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RAX,%R8,1),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x100(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM21,%XMM21,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x1(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM20,%XMM20,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x2(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM19,%XMM19,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x3(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM18,%XMM18,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x4(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM17,%XMM17,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x5(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM16,%XMM16,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x6(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM23,%XMM23,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x7(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP 0x180(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RCX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4082ab <main+0x392b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RCX,8),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 408880 <main+0x3f00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R15D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %EDX,%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %ESI,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x80(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF32X4 $0x3,%ZMM15,%XMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM16,%XMM16,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VEXTRACTF32X4 $0x2,%ZMM15,%XMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM18,%XMM18,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM15,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM15,%XMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM20,%XMM20,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %XMM15,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV 0x98(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTD 0x7a73(%RIP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV 0x30(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 408488 <main+0x3b08>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 27% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 35.50 to 12.18 cycles (2.91x speedup).

Details

63% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 35.50 to 23.50 cycles (1.51x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 9 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VINSERTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 88 FP arithmetical operations:

88: addition or subtraction

The binary loop is loading 80 bytes (10 double precision FP elements). The binary loop is storing 40 bytes (5 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.73 FP operations per loaded or stored byte.

General properties

nb instructions	133
nb uops	141
loop length	788
used x86 registers	11
used mmx registers	0
used xmm registers	10
used ymm registers	5
used zmm registers	9
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.50 cycles
front end	23.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.00	35.50	3.67	3.67	4.50	35.50	5.00	4.50	4.50	4.50	5.00	3.67
cycles	16.00	35.50	3.67	3.67	4.50	35.50	5.00	4.50	4.50	4.50	5.00	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	23.50
Dispatch	35.50
Data deps.	0.00
Overall L1	35.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	73%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	86%

INT+FP

all	63%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Vector efficiency ratios

INT

all	11%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	30%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	27%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 35.50 cycles. At this rate:

1% of peak load performance is reached (2.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 408524

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM22,%XMM22,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RAX,%R8,1),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x100(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM21,%XMM21,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x1(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM20,%XMM20,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x2(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM19,%XMM19,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x3(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM18,%XMM18,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x4(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM17,%XMM17,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x5(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM16,%XMM16,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x6(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM23,%XMM23,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x7(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP 0x180(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RCX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4082ab <main+0x392b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RCX,8),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 408880 <main+0x3f00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %R8D,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x80(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF64X4 $0x1,%ZMM23,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM23,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM22,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM22,%XMM1,%XMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM21,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM21,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM21,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM21,%XMM1,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM20,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM20,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM20,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM20,%XMM1,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM19,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM19,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM19,%XMM1,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM18,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM18,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM18,%XMM1,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM17,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM17,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM17,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM17,%XMM1,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM16,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM16,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM16,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM16,%XMM1,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM15,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM15,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM15,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM15,%XMM1,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %EDI,0x60(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 408480 <main+0x3b00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPUNPCKLQDQ %XMM23,%XMM16,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM17,%XMM18,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM1,%YMM15,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKLQDQ %XMM19,%XMM20,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPUNPCKLQDQ %XMM21,%XMM22,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM15,%YMM16,%YMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VINSERTF64X4 $0x1,%YMM1,%ZMM15,%ZMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 408887 <main+0x3f07>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x40(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R15D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %EDX,%EBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %ESI,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x80(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF32X4 $0x3,%ZMM15,%XMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM16,%XMM16,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VEXTRACTF32X4 $0x2,%ZMM15,%XMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM18,%XMM18,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM15,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM15,%XMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM20,%XMM20,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %XMM15,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV 0x98(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTD 0x7a73(%RIP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV 0x30(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 408488 <main+0x3b08>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.50 to 26.50 cycles (1.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 29% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 28.50 to 9.63 cycles (2.96x speedup).

Details

65% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
64% of SSE/AVX addition or subtraction instructions are used in vector version.
78% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 88 FP arithmetical operations:

88: addition or subtraction

The binary loop is loading 36 bytes (4 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.29 FP operations per loaded or stored byte.

General properties

nb instructions	103
nb uops	110
loop length	612
used x86 registers	9
used mmx registers	0
used xmm registers	10
used ymm registers	2
used zmm registers	9
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	18.33 cycles
front end	18.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.50	28.50	1.67	1.67	4.00	28.00	4.00	4.00	4.00	4.00	4.00	1.67
cycles	15.50	28.50	1.67	1.67	4.00	28.00	4.00	4.00	4.00	4.00	4.00	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	18.33
Dispatch	28.50
Data deps.	0.00
Overall L1	28.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	70%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	83%

INT+FP

all	65%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	64%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	78%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	30%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	29%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

0% of peak load performance is reached (1.26 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 408524

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x88(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCVTSD2SS %XMM22,%XMM22,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RAX,%R8,1),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x100(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM21,%XMM21,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x1(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM20,%XMM20,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x2(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM19,%XMM19,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x3(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM18,%XMM18,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x4(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM17,%XMM17,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x5(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM16,%XMM16,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x6(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM23,%XMM23,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x7(%RAX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM1,(%RBX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP 0x180(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RCX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4082ab <main+0x392b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RCX,8),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 408880 <main+0x3f00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %R8D,%YMM22	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM15,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM19,%XMM19,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM20,%XMM20,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM21,%XMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM23,%XMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x80(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF64X4 $0x1,%ZMM23,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM23,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM22,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM22,%XMM1,%XMM22	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM21,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM21,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM21,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM21,%XMM1,%XMM21	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM20,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM20,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM20,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM20,%XMM1,%XMM20	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM19,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM19,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM19,%XMM1,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM18,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM18,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM18,%XMM1,%XMM18	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM17,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM17,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM17,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM17,%XMM1,%XMM17	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM16,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM16,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM16,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM16,%XMM1,%XMM16	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VEXTRACTF64X4 $0x1,%ZMM15,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM15,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM15,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM15	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM15,%XMM1,%XMM23	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %EDI,0x60(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JE 408480 <main+0x3b00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

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Complex instructions

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Slow data structures access

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Conversion instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

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Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

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Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

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Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround