OV - attention-avx512 - Function __svml_expf16

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4099b0 ENDBR64

0x4099b4 VMOVUPS	0x9502(%RIP),%ZMM1

0x4099be VMOVUPS	0x9538(%RIP),%ZMM2

0x4099c8 VFMADD213PS	{rz-sae},%ZMM2,%ZMM0,%ZMM1

0x4099ce VSUBPS	{rn-sae},%ZMM2,%ZMM1,%ZMM2

0x4099d4 VMOVUPS	0x9562(%RIP),%ZMM3

0x4099de VMOVUPS	0x9598(%RIP),%ZMM4

0x4099e8 VFNMADD213PS	{rn-sae},%ZMM0,%ZMM2,%ZMM3

0x4099ee VFNMADD231PS	{rn-sae},%ZMM4,%ZMM2,%ZMM3

0x4099f4 VPERMPS	0x9482(%RIP),%ZMM1,%ZMM0

0x4099fe VANDPS	0x95b8(%RIP),%ZMM3,%ZMM1

0x409a08 VMOVUPS	0x95ee(%RIP),%ZMM3

0x409a12 VMOVUPS	0x9624(%RIP),%ZMM4

0x409a1c VFMADD231PS	{rn-sae},%ZMM3,%ZMM1,%ZMM4

0x409a22 VMULPS	{rn-sae},%ZMM1,%ZMM1,%ZMM3

0x409a28 VFMADD213PS	{rn-sae},%ZMM1,%ZMM4,%ZMM3

0x409a2e VFMADD213PS	{rn-sae},%ZMM0,%ZMM0,%ZMM3

0x409a34 VANDPS	0x9642(%RIP),%ZMM3,%ZMM0

0x409a3e VSCALEFPS	{rn-sae},%ZMM2,%ZMM0,%ZMM0

0x409a44 RET

0x409a45 NOPW	%CS:(%RAX,%RAX,1)

0x409a4f NOP

Coverage (%)	Name	Source Location	Module
○100.00	main	attention.cpp:53	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.28% of application time for run run_0

Source file and lines
Module	attention-avx512

gain
potential
hint
expert

Vectorization

Your function is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.00 cycles (1.50x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 96 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.09x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

9 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 224 FP arithmetical operations:

112: addition or subtraction (96 inside FMA instructions)
112: multiply (96 inside FMA instructions)

The binary function is loading 576 bytes (144 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.39 FP operations per loaded or stored byte.

General properties

nb instructions	20
nb uops	19
loop length	149
used x86 registers	0
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	5
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.17 cycles
front end	3.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.00	0.00	3.33	3.33	0.00	6.00	1.00	0.00	0.00	0.00	0.00	3.33
cycles	6.00	4.00	3.33	3.33	0.00	6.00	1.00	0.00	0.00	0.00	0.00	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.17
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

50% of peak load performance is reached (96.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4099b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVUPS 0x9502(%RIP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS 0x9538(%RIP),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PS {rz-sae},%ZMM2,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPS {rn-sae},%ZMM2,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPS 0x9562(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS 0x9598(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFNMADD213PS {rn-sae},%ZMM0,%ZMM2,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFNMADD231PS {rn-sae},%ZMM4,%ZMM2,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPERMPS 0x9482(%RIP),%ZMM1,%ZMM0	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (100.0%)
VANDPS 0x95b8(%RIP),%ZMM3,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVUPS 0x95ee(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS 0x9624(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD231PS {rn-sae},%ZMM3,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPS {rn-sae},%ZMM1,%ZMM1,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PS {rn-sae},%ZMM1,%ZMM4,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PS {rn-sae},%ZMM0,%ZMM0,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPS 0x9642(%RIP),%ZMM3,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VSCALEFPS {rn-sae},%ZMM2,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.28% of application time for run run_0

Source file and lines
Module	attention-avx512

gain
potential
hint
expert

Vectorization

Your function is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.00 cycles (1.50x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 96 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.09x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

9 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 224 FP arithmetical operations:

112: addition or subtraction (96 inside FMA instructions)
112: multiply (96 inside FMA instructions)

The binary function is loading 576 bytes (144 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.39 FP operations per loaded or stored byte.

General properties

nb instructions	20
nb uops	19
loop length	149
used x86 registers	0
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	5
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.17 cycles
front end	3.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.00	0.00	3.33	3.33	0.00	6.00	1.00	0.00	0.00	0.00	0.00	3.33
cycles	6.00	4.00	3.33	3.33	0.00	6.00	1.00	0.00	0.00	0.00	0.00	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.17
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

50% of peak load performance is reached (96.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4099b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVUPS 0x9502(%RIP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS 0x9538(%RIP),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PS {rz-sae},%ZMM2,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPS {rn-sae},%ZMM2,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPS 0x9562(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS 0x9598(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFNMADD213PS {rn-sae},%ZMM0,%ZMM2,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFNMADD231PS {rn-sae},%ZMM4,%ZMM2,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPERMPS 0x9482(%RIP),%ZMM1,%ZMM0	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (100.0%)
VANDPS 0x95b8(%RIP),%ZMM3,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VMOVUPS 0x95ee(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS 0x9624(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD231PS {rn-sae},%ZMM3,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPS {rn-sae},%ZMM1,%ZMM1,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PS {rn-sae},%ZMM1,%ZMM4,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD213PS {rn-sae},%ZMM0,%ZMM0,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VANDPS 0x9642(%RIP),%ZMM3,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.67	vect (100.0%)
VSCALEFPS {rn-sae},%ZMM2,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

Name	Coverage (%)	Time (s)
○__svml_expf16_z0	0.28	0.01

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code