OV - attention-avx512 - Loop 57

	Loop Id: 57	Module: attention-avx512	Source: attention.cpp:27-33	Coverage: 0.40%

0x405380 XOR	%R12D,%R12D

0x405383 VMOVAPD	%ZMM9,%ZMM10

0x405389 LEA	(%RDX,%R12,1),%ESI

0x40538d VMOVSS	(%R14,%RSI,4),%XMM9

0x405393 IMUL	%R11D,%R12D

0x405397 LEA	(%RBX,%R12,1),%ESI

0x40539b LEA	0x3(%RBX,%R12,1),%EDI

0x4053a0 VPBROADCASTD	%ESI,%YMM11

0x4053a6 VPADDD	%YMM4,%YMM11,%YMM12

0x4053aa VPBROADCASTD	%EDI,%YMM13

0x4053b0 VPBLENDD	$0x10,%YMM13,%YMM12,%YMM12

0x4053b6 VPADDD	%YMM5,%YMM11,%YMM13

0x4053ba VPERMT2D	%YMM13,%YMM6,%YMM12

0x4053c0 VPBLENDD	$-0x80,%YMM11,%YMM12,%YMM11

0x4053c6 VPSUBD	%YMM2,%YMM11,%YMM11

0x4053ca KXNORB	%K0,%K0,%K1

0x4053ce VPXOR	%XMM12,%XMM12,%XMM12

0x4053d3 VGATHERDPS	(%RAX,%YMM11,4),%YMM12{%K1}

0x4053da VCVTSS2SD	%XMM9,%XMM9,%XMM9

0x4053df VCVTPS2PD	%YMM12,%ZMM11

0x4053e5 VBROADCASTSD	%XMM9,%ZMM9

0x4053eb VFMADD213PD	%ZMM10,%ZMM11,%ZMM9

0x4053f1 VEXTRACTF32X4	$0x3,%ZMM9,%XMM10

0x4053f8 VSHUFPD	$0x1,%XMM10,%XMM10,%XMM11

0x4053fe VCVTSD2SS	%XMM11,%XMM11,%XMM11

0x405403 LEA	(%RDX,%RBX,1),%ESI

0x405406 VMOVSS	%XMM11,(%R15,%RSI,4)

0x40540c VCVTSD2SS	%XMM10,%XMM10,%XMM10

0x405411 LEA	0x1(%RDX,%RBX,1),%ESI

0x405415 VMOVSS	%XMM10,(%R15,%RSI,4)

0x40541b VEXTRACTF32X4	$0x2,%ZMM9,%XMM10

0x405422 VSHUFPD	$0x1,%XMM10,%XMM10,%XMM11

0x405428 VCVTSD2SS	%XMM11,%XMM11,%XMM11

0x40542d LEA	0x2(%RDX,%RBX,1),%ESI

0x405431 VMOVSS	%XMM11,(%R15,%RSI,4)

0x405437 VCVTSD2SS	%XMM10,%XMM10,%XMM10

0x40543c LEA	0x3(%RDX,%RBX,1),%ESI

0x405440 VMOVSS	%XMM10,(%R15,%RSI,4)

0x405446 VEXTRACTF128	$0x1,%YMM9,%XMM10

0x40544c VSHUFPD	$0x1,%XMM10,%XMM10,%XMM11

0x405452 VCVTSD2SS	%XMM11,%XMM11,%XMM11

0x405457 LEA	0x4(%RDX,%RBX,1),%ESI

0x40545b VMOVSS	%XMM11,(%R15,%RSI,4)

0x405461 VCVTSD2SS	%XMM10,%XMM10,%XMM10

0x405466 LEA	0x5(%RDX,%RBX,1),%ESI

0x40546a VMOVSS	%XMM10,(%R15,%RSI,4)

0x405470 VSHUFPD	$0x1,%XMM9,%XMM9,%XMM10

0x405476 VCVTSD2SS	%XMM10,%XMM10,%XMM10

0x40547b LEA	0x6(%RDX,%RBX,1),%ESI

0x40547f VMOVSS	%XMM10,(%R15,%RSI,4)

0x405485 VCVTSD2SS	%XMM9,%XMM9,%XMM9

0x40548a LEA	0x7(%RDX,%RBX,1),%ESI

0x40548e VMOVSS	%XMM9,(%R15,%RSI,4)

0x405494 MOV	0x40(%RSP),%EDI

0x405498 ADD	$0x8,%EDI

0x40549b MOV	0x30(%RSP),%RSI

0x4054a0 ADD	$0x8,%ESI

0x4054a3 MOV	0x50(%RSP),%RBX

0x4054a8 CMP	0x70(%RSP),%RBX

0x4054ad LEA	0x1(%RBX),%RBX

0x4054b1 JE	405600

0x4054b7 MOV	%RBX,0x50(%RSP)

0x4054bc LEA	(,%RBX,8),%EBX

0x4054c3 CMPQ	$0,0x38(%RSP)

0x4054c9 MOV	%RSI,0x30(%RSP)

0x4054ce MOV	%EDI,0x40(%RSP)

0x4054d2 VXORPS	%XMM9,%XMM9,%XMM9

0x4054d7 JE	405380

0x4054dd MOV	%ESI,%R13D

0x4054e0 MOV	%R14,%R11

0x4054e3 MOV	%EDI,%R14D

0x4054e6 MOV	0x28(%RSP),%ESI

0x4054ea MOV	%ESI,%EDI

0x4054ec XOR	%R12D,%R12D

0x4054ef NOP

  (58) 0x4054f0 LEA	-0x1(%RDI),%ESI

  (58) 0x4054f3 VMOVSS	(%R11,%RSI,4),%XMM10

  (58) 0x4054f9 VCVTSS2SD	%XMM10,%XMM10,%XMM10

  (58) 0x4054fe LEA	0x3(%R13),%ESI

  (58) 0x405502 VPBROADCASTD	%R13D,%YMM11

  (58) 0x405508 VPADDD	%YMM7,%YMM11,%YMM12

  (58) 0x40550c VPBROADCASTD	%ESI,%YMM13

  (58) 0x405512 VPBLENDD	$0x10,%YMM13,%YMM12,%YMM12

  (58) 0x405518 VPADDD	%YMM8,%YMM11,%YMM13

  (58) 0x40551d VPERMT2D	%YMM13,%YMM6,%YMM12

  (58) 0x405523 VPBLENDD	$-0x80,%YMM11,%YMM12,%YMM11

  (58) 0x405529 VPSUBD	%YMM2,%YMM11,%YMM11

  (58) 0x40552d KXNORB	%K0,%K0,%K1

  (58) 0x405531 VPXOR	%XMM12,%XMM12,%XMM12

  (58) 0x405536 VGATHERDPS	(%RAX,%YMM11,4),%YMM12{%K1}

  (58) 0x40553d VCVTPS2PD	%YMM12,%ZMM11

  (58) 0x405543 VBROADCASTSD	%XMM10,%ZMM10

  (58) 0x405549 VMULPD	%ZMM10,%ZMM11,%ZMM10

  (58) 0x40554f VADDPD	%ZMM10,%ZMM9,%ZMM9

  (58) 0x405555 MOV	%EDI,%ESI

  (58) 0x405557 VMOVSS	(%R11,%RSI,4),%XMM10

  (58) 0x40555d LEA	0x3(%R14),%ESI

  (58) 0x405561 VPBROADCASTD	%R14D,%YMM11

  (58) 0x405567 VPADDD	%YMM7,%YMM11,%YMM12

  (58) 0x40556b VPBROADCASTD	%ESI,%YMM13

  (58) 0x405571 VPBLENDD	$0x10,%YMM13,%YMM12,%YMM12

  (58) 0x405577 VPADDD	%YMM8,%YMM11,%YMM13

  (58) 0x40557c VPERMT2D	%YMM13,%YMM6,%YMM12

  (58) 0x405582 VPBLENDD	$-0x80,%YMM11,%YMM12,%YMM11

  (58) 0x405588 VPSUBD	%YMM2,%YMM11,%YMM11

  (58) 0x40558c KXNORB	%K0,%K0,%K1

  (58) 0x405590 VPXOR	%XMM12,%XMM12,%XMM12

  (58) 0x405595 VGATHERDPS	(%RAX,%YMM11,4),%YMM12{%K1}

  (58) 0x40559c VCVTSS2SD	%XMM10,%XMM10,%XMM10

  (58) 0x4055a1 VCVTPS2PD	%YMM12,%ZMM11

  (58) 0x4055a7 VBROADCASTSD	%XMM10,%ZMM10

  (58) 0x4055ad VMULPD	%ZMM10,%ZMM11,%ZMM10

  (58) 0x4055b3 VADDPD	%ZMM10,%ZMM9,%ZMM9

  (58) 0x4055b9 ADD	$0x2,%R12

  (58) 0x4055bd ADD	$0x2,%EDI

  (58) 0x4055c0 ADD	%R10D,%R14D

  (58) 0x4055c3 ADD	%R10D,%R13D

  (58) 0x4055c6 CMP	%R12,%R8

  (58) 0x4055c9 JNE	4054f0

0x4055cf MOV	0x18(%RSP),%RSI

0x4055d4 TEST	$0x1,%SIL

0x4055d8 MOV	%R11,%R14

0x4055db MOV	%RSI,%R11

0x4055de MOV	0x90(%RSP),%R13

0x4055e6 JNE	405383

0x4055ec JMP	4053f1

/home/eoseret/llm-attention/attention.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.01
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.11
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.11
CQA cycles if fully vectorized	7.42
Front-end cycles	13.56
P0 cycles	13.56
P1 cycles	14.78
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	5.50
P5 cycles	15.00
P6 cycles	5.33
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	5.33
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.33
Nb uops	81.33
Nb loads	8.33
Nb stores	11.00
Nb stack references	7.00
FLOP/cycle	0.71
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	5.33
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.43
Bytes prefetched	0.00
Bytes loaded	73.33
Bytes stored	52.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	32.79
Vectorization ratio load	13.89
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	43.68
Vector-efficiency ratio all	19.22
Vector-efficiency ratio load	15.45
Vector-efficiency ratio store	7.39
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	28.13
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.49

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.66
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P5,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	10.24
Front-end cycles	13.67
P0 cycles	16.33
P1 cycles	16.67
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	5.50
P5 cycles	17.00
P6 cycles	5.00
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	5.00
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	82.00
Nb loads	7.00
Nb stores	11.00
Nb stack references	5.00
FLOP/cycle	0.94
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.29
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	52.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	41.30
Vectorization ratio load	25.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	75.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.57
Vector-efficiency ratio all	23.23
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	7.39
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	39.06
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.67

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.33
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.33
CQA cycles if fully vectorized	1.75
Front-end cycles	11.33
P0 cycles	8.00
P1 cycles	11.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	5.50
P5 cycles	11.00
P6 cycles	5.00
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	5.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	68.00
Nb loads	8.00
Nb stores	11.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.53
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	52.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	20.51
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	32.00
Vector-efficiency ratio all	12.66
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	7.39
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.66
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P5,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	10.26
Front-end cycles	15.67
P0 cycles	16.33
P1 cycles	16.67
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	5.50
P5 cycles	17.00
P6 cycles	6.00
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	6.00
P11 cycles	5.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	94.00
Nb loads	10.00
Nb stores	11.00
Nb stack references	8.00
FLOP/cycle	0.94
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.47
Bytes prefetched	0.00
Bytes loaded	92.00
Bytes stored	52.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	36.54
Vectorization ratio load	16.67
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	75.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	45.45
Vector-efficiency ratio all	21.75
Vector-efficiency ratio load	16.67
Vector-efficiency ratio store	7.39
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	39.06
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.30

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:27,30-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 19% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 15.11 to 7.42 cycles (2.04x speedup).

Details

32% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

13% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
43% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 5.33 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 0 occurrences
VCVTSD2SS: 0 occurrences
VCVTSS2SD: 0 occurrences
VGATHERDPS: 0 occurrences

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 0 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 0 occurrences
VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences
VCVTSS2SD (FP32 to FP64, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

0 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10.666666666667 FP arithmetical operations:

5.33: addition or subtraction (all inside FMA instructions)
5.33: multiply (all inside FMA instructions)

The binary loop is loading 73 bytes (9 double precision FP elements). The binary loop is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	69.33
nb uops	81.33
loop length	344
used x86 registers	10.33
used mmx registers	0
used xmm registers	3.67
used ymm registers	5.67
used zmm registers	2.33
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	13.56 cycles
front end	13.56 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.56	14.78	4.33	4.33	5.50	15.00	5.33	5.50	5.50	5.50	5.33	4.33
cycles	13.56	14.78	4.33	4.33	5.50	15.00	5.33	5.50	5.50	5.50	5.33	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	13.56
Dispatch	15.00
Data deps.	0.00
Overall L1	15.11

Vectorization ratios

INT

all	26%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	36%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

INT+FP

all	32%
load	13%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Vector efficiency ratios

INT

all	19%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	19%
load	28%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

INT+FP

all	19%
load	15%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	28%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.11 cycles. At this rate:

2% of peak load performance is reached (4.86 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 23% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 17.00 to 10.24 cycles (1.66x speedup).

Details

41% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
75% of SSE/AVX addition or subtraction instructions are used in vector version.
53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
VCVTSS2SD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
VCVTSS2SD (FP32 to FP64, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 72 bytes (9 double precision FP elements). The binary loop is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	82
loop length	349
used x86 registers	10
used mmx registers	0
used xmm registers	4
used ymm registers	8
used zmm registers	3
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.33	16.67	4.67	4.67	5.50	17.00	5.00	5.50	5.50	5.50	5.00	4.67
cycles	16.33	16.67	4.67	4.67	5.50	17.00	5.00	5.50	5.50	5.50	5.00	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	13.67
Dispatch	17.00
Data deps.	0.00
Overall L1	17.00

Vectorization ratios

INT

all	46%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
other	57%

all	38%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	52%

INT+FP

all	41%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	26%
load	9%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	39%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	21%
load	28%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

INT+FP

all	23%
load	18%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	39%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

2% of peak load performance is reached (4.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.06 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4054b7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %ZMM9,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
LEA (%RDX,%R12,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSS (%R14,%RSI,4),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
IMUL %R11D,%R12D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RBX,%R12,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x3(%RBX,%R12,1),%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPBROADCASTD %ESI,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPADDD %YMM4,%YMM11,%YMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBROADCASTD %EDI,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x10,%YMM13,%YMM12,%YMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM5,%YMM11,%YMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM13,%YMM6,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPBLENDD $-0x80,%YMM11,%YMM12,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM2,%YMM11,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VPXOR %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPS (%RAX,%YMM11,4),%YMM12{%K1}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VCVTSS2SD %XMM9,%XMM9,%XMM9	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VCVTPS2PD %YMM12,%ZMM11	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VBROADCASTSD %XMM9,%ZMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VFMADD213PD %ZMM10,%ZMM11,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM9,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RDX,%RBX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSS %XMM11,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x1(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VEXTRACTF32X4 $0x2,%ZMM9,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x2(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM11,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x3(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VEXTRACTF128 $0x1,%YMM9,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x4(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM11,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x5(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VSHUFPD $0x1,%XMM9,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x6(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM9,%XMM9,%XMM9	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x7(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM9,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x40(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x8,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x30(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x70(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RBX),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 405600 <main+0x12c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RBX,8),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMPQ $0,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VXORPS %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JE 405380 <main+0x1040>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.33 to 1.75 cycles (6.48x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 52 bytes.

General properties

nb instructions	60
nb uops	68
loop length	289
used x86 registers	10
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	1
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.33 cycles
front end	11.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	11.00	2.67	2.67	5.50	11.00	5.00	5.50	5.50	5.50	5.00	2.67
cycles	8.00	11.00	2.67	2.67	5.50	11.00	5.00	5.50	5.50	5.50	5.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	11.33
Dispatch	11.00
Data deps.	0.00
Overall L1	11.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	20%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Vector efficiency ratios

INT

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.33 cycles. At this rate:

2% of peak load performance is reached (4.94 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.59 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4054b7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VEXTRACTF32X4 $0x3,%ZMM9,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RDX,%RBX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSS %XMM11,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x1(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VEXTRACTF32X4 $0x2,%ZMM9,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x2(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM11,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x3(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VEXTRACTF128 $0x1,%YMM9,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x4(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM11,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x5(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VSHUFPD $0x1,%XMM9,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x6(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM9,%XMM9,%XMM9	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x7(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM9,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x40(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x8,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x30(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x70(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RBX),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 405600 <main+0x12c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RBX,8),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMPQ $0,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VXORPS %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JE 405380 <main+0x1040>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ESI,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x28(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x18(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x1,%SIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV %R11,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x90(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 405383 <main+0x1043>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4053f1 <main+0x10b1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:27-33
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 17.00 to 10.26 cycles (1.66x speedup).

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
75% of SSE/AVX addition or subtraction instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSD2SS: 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
VCVTSS2SD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 8 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
- /home/eoseret/llm-attention/attention.cpp:33
VCVTSS2SD (FP32 to FP64, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 92 bytes (11 double precision FP elements). The binary loop is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	80
nb uops	94
loop length	394
used x86 registers	11
used mmx registers	0
used xmm registers	4
used ymm registers	8
used zmm registers	3
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.67 cycles
front end	15.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.33	16.67	5.67	5.67	5.50	17.00	6.00	5.50	5.50	5.50	6.00	5.67
cycles	16.33	16.67	5.67	5.67	5.50	17.00	6.00	5.50	5.50	5.50	6.00	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	15.67
Dispatch	17.00
Data deps.	0.00
Overall L1	17.00

Vectorization ratios

INT

all	33%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	38%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	52%

INT+FP

all	36%
load	16%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	21%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	39%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	21%
load	28%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

INT+FP

all	21%
load	16%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	39%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

2% of peak load performance is reached (5.41 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.06 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4054b7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPD %ZMM9,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
LEA (%RDX,%R12,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSS (%R14,%RSI,4),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
IMUL %R11D,%R12D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RBX,%R12,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x3(%RBX,%R12,1),%EDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPBROADCASTD %ESI,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPADDD %YMM4,%YMM11,%YMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBROADCASTD %EDI,%YMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x10,%YMM13,%YMM12,%YMM12	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM5,%YMM11,%YMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM13,%YMM6,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPBLENDD $-0x80,%YMM11,%YMM12,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM2,%YMM11,%YMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VPXOR %XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPS (%RAX,%YMM11,4),%YMM12{%K1}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VCVTSS2SD %XMM9,%XMM9,%XMM9	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	4-5	1	scal (6.3%)
VCVTPS2PD %YMM12,%ZMM11	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VBROADCASTSD %XMM9,%ZMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VFMADD213PD %ZMM10,%ZMM11,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM9,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RDX,%RBX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSS %XMM11,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x1(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VEXTRACTF32X4 $0x2,%ZMM9,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x2(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM11,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x3(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VEXTRACTF128 $0x1,%YMM9,%XMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VSHUFPD $0x1,%XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x4(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM11,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x5(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VSHUFPD $0x1,%XMM9,%XMM9,%XMM10	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VCVTSD2SS %XMM10,%XMM10,%XMM10	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x6(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM10,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VCVTSD2SS %XMM9,%XMM9,%XMM9	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA 0x7(%RDX,%RBX,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSS %XMM9,(%R15,%RSI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x40(%RSP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x8,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x30(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x70(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RBX),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 405600 <main+0x12c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RBX,8),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMPQ $0,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EDI,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VXORPS %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JE 405380 <main+0x1040>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ESI,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x18(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x1,%SIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV %R11,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x90(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 405383 <main+0x1043>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

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FMA

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Vector unaligned load/store instructions

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Gather/scatter instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

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Cycles and memory resources usage

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Execution units bottlenecks

Complex instructions

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Slow data structures access

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Vector unaligned load/store instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

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