OV - attention-avx512 - Loop 52

	Loop Id: 52	Module: attention-avx512	Source: attention.cpp:30-31	Coverage: 8.24%

0x405b90 LEA	-0x1(%R13),%R11D

0x405b94 VMOVSS	(%RDX,%R11,4),%XMM11    [1]

0x405b9a VCVTSS2SD	%XMM11,%XMM11,%XMM11

0x405b9f LEA	0x5(%RDI),%R11D

0x405ba3 VPBROADCASTD	%EDI,%XMM12

0x405ba9 VPADDD	%YMM8,%YMM12,%YMM13

0x405bae VPERMT2D	%YMM12,%YMM5,%YMM13

0x405bb4 VPBROADCASTD	%R11D,%YMM14

0x405bba VPBLENDD	$0x20,%YMM14,%YMM13,%YMM13

0x405bc0 VPADDD	%YMM9,%YMM12,%YMM12

0x405bc5 VPERMT2Q	%YMM12,%YMM7,%YMM13

0x405bcb VPSUBD	%YMM2,%YMM13,%YMM12

0x405bcf VPXOR	%XMM13,%XMM13,%XMM13

0x405bd4 KXNORB	%K0,%K0,%K1

0x405bd8 VGATHERDPS	(%RAX,%YMM12,4),%YMM13{%K1}    [2]

0x405bdf VCVTPS2PD	%YMM13,%ZMM12

0x405be5 VBROADCASTSD	%XMM11,%ZMM11

0x405beb VMULPD	%ZMM11,%ZMM12,%ZMM11

0x405bf1 VADDPD	%ZMM11,%ZMM10,%ZMM10

0x405bf7 MOV	%R13D,%R11D

0x405bfa VMOVSS	(%RDX,%R11,4),%XMM11    [1]

0x405c00 LEA	0x5(%RSI),%R11D

0x405c04 VPBROADCASTD	%ESI,%XMM12

0x405c0a VPADDD	%YMM8,%YMM12,%YMM13

0x405c0f VPERMT2D	%YMM12,%YMM5,%YMM13

0x405c15 VPBROADCASTD	%R11D,%YMM14

0x405c1b VPBLENDD	$0x20,%YMM14,%YMM13,%YMM13

0x405c21 VPADDD	%YMM9,%YMM12,%YMM12

0x405c26 VPERMT2Q	%YMM12,%YMM7,%YMM13

0x405c2c VPSUBD	%YMM2,%YMM13,%YMM12

0x405c30 VPXOR	%XMM13,%XMM13,%XMM13

0x405c35 KXNORB	%K0,%K0,%K1

0x405c39 VGATHERDPS	(%RAX,%YMM12,4),%YMM13{%K1}    [2]

0x405c40 VCVTSS2SD	%XMM11,%XMM11,%XMM11

0x405c45 VCVTPS2PD	%YMM13,%ZMM12

0x405c4b VBROADCASTSD	%XMM11,%ZMM11

0x405c51 VMULPD	%ZMM11,%ZMM12,%ZMM11

0x405c57 VADDPD	%ZMM11,%ZMM10,%ZMM10

0x405c5d ADD	$0x2,%R12

0x405c61 ADD	$0x2,%R13D

0x405c65 ADD	%R10D,%ESI

0x405c68 ADD	%R10D,%EDI

0x405c6b CMP	%R12,%R8

0x405c6e JNE	405b90

/home/eoseret/llm-attention/attention.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P5,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	6.00
Front-end cycles	9.17
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	0.00
P5 cycles	14.00
P6 cycles	3.60
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.40
P11 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	6
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	55.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.29
Nb FLOP add-sub	16.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.14
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	68.75
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	60.00
Vector-efficiency ratio all	41.41
Vector-efficiency ratio load	28.13
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	30.63

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P5,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	6.00
Front-end cycles	9.17
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	0.00
P5 cycles	14.00
P6 cycles	3.60
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	3.40
P11 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	6
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	55.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.29
Nb FLOP add-sub	16.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.14
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	68.75
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	60.00
Vector-efficiency ratio all	41.41
Vector-efficiency ratio load	28.13
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	30.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 41% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.00 to 6.00 cycles (2.33x speedup).

Details

68% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.00 to 12.00 cycles (1.17x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSS2SD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSS2SD (FP32 to FP64, scalar): 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: multiply

The binary loop is loading 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.44 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	55
loop length	228
used x86 registers	9
used mmx registers	0
used xmm registers	3
used ymm registers	8
used zmm registers	3
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.00	12.00	6.00	6.00	0.00	14.00	3.60	0.00	0.00	0.00	3.40	6.00
cycles	12.00	12.00	6.00	6.00	0.00	14.00	3.60	0.00	0.00	0.00	3.40	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	6.00

Cycles summary

Front-end	9.17
Dispatch	14.00
Data deps.	6.00
Overall L1	14.00

Vectorization ratios

INT

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	57%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	68%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

Vector efficiency ratios

INT

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	46%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

INT+FP

all	41%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

2% of peak load performance is reached (5.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405b90

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA -0x1(%R13),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%RDX,%R11,4),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
LEA 0x5(%RDI),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %EDI,%XMM12	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM8,%YMM12,%YMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM12,%YMM5,%YMM13	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %R11D,%YMM14	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x20,%YMM14,%YMM13,%YMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM9,%YMM12,%YMM12	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2Q %YMM12,%YMM7,%YMM13	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPSUBD %YMM2,%YMM13,%YMM12	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RAX,%YMM12,4),%YMM13{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM13,%ZMM12	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VBROADCASTSD %XMM11,%ZMM11	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMULPD %ZMM11,%ZMM12,%ZMM11	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM10,%ZMM10	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
MOV %R13D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%RDX,%R11,4),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
LEA 0x5(%RSI),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %ESI,%XMM12	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM8,%YMM12,%YMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM12,%YMM5,%YMM13	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %R11D,%YMM14	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x20,%YMM14,%YMM13,%YMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM9,%YMM12,%YMM12	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2Q %YMM12,%YMM7,%YMM13	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPSUBD %YMM2,%YMM13,%YMM12	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RAX,%YMM12,4),%YMM13{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTSS2SD %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VCVTPS2PD %YMM13,%ZMM12	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VBROADCASTSD %XMM11,%ZMM11	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMULPD %ZMM11,%ZMM12,%ZMM11	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM10,%ZMM10	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
ADD $0x2,%R12	1	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x2,%R13D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %R10D,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %R10D,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMP %R12,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 405b90 <main+0x1850>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

68% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSS2SD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSS2SD (FP32 to FP64, scalar): 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Type of elements and instruction set

4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: multiply

The binary loop is loading 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.44 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	55
loop length	228
used x86 registers	9
used mmx registers	0
used xmm registers	3
used ymm registers	8
used zmm registers	3
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.00	12.00	6.00	6.00	0.00	14.00	3.60	0.00	0.00	0.00	3.40	6.00
cycles	12.00	12.00	6.00	6.00	0.00	14.00	3.60	0.00	0.00	0.00	3.40	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	6.00

Cycles summary

Front-end	9.17
Dispatch	14.00
Data deps.	6.00
Overall L1	14.00

Vectorization ratios

INT

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	57%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	68%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

Vector efficiency ratios

INT

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	46%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

INT+FP

all	41%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

2% of peak load performance is reached (5.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405b90

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA -0x1(%R13),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%RDX,%R11,4),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
LEA 0x5(%RDI),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %EDI,%XMM12	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM8,%YMM12,%YMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM12,%YMM5,%YMM13	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %R11D,%YMM14	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x20,%YMM14,%YMM13,%YMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM9,%YMM12,%YMM12	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2Q %YMM12,%YMM7,%YMM13	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPSUBD %YMM2,%YMM13,%YMM12	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RAX,%YMM12,4),%YMM13{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM13,%ZMM12	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VBROADCASTSD %XMM11,%ZMM11	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMULPD %ZMM11,%ZMM12,%ZMM11	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM10,%ZMM10	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
MOV %R13D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%RDX,%R11,4),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
LEA 0x5(%RSI),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %ESI,%XMM12	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM8,%YMM12,%YMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM12,%YMM5,%YMM13	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %R11D,%YMM14	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x20,%YMM14,%YMM13,%YMM13	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM9,%YMM12,%YMM12	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2Q %YMM12,%YMM7,%YMM13	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPSUBD %YMM2,%YMM13,%YMM12	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM13,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RAX,%YMM12,4),%YMM13{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTSS2SD %XMM11,%XMM11,%XMM11	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VCVTPS2PD %YMM13,%ZMM12	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VBROADCASTSD %XMM11,%ZMM11	1	0	0	0	0	1	0	0	0	3	1	scal (12.5%)
VMULPD %ZMM11,%ZMM12,%ZMM11	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM10,%ZMM10	1	0.50	0	0	0	0.50	0	0	0	3	0.50	vect (100.0%)
ADD $0x2,%R12	1	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x2,%R13D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %R10D,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %R10D,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMP %R12,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 405b90 <main+0x1850>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code