OV - attention-avx512 - Loop 30

	Loop Id: 30	Module: attention-avx512	Source: attention.cpp:43-284 [...]	Coverage: 0.40%

0x406a80 MOV	0x120(%RSP),%RAX

0x406a88 MOV	0x30(%RSP),%RCX

0x406a8d VMOVSS	%XMM19,(%RAX,%RCX,4)

0x406a94 MOV	0x128(%RSP),%RAX

0x406a9c MOV	0x70(%RSP),%RDI

0x406aa1 ADD	%RAX,%RDI

0x406aa4 MOV	0x58(%RSP),%RDX

0x406aa9 INC	%RDX

0x406aac ADD	%RAX,%R14

0x406aaf MOV	0x50(%RSP),%RSI

0x406ab4 ADD	%RAX,%RSI

0x406ab7 MOV	0xb0(%RSP),%RAX

0x406abf CMP	%RAX,%RCX

0x406ac2 JE	406a40

0x406ac8 LEA	0x1(%R8),%R9

0x406acc VMOVAPS	%XMM21,%XMM16

0x406ad2 TEST	$-0x8,%R9

0x406ad9 JE	406b24

0x406adb MOV	%RDX,%RAX

0x406ade SHR	$0x3,%RAX

0x406ae2 MOV	%RDI,%RCX

0x406ae5 VMOVAPS	%XMM21,%XMM16

0x406aeb NOPL	(%RAX,%RAX,1)

  (34) 0x406af0 VMAXSS	-0x1c(%RCX),%XMM16,%XMM0

  (34) 0x406af7 VMAXSS	-0x18(%RCX),%XMM0,%XMM0

  (34) 0x406afc VMAXSS	-0x14(%RCX),%XMM0,%XMM0

  (34) 0x406b01 VMAXSS	-0x10(%RCX),%XMM0,%XMM0

  (34) 0x406b06 VMAXSS	-0xc(%RCX),%XMM0,%XMM0

  (34) 0x406b0b VMAXSS	-0x8(%RCX),%XMM0,%XMM0

  (34) 0x406b10 VMAXSS	-0x4(%RCX),%XMM0,%XMM0

  (34) 0x406b15 VMAXSS	(%RCX),%XMM0,%XMM16

  (34) 0x406b1b ADD	$0x20,%RCX

  (34) 0x406b1f DEC	%RAX

  (34) 0x406b22 JNE	406af0

0x406b24 MOV	%R9,%RAX

0x406b27 AND	$-0x8,%RAX

0x406b2b CMP	%R9,%RAX

0x406b2e JE	406b3f

  (33) 0x406b30 VMAXSS	(%R14,%RAX,4),%XMM16,%XMM16

  (33) 0x406b37 INC	%RAX

  (33) 0x406b3a CMP	%RAX,%RDX

  (33) 0x406b3d JNE	406b30

0x406b3f MOV	%RDI,0x70(%RSP)

0x406b44 MOV	%RSI,0x50(%RSP)

0x406b49 MOV	%RDX,0x58(%RSP)

0x406b4e MOV	%R9,%RSI

0x406b51 AND	$-0x10,%RSI

0x406b55 VPBROADCASTQ	%RSI,%ZMM17

0x406b5b MOV	%R8,0x30(%RSP)

0x406b60 MOV	%R9,0x40(%RSP)

0x406b65 MOV	%RSI,0x38(%RSP)

0x406b6a VPBROADCASTQ	%R9,%ZMM19

0x406b70 JE	406c00

0x406b76 LEA	-0x1(%RSI),%RBX

0x406b7a MOV	0x98(%RSP),%RDI

0x406b82 IMUL	%R8,%RDI

0x406b86 VBROADCASTSS	%XMM16,%ZMM20

0x406b8c VXORPS	%XMM18,%XMM18,%XMM18

0x406b92 XOR	%R12D,%R12D

0x406b95 MOV	$0x408600,%RSI

0x406b9c NOPL	(%RAX)

  (32) 0x406ba0 VMOVUPS	(%R14,%R12,4),%ZMM0

  (32) 0x406ba7 VSUBPS	%ZMM20,%ZMM0,%ZMM0

  (32) 0x406bad CALL	%RSI

  (32) 0x406baf VADDPS	%ZMM18,%ZMM0,%ZMM18

  (32) 0x406bb5 ADD	$0x10,%R12

  (32) 0x406bb9 CMP	%RBX,%R12

  (32) 0x406bbc JLE	406ba0

0x406bbe VPCMPEQQ	%ZMM17,%ZMM19,%K0

0x406bc4 KMOVD	%K0,%ECX

0x406bc8 MOV	0x38(%RSP),%RSI

0x406bcd MOV	%RSI,%RAX

0x406bd0 TEST	$0x1,%CL

0x406bd3 MOV	0xc0(%RSP),%R12

0x406bdb MOV	0xe0(%RSP),%RBX

0x406be3 JE	406c1a

0x406be5 JMP	406c6e

0x406c00 MOV	0x98(%RSP),%RDI

0x406c08 IMUL	%R8,%RDI

0x406c0c VBROADCASTSS	%XMM16,%ZMM20

0x406c12 VXORPS	%XMM18,%XMM18,%XMM18

0x406c18 XOR	%EAX,%EAX

0x406c1a VPBROADCASTQ	%RAX,%ZMM0

0x406c20 VPSUBQ	%ZMM0,%ZMM19,%ZMM1

0x406c26 VPSUBQ	%ZMM0,%ZMM19,%ZMM0

0x406c2c VPCMPNLEUQ	%ZMM22,%ZMM0,%K0

0x406c33 VPCMPNLEUQ	%ZMM23,%ZMM1,%K1

0x406c3a KUNPCKBW	%K0,%K1,%K1

0x406c3e KMOVW	%K1,0x28(%RSP)

0x406c44 ADD	%RAX,%RDI

0x406c47 MOV	0xa0(%RSP),%RAX

0x406c4f VMOVUPS	(%RAX,%RDI,4),%ZMM0{%K1}{z}

0x406c56 VSUBPS	%ZMM20,%ZMM0,%ZMM1

0x406c5c CALL	4086a0 <__svml_expf16_mask_z0>

0x406c62 KMOVW	0x28(%RSP),%K1

0x406c68 VADDPS	%ZMM0,%ZMM18,%ZMM18{%K1}

0x406c6e VEXTRACTF64X4	$0x1,%ZMM18,%YMM0

0x406c75 VADDPS	%ZMM0,%ZMM18,%ZMM0

0x406c7b VMOVAPS	%XMM0,%XMM1

0x406c7f VEXTRACTF128	$0x1,%YMM0,%XMM0

0x406c85 VADDPS	%XMM0,%XMM1,%XMM0

0x406c89 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x406c8e VADDPS	%XMM1,%XMM0,%XMM0

0x406c92 VMOVSHDUP	%XMM0,%XMM1

0x406c96 VADDSS	%XMM1,%XMM0,%XMM19

0x406c9c VDIVSS	%XMM19,%XMM24,%XMM1

0x406ca2 TEST	%RSI,%RSI

0x406ca5 JE	406d80

0x406cab LEA	-0x1(%RSI),%RBX

0x406caf MOV	0x98(%RSP),%RAX

0x406cb7 IMUL	0x30(%RSP),%RAX

0x406cbd MOV	%RAX,0x28(%RSP)

0x406cc2 VBROADCASTSS	%XMM16,%ZMM18

0x406cc8 VBROADCASTSS	%XMM1,%ZMM16

0x406cce XOR	%R12D,%R12D

0x406cd1 MOV	$0x408600,%RSI

0x406cd8 MOV	0x50(%RSP),%RDI

0x406cdd NOPL	(%RAX)

  (31) 0x406ce0 VMOVUPS	(%R14,%R12,4),%ZMM0

  (31) 0x406ce7 VSUBPS	%ZMM18,%ZMM0,%ZMM0

  (31) 0x406ced CALL	%RSI

  (31) 0x406cef VMULPS	%ZMM16,%ZMM0,%ZMM0

  (31) 0x406cf5 VMOVUPS	%ZMM0,(%RDI,%R12,4)

  (31) 0x406cfc ADD	$0x10,%R12

  (31) 0x406d00 CMP	%RBX,%R12

  (31) 0x406d03 JLE	406ce0

0x406d05 MOV	0x40(%RSP),%R8

0x406d0a VPBROADCASTQ	%R8,%ZMM0

0x406d10 VPCMPEQQ	%ZMM17,%ZMM0,%K0

0x406d16 KMOVD	%K0,%EAX

0x406d1a TEST	$0x1,%AL

0x406d1c MOV	0xc0(%RSP),%R12

0x406d24 MOV	0xe0(%RSP),%RBX

0x406d2c MOV	0x38(%RSP),%RAX

0x406d31 MOV	0x28(%RSP),%RSI

0x406d36 JE	406da7

0x406d38 CMP	0x98(%RSP),%R8

0x406d40 JAE	406a80

0x406d46 JMP	406e16

0x406d80 MOV	0x40(%RSP),%RAX

0x406d85 VPBROADCASTQ	%RAX,%ZMM0

0x406d8b MOV	0x98(%RSP),%RSI

0x406d93 IMUL	0x30(%RSP),%RSI

0x406d99 VBROADCASTSS	%XMM16,%ZMM18

0x406d9f VBROADCASTSS	%XMM1,%ZMM16

0x406da5 XOR	%EAX,%EAX

0x406da7 VPBROADCASTQ	%RAX,%ZMM1

0x406dad VPSUBQ	%ZMM1,%ZMM0,%ZMM2

0x406db3 VPSUBQ	%ZMM1,%ZMM0,%ZMM0

0x406db9 VPCMPNLEUQ	%ZMM22,%ZMM0,%K0

0x406dc0 VPCMPNLEUQ	%ZMM23,%ZMM2,%K1

0x406dc7 KUNPCKBW	%K0,%K1,%K1

0x406dcb KMOVW	%K1,0x38(%RSP)

0x406dd1 ADD	%RAX,%RSI

0x406dd4 MOV	0xa0(%RSP),%RAX

0x406ddc VMOVUPS	(%RAX,%RSI,4),%ZMM0{%K1}{z}

0x406de3 VSUBPS	%ZMM18,%ZMM0,%ZMM1

0x406de9 CALL	4086a0 <__svml_expf16_mask_z0>

0x406def MOV	0x40(%RSP),%R8

0x406df4 VMULPS	%ZMM16,%ZMM0,%ZMM0

0x406dfa KMOVW	0x38(%RSP),%K1

0x406e00 VMOVUPS	%ZMM0,(%R13,%RSI,4){%K1}

0x406e08 CMP	0x98(%RSP),%R8

0x406e10 JAE	406a80

0x406e16 MOV	0x20(%RSP),%RAX

0x406e1b MOV	0x30(%RSP),%RCX

0x406e20 SUB	%ECX,%EAX

0x406e22 MOV	0x48(%RSP),%RDI

0x406e27 IMUL	%RCX,%RDI

0x406e2b MOV	$0x100000000,%RCX

0x406e35 ADD	%RCX,%RDI

0x406e38 SAR	$0x1e,%RDI

0x406e3c ADD	%R13,%RDI

0x406e3f LEA	0x4(,%RAX,4),%RDX

0x406e47 XOR	%ESI,%ESI

0x406e49 VMOVSS	%XMM19,0x38(%RSP)

0x406e51 VZEROUPPER

0x406e54 CALL	409640 <_intel_fast_memset>

0x406e59 VMOVSS	0x38(%RSP),%XMM19

0x406e61 MOV	0x40(%RSP),%R8

0x406e66 VMOVSS	0x82e4(%RIP),%XMM24

0x406e70 VMOVDQU64	0x84c6(%RIP),%ZMM23

0x406e7a VMOVDQU64	0x847c(%RIP),%ZMM22

0x406e84 VMOVSS	0x82c2(%RIP),%XMM21

0x406e8e JMP	406a80

/home/eoseret/llm-attention/attention.cpp: 43 - 284

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

[...]

98:    if (argc < 4) {

[...]

284:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.66
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.34
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-61,attention.cpp:98-98,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	26.50
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	25.92
CQA cycles if fully vectorized	19.80
Front-end cycles	26.50
P0 cycles	13.50
P1 cycles	13.40
P2 cycles	13.67
P3 cycles	13.67
P4 cycles	7.50
P5 cycles	20.00
P6 cycles	13.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	13.60
P11 cycles	13.67
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	155.00
Nb uops	159.00
Nb loads	41.00
Nb stores	12.00
Nb stack references	16.00
FLOP/cycle	3.40
Nb FLOP add-sub	73.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.91
Bytes prefetched	0.00
Bytes loaded	528.00
Bytes stored	132.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	43.84
Vectorization ratio load	28.57
Vectorization ratio store	10.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	76.92
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	44.44
Vector-efficiency ratio all	37.41
Vector-efficiency ratio load	36.16
Vector-efficiency ratio store	20.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	67.79
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	29.51

Metric	Value
CQA speedup if no scalar integer	1.66
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.34
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-61,attention.cpp:98-98,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	26.50
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	25.92
CQA cycles if fully vectorized	19.80
Front-end cycles	26.50
P0 cycles	13.50
P1 cycles	13.40
P2 cycles	13.67
P3 cycles	13.67
P4 cycles	7.50
P5 cycles	20.00
P6 cycles	13.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	13.60
P11 cycles	13.67
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	155.00
Nb uops	159.00
Nb loads	41.00
Nb stores	12.00
Nb stack references	16.00
FLOP/cycle	3.40
Nb FLOP add-sub	73.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.91
Bytes prefetched	0.00
Bytes loaded	528.00
Bytes stored	132.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	43.84
Vectorization ratio load	28.57
Vectorization ratio store	10.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	76.92
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	44.44
Vector-efficiency ratio all	37.41
Vector-efficiency ratio load	36.16
Vector-efficiency ratio store	20.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	67.79
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	29.51

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,98,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52-61,98,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 72 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.50 to 16.00 cycles (1.66x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 37% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 26.50 to 19.80 cycles (1.34x speedup).

Details

43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
10% of SSE/AVX stores are used in vector version.
76% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
44% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_expf16_mask_z0: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 5 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

73: addition or subtraction
16: multiply
1: divide

The binary loop is loading 528 bytes (132 single precision FP elements). The binary loop is storing 132 bytes (33 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	155
nb uops	159
loop length	834
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	1
used zmm registers	10
nb stack references	16
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.50 cycles
front end	26.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.50	13.40	13.67	13.67	7.50	20.00	13.50	7.50	7.50	7.50	13.60	13.67
cycles	13.50	13.40	13.67	13.67	7.50	20.00	13.50	7.50	7.50	7.50	13.60	13.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	26.50
Dispatch	20.00
DIV/SQRT	3.00
Overall L1	26.50

Vectorization ratios

INT

all	31%
load	22%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	59%
load	40%
store	33%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	60%

INT+FP

all	43%
load	28%
store	10%
mul	100%
add-sub	76%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	44%

Vector efficiency ratios

INT

all	38%
load	31%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	70%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	36%
load	43%
store	37%
mul	100%
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

INT+FP

all	37%
load	36%
store	20%
mul	100%
add-sub	67%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	29%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 26.50 cycles. At this rate:

10% of peak load performance is reached (19.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.98 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 26.50 to 20.00 cycles (1.32x speedup).

ASM code

In the binary file, the address of the loop is: 406ac8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x120(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM19,(%RAX,%RCX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x128(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x50(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xb0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 406a40 <main+0x2700>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
TEST $-0x8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 406b24 <main+0x27e4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 406b3f <main+0x27ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %RSI,%ZMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JE 406c00 <main+0x28c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RSI),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x98(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x408600,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %ZMM17,%ZMM19,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0xc0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe0(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 406c1a <main+0x28da>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 406c6e <main+0x292e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x98(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM0,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM1,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xa0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RDI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM20,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 4086a0 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
KMOVW 0x28(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %ZMM0,%ZMM18,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPS %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VDIVSS %XMM19,%XMM24,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 406d80 <main+0x2a40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RSI),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x98(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %RAX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x408600,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %R8,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %ZMM17,%ZMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0xc0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe0(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 406da7 <main+0x2a67>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0x98(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 406a80 <main+0x2740>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 406e16 <main+0x2ad6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x98(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RSI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM2,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xa0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RSI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM18,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 4086a0 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x40(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPS %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVW 0x38(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %ZMM0,(%R13,%RSI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP 0x98(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 406a80 <main+0x2740>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x48(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV $0x100000000,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAR $0x1e,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS %XMM19,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 409640 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x38(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x40(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x82e4(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVDQU64 0x84c6(%RIP),%ZMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVDQU64 0x847c(%RIP),%ZMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVSS 0x82c2(%RIP),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 406a80 <main+0x2740>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,98,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52-61,98,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
10% of SSE/AVX stores are used in vector version.
76% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
44% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

__svml_expf16_mask_z0: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

73: addition or subtraction
16: multiply
1: divide

The binary loop is loading 528 bytes (132 single precision FP elements). The binary loop is storing 132 bytes (33 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	155
nb uops	159
loop length	834
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	1
used zmm registers	10
nb stack references	16
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.50 cycles
front end	26.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.50	13.40	13.67	13.67	7.50	20.00	13.50	7.50	7.50	7.50	13.60	13.67
cycles	13.50	13.40	13.67	13.67	7.50	20.00	13.50	7.50	7.50	7.50	13.60	13.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	26.50
Dispatch	20.00
DIV/SQRT	3.00
Overall L1	26.50

Vectorization ratios

INT

all	31%
load	22%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	59%
load	40%
store	33%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	60%

INT+FP

all	43%
load	28%
store	10%
mul	100%
add-sub	76%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	44%

Vector efficiency ratios

INT

all	38%
load	31%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	70%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	36%
load	43%
store	37%
mul	100%
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

INT+FP

all	37%
load	36%
store	20%
mul	100%
add-sub	67%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	29%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 26.50 cycles. At this rate:

10% of peak load performance is reached (19.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.98 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 406ac8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x120(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM19,(%RAX,%RCX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x128(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x50(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xb0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 406a40 <main+0x2700>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
TEST $-0x8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 406b24 <main+0x27e4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 406b3f <main+0x27ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %RSI,%ZMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JE 406c00 <main+0x28c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RSI),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x98(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x408600,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %ZMM17,%ZMM19,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0xc0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe0(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 406c1a <main+0x28da>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 406c6e <main+0x292e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x98(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM0,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM1,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xa0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RDI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM20,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 4086a0 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
KMOVW 0x28(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %ZMM0,%ZMM18,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPS %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VDIVSS %XMM19,%XMM24,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 406d80 <main+0x2a40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RSI),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x98(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %RAX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x408600,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %R8,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %ZMM17,%ZMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0xc0(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe0(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 406da7 <main+0x2a67>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0x98(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 406a80 <main+0x2740>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 406e16 <main+0x2ad6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x98(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RSI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM2,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xa0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RSI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM18,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 4086a0 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x40(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPS %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVW 0x38(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %ZMM0,(%R13,%RSI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP 0x98(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 406a80 <main+0x2740>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x48(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV $0x100000000,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAR $0x1e,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS %XMM19,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 409640 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x38(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x40(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x82e4(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVDQU64 0x84c6(%RIP),%ZMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVDQU64 0x847c(%RIP),%ZMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVSS 0x82c2(%RIP),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 406a80 <main+0x2740>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code