OV - attention-avx512 - Loop 51

	Loop Id: 51	Module: attention-avx512	Source: attention.cpp:30-31	Coverage: 8.03%

0x405090 MOV	%R10D,%R14D

0x405093 VMOVSS	(%R15,%R14,4),%XMM15    [2]

0x405099 VCVTSS2SD	%XMM15,%XMM15,%XMM15

0x40509e LEA	-0x7(%RSI),%R14D

0x4050a2 VMOVSS	(%R13,%R14,4),%XMM16    [1]

0x4050aa VCVTSS2SD	%XMM16,%XMM16,%XMM16

0x4050b0 VFMADD231SD	%XMM16,%XMM15,%XMM14

0x4050b6 LEA	-0x6(%RSI),%R14D

0x4050ba VMOVSS	(%R13,%R14,4),%XMM16    [1]

0x4050c2 VCVTSS2SD	%XMM16,%XMM16,%XMM16

0x4050c8 VFMADD231SD	%XMM16,%XMM15,%XMM13

0x4050ce LEA	-0x5(%RSI),%R14D

0x4050d2 VMOVSS	(%R13,%R14,4),%XMM16    [1]

0x4050da VCVTSS2SD	%XMM16,%XMM16,%XMM16

0x4050e0 LEA	-0x4(%RSI),%R14D

0x4050e4 VMOVSS	(%R13,%R14,4),%XMM17    [1]

0x4050ec VCVTSS2SD	%XMM17,%XMM17,%XMM17

0x4050f2 VFMADD231SD	%XMM16,%XMM15,%XMM12

0x4050f8 VFMADD231SD	%XMM17,%XMM15,%XMM11

0x4050fe LEA	-0x3(%RSI),%R14D

0x405102 VMOVSS	(%R13,%R14,4),%XMM16    [1]

0x40510a VCVTSS2SD	%XMM16,%XMM16,%XMM16

0x405110 VFMADD231SD	%XMM16,%XMM15,%XMM10

0x405116 LEA	-0x2(%RSI),%R14D

0x40511a VMOVSS	(%R13,%R14,4),%XMM16    [1]

0x405122 VCVTSS2SD	%XMM16,%XMM16,%XMM16

0x405128 VFMADD231SD	%XMM16,%XMM15,%XMM9

0x40512e LEA	-0x1(%RSI),%R14D

0x405132 VMOVSS	(%R13,%R14,4),%XMM16    [1]

0x40513a VCVTSS2SD	%XMM16,%XMM16,%XMM16

0x405140 VFMADD231SD	%XMM16,%XMM15,%XMM8

0x405146 MOV	%ESI,%R14D

0x405149 VMOVSS	(%R13,%R14,4),%XMM16    [1]

0x405151 VCVTSS2SD	%XMM16,%XMM16,%XMM16

0x405157 VFMADD231SD	%XMM16,%XMM15,%XMM7

0x40515d ADD	%R8D,%ESI

0x405160 INC	%R10D

0x405163 DEC	%RDI

0x405166 JNE	405090

/home/eoseret/llm-attention/attention.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P5,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	0.78
Front-end cycles	7.83
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	0.00
P5 cycles	9.00
P6 cycles	5.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.00
P11 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	47.00
Nb loads	9.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.78
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.10
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P5,
Function	main
Source	attention.cpp:30-31
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	0.78
Front-end cycles	7.83
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	0.00
P5 cycles	9.00
P6 cycles	5.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.00
P11 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	47.00
Nb loads	9.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.78
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.10
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.00 to 0.78 cycles (11.52x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.00 to 8.50 cycles (1.06x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSS2SD: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.44 FP operations per loaded or stored byte.

General properties

nb instructions	39
nb uops	47
loop length	220
used x86 registers	7
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.83 cycles
front end	7.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.50	8.50	3.00	3.00	0.00	9.00	5.00	0.00	0.00	0.00	5.00	3.00
cycles	8.50	8.50	3.00	3.00	0.00	9.00	5.00	0.00	0.00	0.00	5.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	7.83
Dispatch	9.00
Data deps.	4.00
Overall L1	9.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405090

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R10D,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R15,%R14,4),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM15,%XMM15,%XMM15	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
LEA -0x7(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x6(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM13	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x5(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
LEA -0x4(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM17	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM17,%XMM17,%XMM17	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM17,%XMM15,%XMM11	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x3(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x2(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x1(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R8D,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
INC %R10D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
DEC %RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 405090 <main+0x1290>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:30-31
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:30-31.

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSS2SD: 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 9 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.44 FP operations per loaded or stored byte.

General properties

nb instructions	39
nb uops	47
loop length	220
used x86 registers	7
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.83 cycles
front end	7.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.50	8.50	3.00	3.00	0.00	9.00	5.00	0.00	0.00	0.00	5.00	3.00
cycles	8.50	8.50	3.00	3.00	0.00	9.00	5.00	0.00	0.00	0.00	5.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	7.83
Dispatch	9.00
Data deps.	4.00
Overall L1	9.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

2% of peak load performance is reached (4.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405090

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R10D,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R15,%R14,4),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM15,%XMM15,%XMM15	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
LEA -0x7(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x6(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM13	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x5(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
LEA -0x4(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM17	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM17,%XMM17,%XMM17	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM17,%XMM15,%XMM11	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x3(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x2(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x1(%RSI),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R14,4),%XMM16	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM16	2	0.50	0.50	0	0	1	0	0	0	4-5	1	scal (6.3%)
VFMADD231SD %XMM16,%XMM15,%XMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R8D,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
INC %R10D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
DEC %RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 405090 <main+0x1290>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code