OV - attention-avx512 - Loop 48

	Loop Id: 48	Module: attention-avx512	Source: attention.cpp:26-193 [...]	Coverage: 0.11%

0x404fc0 MOV	-0x110(%RBP),%RAX

0x404fc7 CMP	-0x158(%RBP),%RAX

0x404fce LEA	0x1(%RAX),%RAX

0x404fd2 JE	4056c0

0x404fd8 MOV	%RAX,-0x110(%RBP)

0x404fdf MOV	-0x48(%RBP),%RAX

0x404fe3 ADD	%R8D,%EAX

0x404fe6 MOV	%RAX,-0xb0(%RBP)

0x404fed MOVL	$0,-0x40(%RBP)

0x404ff4 MOVQ	$0,-0x50(%RBP)

0x404ffc JMP	40501c

0x405000 MOV	-0x40(%RBP),%EAX

0x405003 ADD	-0x48(%RBP),%EAX

0x405006 MOV	%EAX,-0x40(%RBP)

0x405009 MOV	-0x50(%RBP),%RAX

0x40500d CMP	-0x120(%RBP),%EAX

0x405013 LEA	0x1(%RAX),%EAX

0x405016 MOV	%RAX,-0x50(%RBP)

0x40501a JE	404fc0

0x40501c MOV	%R14D,%ECX

0x40501f TEST	%R10,%R10

0x405022 JE	4051ec

0x405028 MOV	-0x50(%RBP),%RAX

0x40502c IMUL	-0x48(%RBP),%EAX

0x405030 MOV	$0x7,%R9D

0x405036 XOR	%R11D,%R11D

0x405039 MOV	-0xd8(%RBP),%R13

0x405040 MOV	-0x48(%RBP),%R8

0x405044 NOPW	%CS:(%RAX,%RAX,1)

  (52) 0x405050 LEA	(,%R11,8),%EDX

  (52) 0x405058 VXORPS	%XMM7,%XMM7,%XMM7

  (52) 0x40505c MOV	-0x40(%RBP),%R10D

  (52) 0x405060 MOV	%R9D,%ESI

  (52) 0x405063 MOV	-0x70(%RBP),%RDI

  (52) 0x405067 VXORPS	%XMM8,%XMM8,%XMM8

  (52) 0x40506c VXORPS	%XMM9,%XMM9,%XMM9

  (52) 0x405071 VXORPS	%XMM10,%XMM10,%XMM10

  (52) 0x405076 VXORPS	%XMM11,%XMM11,%XMM11

  (52) 0x40507b VXORPS	%XMM12,%XMM12,%XMM12

  (52) 0x405080 VXORPS	%XMM13,%XMM13,%XMM13

  (52) 0x405085 VXORPS	%XMM14,%XMM14,%XMM14

  (52) 0x40508a NOPW	(%RAX,%RAX,1)

    (51) 0x405090 MOV	%R10D,%R14D

    (51) 0x405093 VMOVSS	(%R15,%R14,4),%XMM15

    (51) 0x405099 VCVTSS2SD	%XMM15,%XMM15,%XMM15

    (51) 0x40509e LEA	-0x7(%RSI),%R14D

    (51) 0x4050a2 VMOVSS	(%R13,%R14,4),%XMM16

    (51) 0x4050aa VCVTSS2SD	%XMM16,%XMM16,%XMM16

    (51) 0x4050b0 VFMADD231SD	%XMM16,%XMM15,%XMM14

    (51) 0x4050b6 LEA	-0x6(%RSI),%R14D

    (51) 0x4050ba VMOVSS	(%R13,%R14,4),%XMM16

    (51) 0x4050c2 VCVTSS2SD	%XMM16,%XMM16,%XMM16

    (51) 0x4050c8 VFMADD231SD	%XMM16,%XMM15,%XMM13

    (51) 0x4050ce LEA	-0x5(%RSI),%R14D

    (51) 0x4050d2 VMOVSS	(%R13,%R14,4),%XMM16

    (51) 0x4050da VCVTSS2SD	%XMM16,%XMM16,%XMM16

    (51) 0x4050e0 LEA	-0x4(%RSI),%R14D

    (51) 0x4050e4 VMOVSS	(%R13,%R14,4),%XMM17

    (51) 0x4050ec VCVTSS2SD	%XMM17,%XMM17,%XMM17

    (51) 0x4050f2 VFMADD231SD	%XMM16,%XMM15,%XMM12

    (51) 0x4050f8 VFMADD231SD	%XMM17,%XMM15,%XMM11

    (51) 0x4050fe LEA	-0x3(%RSI),%R14D

    (51) 0x405102 VMOVSS	(%R13,%R14,4),%XMM16

    (51) 0x40510a VCVTSS2SD	%XMM16,%XMM16,%XMM16

    (51) 0x405110 VFMADD231SD	%XMM16,%XMM15,%XMM10

    (51) 0x405116 LEA	-0x2(%RSI),%R14D

    (51) 0x40511a VMOVSS	(%R13,%R14,4),%XMM16

    (51) 0x405122 VCVTSS2SD	%XMM16,%XMM16,%XMM16

    (51) 0x405128 VFMADD231SD	%XMM16,%XMM15,%XMM9

    (51) 0x40512e LEA	-0x1(%RSI),%R14D

    (51) 0x405132 VMOVSS	(%R13,%R14,4),%XMM16

    (51) 0x40513a VCVTSS2SD	%XMM16,%XMM16,%XMM16

    (51) 0x405140 VFMADD231SD	%XMM16,%XMM15,%XMM8

    (51) 0x405146 MOV	%ESI,%R14D

    (51) 0x405149 VMOVSS	(%R13,%R14,4),%XMM16

    (51) 0x405151 VCVTSS2SD	%XMM16,%XMM16,%XMM16

    (51) 0x405157 VFMADD231SD	%XMM16,%XMM15,%XMM7

    (51) 0x40515d ADD	%R8D,%ESI

    (51) 0x405160 INC	%R10D

    (51) 0x405163 DEC	%RDI

    (51) 0x405166 JNE	405090

  (52) 0x40516c VCVTSD2SS	%XMM14,%XMM14,%XMM14

  (52) 0x405171 LEA	(%RAX,%RDX,1),%ESI

  (52) 0x405174 VMOVSS	%XMM14,(%RBX,%RSI,4)

  (52) 0x405179 VCVTSD2SS	%XMM13,%XMM13,%XMM13

  (52) 0x40517e LEA	0x1(%RAX,%RDX,1),%ESI

  (52) 0x405182 VMOVSS	%XMM13,(%RBX,%RSI,4)

  (52) 0x405187 VCVTSD2SS	%XMM12,%XMM12,%XMM12

  (52) 0x40518c LEA	0x2(%RAX,%RDX,1),%ESI

  (52) 0x405190 VMOVSS	%XMM12,(%RBX,%RSI,4)

  (52) 0x405195 VCVTSD2SS	%XMM11,%XMM11,%XMM11

  (52) 0x40519a LEA	0x3(%RAX,%RDX,1),%ESI

  (52) 0x40519e VMOVSS	%XMM11,(%RBX,%RSI,4)

  (52) 0x4051a3 VCVTSD2SS	%XMM10,%XMM10,%XMM10

  (52) 0x4051a8 LEA	0x4(%RAX,%RDX,1),%ESI

  (52) 0x4051ac VMOVSS	%XMM10,(%RBX,%RSI,4)

  (52) 0x4051b1 VCVTSD2SS	%XMM9,%XMM9,%XMM9

  (52) 0x4051b6 LEA	0x5(%RAX,%RDX,1),%ESI

  (52) 0x4051ba VMOVSS	%XMM9,(%RBX,%RSI,4)

  (52) 0x4051bf VCVTSD2SS	%XMM8,%XMM8,%XMM8

  (52) 0x4051c4 LEA	0x6(%RAX,%RDX,1),%ESI

  (52) 0x4051c8 VMOVSS	%XMM8,(%RBX,%RSI,4)

  (52) 0x4051cd VCVTSD2SS	%XMM7,%XMM7,%XMM7

  (52) 0x4051d1 LEA	0x7(%RAX,%RDX,1),%EDX

  (52) 0x4051d5 VMOVSS	%XMM7,(%RBX,%RDX,4)

  (52) 0x4051da ADD	$0x8,%R9D

  (52) 0x4051de CMP	-0x60(%RBP),%R11

  (52) 0x4051e2 LEA	0x1(%R11),%R11

  (52) 0x4051e6 JNE	405050

0x4051ec MOV	-0xc8(%RBP),%RAX

0x4051f3 CMP	-0x70(%RBP),%EAX

0x4051f6 MOV	-0x178(%RBP),%R13

0x4051fd MOV	-0x30(%RBP),%R10

0x405201 MOV	%ECX,%R14D

0x405204 MOV	-0x38(%RBP),%R8

0x405208 JAE	405000

/home/eoseret/llm-attention/attention.cpp: 26 - 193

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

193:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-27,attention.cpp:31-31,attention.cpp:193-193
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.48
Front-end cycles	6.00
P0 cycles	2.60
P1 cycles	2.60
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	3.00
P5 cycles	2.60
P6 cycles	2.60
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	2.60
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	16.00
Nb stores	6.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.67
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.72
Vector-efficiency ratio load	11.61
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.04

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-27,attention.cpp:31-31,attention.cpp:193-193
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.48
Front-end cycles	6.00
P0 cycles	2.60
P1 cycles	2.60
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	3.00
P5 cycles	2.60
P6 cycles	2.60
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	2.60
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	16.00
Nb stores	6.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.67
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.72
Vector-efficiency ratio load	11.61
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.04

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-193
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,193.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26-27,31,193.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.48 cycles (12.52x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 108 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	36
nb uops	36
loop length	176
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.60	2.60	5.33	5.33	3.00	2.60	2.60	3.00	3.00	3.00	2.60	5.33
cycles	2.60	2.60	5.33	5.33	3.00	2.60	2.60	3.00	3.00	3.00	2.60	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	5.33
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

9% of peak load performance is reached (18.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 5.33 cycles (1.13x speedup).

ASM code

In the binary file, the address of the loop is: 405000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x110(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0x158(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RAX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4056c0 <main+0x18c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 40501c <main+0x121c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x40(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD -0x48(%RBP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %EAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0x120(%RBP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
LEA 0x1(%RAX),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 404fc0 <main+0x11c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4051ec <main+0x13ec>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL -0x48(%RBP),%EAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0xd8(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0x70(%RBP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV -0x178(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 405000 <main+0x1200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:26-193
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,193.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26-27,31,193.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 108 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	36
nb uops	36
loop length	176
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.60	2.60	5.33	5.33	3.00	2.60	2.60	3.00	3.00	3.00	2.60	5.33
cycles	2.60	2.60	5.33	5.33	3.00	2.60	2.60	3.00	3.00	3.00	2.60	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	5.33
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

9% of peak load performance is reached (18.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 405000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x110(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0x158(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RAX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 4056c0 <main+0x18c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 40501c <main+0x121c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV -0x40(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD -0x48(%RBP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %EAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0x120(%RBP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
LEA 0x1(%RAX),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 404fc0 <main+0x11c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4051ec <main+0x13ec>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL -0x48(%RBP),%EAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0xd8(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xc8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0x70(%RBP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV -0x178(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x30(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JAE 405000 <main+0x1200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code