OV - attention-avx512 - Loop 27

	Loop Id: 27	Module: attention-avx512	Source: attention.cpp:43-284 [...]	Coverage: 0.42%

0x406d00 MOV	-0x1a0(%RBP),%RAX

0x406d07 MOV	-0x40(%RBP),%RCX

0x406d0b VMOVSS	%XMM11,(%RAX,%RCX,4)

0x406d10 MOV	-0x108(%RBP),%RAX

0x406d17 MOV	-0x58(%RBP),%RDI

0x406d1b ADD	%RAX,%RDI

0x406d1e MOV	-0x90(%RBP),%RDX

0x406d25 INC	%RDX

0x406d28 ADD	%RAX,%RSI

0x406d2b MOV	%RSI,-0x30(%RBP)

0x406d2f MOV	-0xa0(%RBP),%RSI

0x406d36 ADD	%RAX,%RSI

0x406d39 MOV	-0x180(%RBP),%RAX

0x406d40 CMP	%RAX,%RCX

0x406d43 JE	406cc0

0x406d49 LEA	0x1(%R8),%R9

0x406d4d VMOVAPS	%XMM13,%XMM8

0x406d52 TEST	$-0x8,%R9

0x406d59 JE	406da0

0x406d5b MOV	%RDX,%RAX

0x406d5e SHR	$0x3,%RAX

0x406d62 MOV	%RDI,%RCX

0x406d65 VMOVAPS	%XMM13,%XMM8

0x406d6a NOPW	(%RAX,%RAX,1)

  (31) 0x406d70 VMAXSS	-0x1c(%RCX),%XMM8,%XMM0

  (31) 0x406d75 VMAXSS	-0x18(%RCX),%XMM0,%XMM0

  (31) 0x406d7a VMAXSS	-0x14(%RCX),%XMM0,%XMM0

  (31) 0x406d7f VMAXSS	-0x10(%RCX),%XMM0,%XMM0

  (31) 0x406d84 VMAXSS	-0xc(%RCX),%XMM0,%XMM0

  (31) 0x406d89 VMAXSS	-0x8(%RCX),%XMM0,%XMM0

  (31) 0x406d8e VMAXSS	-0x4(%RCX),%XMM0,%XMM0

  (31) 0x406d93 VMAXSS	(%RCX),%XMM0,%XMM8

  (31) 0x406d97 ADD	$0x20,%RCX

  (31) 0x406d9b DEC	%RAX

  (31) 0x406d9e JNE	406d70

0x406da0 MOV	%R9,%R10

0x406da3 AND	$-0x8,%R10

0x406da7 CMP	%R9,%R10

0x406daa JE	406dcd

0x406dac MOV	%R10,%RAX

0x406daf MOV	-0x30(%RBP),%RCX

0x406db3 NOPW	%CS:(%RAX,%RAX,1)

  (30) 0x406dc0 VMAXSS	(%RCX,%RAX,4),%XMM8,%XMM8

  (30) 0x406dc5 INC	%RAX

  (30) 0x406dc8 CMP	%RAX,%RDX

  (30) 0x406dcb JNE	406dc0

0x406dcd MOV	%RDI,-0x58(%RBP)

0x406dd1 MOV	%RSI,-0xa0(%RBP)

0x406dd8 MOV	%RDX,-0x90(%RBP)

0x406ddf VPBROADCASTQ	%R10,%YMM9

0x406de5 TEST	%R10,%R10

0x406de8 MOV	%R8,-0x40(%RBP)

0x406dec MOV	%R9,-0x60(%RBP)

0x406df0 MOV	%R10,-0x38(%RBP)

0x406df4 VPBROADCASTQ	%R9,%YMM12

0x406dfa JE	406e80

0x406e00 MOV	%R15,%RDI

0x406e03 LEA	-0x1(%R10),%R15

0x406e07 IMUL	%R8,%RDI

0x406e0b VBROADCASTSS	%XMM8,%YMM11

0x406e10 VXORPS	%XMM10,%XMM10,%XMM10

0x406e15 XOR	%R13D,%R13D

0x406e18 MOV	-0x30(%RBP),%RSI

0x406e1c NOPL	(%RAX)

  (29) 0x406e20 VMOVUPS	(%RSI,%R13,4),%YMM0

  (29) 0x406e26 VSUBPS	%YMM11,%YMM0,%YMM0

  (29) 0x406e2b CALL	%R14

  (29) 0x406e2e VADDPS	%YMM0,%YMM10,%YMM10

  (29) 0x406e32 ADD	$0x8,%R13

  (29) 0x406e36 CMP	%R15,%R13

  (29) 0x406e39 JLE	406e20

0x406e3b VPCMPEQQ	%YMM9,%YMM12,%K0

0x406e41 KMOVD	%K0,%ECX

0x406e45 MOV	-0x38(%RBP),%RDX

0x406e49 MOV	%RDX,%RAX

0x406e4c TEST	$0x1,%CL

0x406e4f MOV	-0x100(%RBP),%R14

0x406e56 MOV	-0x160(%RBP),%R13

0x406e5d MOV	-0x148(%RBP),%R15

0x406e64 JE	406e9e

0x406e66 JMP	406ef9

0x406e80 MOV	%R15,%RDI

0x406e83 IMUL	%R8,%RDI

0x406e87 VBROADCASTSS	%XMM8,%YMM11

0x406e8c VXORPS	%XMM10,%XMM10,%XMM10

0x406e91 XOR	%EAX,%EAX

0x406e93 MOV	-0x100(%RBP),%R14

0x406e9a MOV	-0x30(%RBP),%RSI

0x406e9e VPBROADCASTQ	%RAX,%YMM0

0x406ea4 VPSUBQ	%YMM0,%YMM12,%YMM1

0x406ea8 VPSUBQ	%YMM0,%YMM12,%YMM0

0x406eac VPCMPNLEUQ	%YMM14,%YMM0,%K0

0x406eb3 VPCMPNLEUQ	%YMM15,%YMM1,%K1

0x406eba KSHIFTLB	$0x4,%K1,%K1

0x406ec0 KORB	%K1,%K0,%K1

0x406ec4 KMOVW	%K1,-0x98(%RBP)

0x406ecc ADD	%RAX,%RDI

0x406ecf VMOVUPS	(%R14,%RDI,4),%YMM0{%K1}{z}

0x406ed6 VSUBPS	%YMM11,%YMM0,%YMM0

0x406edb VPMOVM2D	%K1,%YMM1

0x406ee1 CALL	408e20 <__svml_expf8_mask_l9>

0x406ee7 MOV	-0x38(%RBP),%RDX

0x406eeb KMOVW	-0x98(%RBP),%K1

0x406ef3 VADDPS	%YMM0,%YMM10,%YMM10{%K1}

0x406ef9 VEXTRACTF128	$0x1,%YMM10,%XMM0

0x406eff VADDPS	%XMM0,%XMM10,%XMM0

0x406f03 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x406f08 VADDPS	%XMM1,%XMM0,%XMM0

0x406f0c VMOVSHDUP	%XMM0,%XMM1

0x406f10 VADDSS	%XMM1,%XMM0,%XMM11

0x406f14 VMOVSS	0x820c(%RIP),%XMM0

0x406f1c VDIVSS	%XMM11,%XMM0,%XMM1

0x406f21 TEST	%RDX,%RDX

0x406f24 JE	407000

0x406f2a MOV	%R15,%RDI

0x406f2d LEA	-0x1(%RDX),%R15

0x406f31 IMUL	-0x40(%RBP),%RDI

0x406f36 MOV	%RDI,-0x98(%RBP)

0x406f3d VBROADCASTSS	%XMM8,%YMM10

0x406f42 VBROADCASTSS	%XMM1,%YMM8

0x406f47 XOR	%R14D,%R14D

0x406f4a MOV	%RSI,%RDI

0x406f4d MOV	$0x408a40,%RSI

0x406f54 MOV	-0xa0(%RBP),%R13

0x406f5b NOPL	(%RAX,%RAX,1)

  (28) 0x406f60 VMOVUPS	(%RDI,%R14,4),%YMM0

  (28) 0x406f66 VSUBPS	%YMM10,%YMM0,%YMM0

  (28) 0x406f6b CALL	%RSI

  (28) 0x406f6d VMULPS	%YMM0,%YMM8,%YMM0

  (28) 0x406f71 VMOVUPS	%YMM0,(%R13,%R14,4)

  (28) 0x406f78 ADD	$0x8,%R14

  (28) 0x406f7c CMP	%R15,%R14

  (28) 0x406f7f JLE	406f60

0x406f81 MOV	-0x60(%RBP),%R8

0x406f85 VPBROADCASTQ	%R8,%YMM0

0x406f8b VPCMPEQQ	%YMM9,%YMM0,%K0

0x406f91 KMOVD	%K0,%EAX

0x406f95 TEST	$0x1,%AL

0x406f97 MOV	-0x148(%RBP),%R15

0x406f9e MOV	-0x160(%RBP),%R13

0x406fa5 MOV	%RDI,%RSI

0x406fa8 MOV	-0x38(%RBP),%RAX

0x406fac MOV	-0x98(%RBP),%RDI

0x406fb3 JE	40701e

0x406fb5 CMP	%R15,%R8

0x406fb8 MOV	$0x408a40,%R14

0x406fbf JAE	406d00

0x406fc5 JMP	407090

0x407000 MOV	-0x60(%RBP),%RAX

0x407004 VPBROADCASTQ	%RAX,%YMM0

0x40700a MOV	%R15,%RDI

0x40700d IMUL	-0x40(%RBP),%RDI

0x407012 VBROADCASTSS	%XMM8,%YMM10

0x407017 VBROADCASTSS	%XMM1,%YMM8

0x40701c XOR	%EAX,%EAX

0x40701e VPBROADCASTQ	%RAX,%YMM1

0x407024 VPSUBQ	%YMM1,%YMM0,%YMM2

0x407028 VPSUBQ	%YMM1,%YMM0,%YMM0

0x40702c VPCMPNLEUQ	%YMM14,%YMM0,%K0

0x407033 VPCMPNLEUQ	%YMM15,%YMM2,%K1

0x40703a KSHIFTLB	$0x4,%K1,%K1

0x407040 KORB	%K1,%K0,%K1

0x407044 KMOVW	%K1,-0x38(%RBP)

0x407049 ADD	%RAX,%RDI

0x40704c MOV	-0x100(%RBP),%RAX

0x407053 VMOVUPS	(%RAX,%RDI,4),%YMM0{%K1}{z}

0x40705a VSUBPS	%YMM10,%YMM0,%YMM0

0x40705f VPMOVM2D	%K1,%YMM1

0x407065 CALL	408e20 <__svml_expf8_mask_l9>

0x40706b MOV	-0x60(%RBP),%R8

0x40706f VMULPS	%YMM0,%YMM8,%YMM0

0x407073 KMOVW	-0x38(%RBP),%K1

0x407078 VMOVUPS	%YMM0,(%R13,%RDI,4){%K1}

0x407080 CMP	%R15,%R8

0x407083 MOV	$0x408a40,%R14

0x40708a JAE	406d00

0x407090 MOV	-0x88(%RBP),%RAX

0x407097 MOV	-0x40(%RBP),%RCX

0x40709b SUB	%ECX,%EAX

0x40709d MOV	-0xb0(%RBP),%RDI

0x4070a4 IMUL	%RCX,%RDI

0x4070a8 MOV	$0x100000000,%RCX

0x4070b2 ADD	%RCX,%RDI

0x4070b5 SAR	$0x1e,%RDI

0x4070b9 ADD	%R13,%RDI

0x4070bc LEA	0x4(,%RAX,4),%RDX

0x4070c4 XOR	%ESI,%ESI

0x4070c6 VMOVSS	%XMM11,-0x38(%RBP)

0x4070cb VZEROUPPER

0x4070ce CALL	40c5b0 <__intel_avx_rep_memset>

0x4070d3 VMOVSS	-0x38(%RBP),%XMM11

0x4070d8 MOV	-0x60(%RBP),%R8

0x4070dc MOV	-0x30(%RBP),%RSI

0x4070e0 VMOVDQU	0x8018(%RIP),%YMM15

0x4070e8 VMOVDQU	0x7ff0(%RIP),%YMM14

0x4070f0 VMOVSS	0x802c(%RIP),%XMM13

0x4070f8 JMP	406d00

/home/eoseret/llm-attention/attention.cpp: 43 - 284

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

[...]

98:    if (argc < 4) {

[...]

284:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.90
CQA speedup if FP arith vectorized	1.87
CQA speedup if fully vectorized	9.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-61,attention.cpp:98-98,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.50
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.25
CQA cycles if fully vectorized	2.86
Front-end cycles	28.50
P0 cycles	14.43
P1 cycles	14.47
P2 cycles	13.67
P3 cycles	13.67
P4 cycles	8.00
P5 cycles	19.00
P6 cycles	14.50
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	14.60
P11 cycles	13.67
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	167.00
Nb uops	171.00
Nb loads	41.00
Nb stores	13.00
Nb stack references	16.00
FLOP/cycle	1.47
Nb FLOP add-sub	33.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.82
Bytes prefetched	0.00
Bytes loaded	400.00
Bytes stored	108.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.16
Vectorization ratio load	30.77
Vectorization ratio store	9.09
Vectorization ratio mul	100.00
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	36.84
Vector-efficiency ratio all	21.83
Vector-efficiency ratio load	22.60
Vector-efficiency ratio store	14.77
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	35.94
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	18.83

Metric	Value
CQA speedup if no scalar integer	1.90
CQA speedup if FP arith vectorized	1.87
CQA speedup if fully vectorized	9.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-61,attention.cpp:98-98,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.50
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.25
CQA cycles if fully vectorized	2.86
Front-end cycles	28.50
P0 cycles	14.43
P1 cycles	14.47
P2 cycles	13.67
P3 cycles	13.67
P4 cycles	8.00
P5 cycles	19.00
P6 cycles	14.50
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	14.60
P11 cycles	13.67
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	167.00
Nb uops	171.00
Nb loads	41.00
Nb stores	13.00
Nb stack references	16.00
FLOP/cycle	1.47
Nb FLOP add-sub	33.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.82
Bytes prefetched	0.00
Bytes loaded	400.00
Bytes stored	108.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.16
Vectorization ratio load	30.77
Vectorization ratio store	9.09
Vectorization ratio mul	100.00
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	36.84
Vector-efficiency ratio all	21.83
Vector-efficiency ratio load	22.60
Vector-efficiency ratio store	14.77
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	35.94
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	18.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,98,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52-61,98,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 72 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.50 to 15.00 cycles (1.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions).

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

30% of SSE/AVX loads are used in vector version.
9% of SSE/AVX stores are used in vector version.
75% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
36% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__intel_avx_rep_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
__svml_expf8_mask_l9: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 4 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

33: addition or subtraction
8: multiply
1: divide

The binary loop is loading 400 bytes (100 single precision FP elements). The binary loop is storing 108 bytes (27 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	167
nb uops	171
loop length	825
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	10
used zmm registers	0
nb stack references	16
ADD-SUB / MUL ratio	6.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.50 cycles
front end	28.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.43	14.47	13.67	13.67	8.00	19.00	14.50	8.00	8.00	8.00	14.60	13.67
cycles	14.43	14.47	13.67	13.67	8.00	19.00	14.50	8.00	8.00	8.00	14.60	13.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	28.50
Dispatch	19.00
DIV/SQRT	3.00
Overall L1	28.50

Vectorization ratios

INT

all	27%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	55%
load	40%
store	33%
mul	100%
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	53%

INT+FP

all	38%
load	30%
store	9%
mul	100%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	36%

Vector efficiency ratios

INT

all	21%
load	21%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	22%
load	23%
store	20%
mul	50%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	15%

INT+FP

all	21%
load	22%
store	14%
mul	50%
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

7% of peak load performance is reached (14.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 28.50 to 19.00 cycles (1.50x speedup).

ASM code

In the binary file, the address of the loop is: 406d49

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x1a0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM11,(%RAX,%RCX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x108(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x180(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 406cc0 <main+0x2ec0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
TEST $-0x8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 406da0 <main+0x2fa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 406dcd <main+0x2fcd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R10,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JE 406e80 <main+0x3080>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R10),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM8,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %YMM9,%YMM12,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV -0x100(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x160(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x148(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 406e9e <main+0x309e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 406ef9 <main+0x30f9>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM8,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x100(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM0,%YMM12,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPSUBQ %YMM0,%YMM12,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ %YMM14,%YMM0,%K0																vect (50.0%)
VPCMPNLEUQ %YMM15,%YMM1,%K1																vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K1,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS (%R14,%RDI,4),%YMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM11,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVM2D %K1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (1.6%)
CALL 408e20 <__svml_expf8_mask_l9>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW -0x98(%RBP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %YMM0,%YMM10,%YMM10{%K1}	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM0,%XMM10,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x820c(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VDIVSS %XMM11,%XMM0,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 407000 <main+0x3200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RDX),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL -0x40(%RBP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %RDI,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM8,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x408a40,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0xa0(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x60(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %R8,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %YMM9,%YMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV -0x148(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x160(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 40701e <main+0x321e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x408a40,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 406d00 <main+0x2f00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 407090 <main+0x3290>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL -0x40(%RBP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
VBROADCASTSS %XMM8,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM1,%YMM0,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPSUBQ %YMM1,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ %YMM14,%YMM0,%K0																vect (50.0%)
VPCMPNLEUQ %YMM15,%YMM2,%K1																vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x100(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RDI,4),%YMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM10,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVM2D %K1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (1.6%)
CALL 408e20 <__svml_expf8_mask_l9>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x60(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPS %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVW -0x38(%RBP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %YMM0,(%R13,%RDI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
CMP %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x408a40,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 406d00 <main+0x2f00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV $0x100000000,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAR $0x1e,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSS %XMM11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 40c5b0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS -0x38(%RBP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x60(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQU 0x8018(%RIP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQU 0x7ff0(%RIP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVSS 0x802c(%RIP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 406d00 <main+0x2f00>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,98,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52-61,98,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions).

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

30% of SSE/AVX loads are used in vector version.
9% of SSE/AVX stores are used in vector version.
75% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
36% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

__intel_avx_rep_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
__svml_expf8_mask_l9: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

33: addition or subtraction
8: multiply
1: divide

The binary loop is loading 400 bytes (100 single precision FP elements). The binary loop is storing 108 bytes (27 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	167
nb uops	171
loop length	825
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	10
used zmm registers	0
nb stack references	16
ADD-SUB / MUL ratio	6.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.50 cycles
front end	28.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.43	14.47	13.67	13.67	8.00	19.00	14.50	8.00	8.00	8.00	14.60	13.67
cycles	14.43	14.47	13.67	13.67	8.00	19.00	14.50	8.00	8.00	8.00	14.60	13.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	28.50
Dispatch	19.00
DIV/SQRT	3.00
Overall L1	28.50

Vectorization ratios

INT

all	27%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	55%
load	40%
store	33%
mul	100%
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	53%

INT+FP

all	38%
load	30%
store	9%
mul	100%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	36%

Vector efficiency ratios

INT

all	21%
load	21%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	22%
load	23%
store	20%
mul	50%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	15%

INT+FP

all	21%
load	22%
store	14%
mul	50%
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

7% of peak load performance is reached (14.04 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 406d49

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x1a0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM11,(%RAX,%RCX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x108(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x180(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 406cc0 <main+0x2ec0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
TEST $-0x8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 406da0 <main+0x2fa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 406dcd <main+0x2fcd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R10,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JE 406e80 <main+0x3080>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%R10),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM8,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %YMM9,%YMM12,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV -0x100(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x160(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x148(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 406e9e <main+0x309e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 406ef9 <main+0x30f9>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM8,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x100(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM0,%YMM12,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPSUBQ %YMM0,%YMM12,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ %YMM14,%YMM0,%K0																vect (50.0%)
VPCMPNLEUQ %YMM15,%YMM1,%K1																vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K1,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS (%R14,%RDI,4),%YMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM11,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVM2D %K1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (1.6%)
CALL 408e20 <__svml_expf8_mask_l9>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW -0x98(%RBP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %YMM0,%YMM10,%YMM10{%K1}	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM0,%XMM10,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x820c(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VDIVSS %XMM11,%XMM0,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 407000 <main+0x3200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RDX),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL -0x40(%RBP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %RDI,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM8,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x408a40,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0xa0(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x60(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %R8,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %YMM9,%YMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV -0x148(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x160(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 40701e <main+0x321e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x408a40,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 406d00 <main+0x2f00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 407090 <main+0x3290>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL -0x40(%RBP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
VBROADCASTSS %XMM8,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM1,%YMM0,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPSUBQ %YMM1,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ %YMM14,%YMM0,%K0																vect (50.0%)
VPCMPNLEUQ %YMM15,%YMM2,%K1																vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x100(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RDI,4),%YMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM10,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVM2D %K1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (1.6%)
CALL 408e20 <__svml_expf8_mask_l9>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x60(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMULPS %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
KMOVW -0x38(%RBP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %YMM0,(%R13,%RDI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
CMP %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV $0x408a40,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JAE 406d00 <main+0x2f00>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV $0x100000000,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
ADD %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAR $0x1e,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R13,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSS %XMM11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 40c5b0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS -0x38(%RBP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x60(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQU 0x8018(%RIP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQU 0x7ff0(%RIP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVSS 0x802c(%RIP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 406d00 <main+0x2f00>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code