OV - attention-avx512 - Function __svml_sexp_cout_rare

	Function: __svml_sexp_cout_rare_internal	Module: attention-avx512	Source: :0-0	Coverage (incl. loops): 1.80% \| (excl. loops): 1.80%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4090e0 ENDBR64

0x4090e4 MOV	(%RDI),%EAX

0x4090e6 MOV	%EAX,%ECX

0x4090e8 NOT	%ECX

0x4090ea MOVD	%EAX,%XMM0

0x4090ee TEST	$0x7f800000,%ECX

0x4090f4 JNE	409110

0x4090f6 AND	$-0x7f800001,%EAX

0x4090fb NEG	%EAX

0x4090fd XORPS	%XMM1,%XMM1

0x409100 JO	409109

0x409102 MULSS	%XMM0,%XMM0

0x409106 MOVAPS	%XMM0,%XMM1

0x409109 XOR	%EAX,%EAX

0x40910b MOVSS	%XMM1,(%RSI)

0x40910f RET

0x409110 MOVSS	0x6930(%RIP),%XMM1

0x409118 UCOMISS	%XMM0,%XMM1

0x40911b JAE	40912f

0x40911d MOVL	$0x7f800000,-0xc(%RSP)

0x409125 MOV	$0x3,%EAX

0x40912a JMP	409282

0x40912f UCOMISS	0x6916(%RIP),%XMM0

0x409136 JAE	409145

0x409138 MOVL	$0,-0xc(%RSP)

0x409140 JMP	40922f

0x409145 MOVSS	0x6903(%RIP),%XMM1

0x40914d MULSS	%XMM0,%XMM1

0x409151 MOVSS	%XMM1,-0x8(%RSP)

0x409157 MOVSS	-0x8(%RSP),%XMM1

0x40915d ADDSS	0x68ef(%RIP),%XMM1

0x409165 MOVSS	%XMM1,-0x4(%RSP)

0x40916b MOVSS	-0x4(%RSP),%XMM1

0x409171 MOVSS	0x68df(%RIP),%XMM2

0x409179 ADDSS	%XMM1,%XMM2

0x40917d MOVSS	%XMM2,-0x8(%RSP)

0x409183 MOVSS	-0x8(%RSP),%XMM2

0x409189 MULSS	0x68cb(%RIP),%XMM2

0x409191 MOVSS	-0x8(%RSP),%XMM3

0x409197 MULSS	0x68c1(%RIP),%XMM3

0x40919f ADDSS	%XMM0,%XMM2

0x4091a3 ADDSS	%XMM3,%XMM2

0x4091a7 MOVSS	0x68b5(%RIP),%XMM3

0x4091af MULSS	%XMM2,%XMM3

0x4091b3 ADDSS	0x68ad(%RIP),%XMM3

0x4091bb MOVD	%XMM1,%EAX

0x4091bf MULSS	%XMM2,%XMM3

0x4091c3 ADDSS	0x68a1(%RIP),%XMM3

0x4091cb MULSS	%XMM2,%XMM3

0x4091cf ADDSS	0x6899(%RIP),%XMM3

0x4091d7 MULSS	%XMM2,%XMM3

0x4091db MOVSS	0x6891(%RIP),%XMM1

0x4091e3 ADDSS	%XMM1,%XMM3

0x4091e7 MULSS	%XMM2,%XMM3

0x4091eb ADDSS	%XMM1,%XMM3

0x4091ef MOVSS	%XMM3,-0xc(%RSP)

0x4091f5 UCOMISS	0x687c(%RIP),%XMM0

0x4091fc JAE	409236

0x4091fe SAL	$0x17,%EAX

0x409201 ADD	$0x5d800000,%EAX

0x409206 AND	$0x7f800000,%EAX

0x40920b MOVD	%EAX,%XMM0

0x40920f MULSS	-0xc(%RSP),%XMM0

0x409215 MOVSS	%XMM0,-0xc(%RSP)

0x40921b MOVSS	-0xc(%RSP),%XMM0

0x409221 MULSS	0x6853(%RIP),%XMM0

0x409229 MOVSS	%XMM0,-0xc(%RSP)

0x40922f MOV	$0x4,%EAX

0x409234 JMP	409282

0x409236 MOVSX	%AX,%ECX

0x409239 ADD	$0x7f,%ECX

0x40923c CMP	$0xfe,%ECX

0x409242 JA	409253

0x409244 SAL	$0x17,%ECX

0x409247 MOVD	%ECX,%XMM0

0x40924b MULSS	-0xc(%RSP),%XMM0

0x409251 JMP	40927a

0x409253 SAL	$0x17,%EAX

0x409256 ADD	$0x3f000000,%EAX

0x40925b AND	$0x7f800000,%EAX

0x409260 MOVD	%EAX,%XMM0

0x409264 MULSS	-0xc(%RSP),%XMM0

0x40926a MOVSS	%XMM0,-0xc(%RSP)

0x409270 MOVSS	-0xc(%RSP),%XMM0

0x409276 ADDSS	%XMM0,%XMM0

0x40927a MOVSS	%XMM0,-0xc(%RSP)

0x409280 XOR	%EAX,%EAX

0x409282 MOVSS	-0xc(%RSP),%XMM1

0x409288 MOVSS	%XMM1,(%RSI)

0x40928c RET

0x40928d NOPL	(%RAX)

Coverage (%)	Name	Module
○29.41	__svml_l9__svml_sexp_cout_rare[...]	attention-avx512
○23.53	__svml_l9__svml_sexp_cout_rare[...]	attention-avx512
○17.65	__svml_l9__svml_sexp_cout_rare[...]	attention-avx512
○11.76	__svml_l9__svml_sexp_cout_rare[...]	attention-avx512
○11.76	__svml_l9__svml_sexp_cout_rare[...]	attention-avx512
○5.88	__svml_l9__svml_sexp_cout_rare[...]	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 1.80% of application time for run run_0

Source file and lines
Module	attention-avx512

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=7

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 7 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.33 to 12.83 cycles (1.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 6% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.33 to 0.96 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISS: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

MOVSX: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

26 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 23 FP arithmetical operations:

10: addition or subtraction
13: multiply

The binary function is loading 100 bytes (25 single precision FP elements). The binary function is storing 48 bytes (12 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	91
nb uops	92
loop length	432
used x86 registers	5
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.00	11.00	9.00	9.00	6.00	11.10	10.90	6.00	6.00	6.00	11.00	9.00
cycles	11.00	11.50	9.00	9.00	6.00	11.10	10.90	6.00	6.00	6.00	11.00	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.33
Dispatch	11.50
Overall L1	15.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	7%
load	6%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	6%
load	6%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

3% of peak load performance is reached (6.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.33 to 11.50 cycles (1.33x speedup).

ASM code

In the binary file, the address of the function is: 4090e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
MOV (%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
NOT %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
TEST $0x7f800000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JNE 409110 <__svml_sexp_cout_rare_internal+0x30>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $-0x7f800001,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XORPS %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JO 409109 <__svml_sexp_cout_rare_internal+0x29>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MULSS %XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVAPS %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSS %XMM1,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOVSS 0x6930(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
UCOMISS %XMM0,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JAE 40912f <__svml_sexp_cout_rare_internal+0x4f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVL $0x7f800000,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x3,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 409282 <__svml_sexp_cout_rare_internal+0x1a2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
UCOMISS 0x6916(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 409145 <__svml_sexp_cout_rare_internal+0x65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVL $0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 40922f <__svml_sexp_cout_rare_internal+0x14f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOVSS 0x6903(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS %XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVSS %XMM1,-0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0x8(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADDSS 0x68ef(%RIP),%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	scal (6.3%)
MOVSS %XMM1,-0x4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0x4(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVSS 0x68df(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADDSS %XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MOVSS %XMM2,-0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0x8(%RSP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS 0x68cb(%RIP),%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
MOVSS -0x8(%RSP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS 0x68c1(%RIP),%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
ADDSS %XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
ADDSS %XMM3,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MOVSS 0x68b5(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADDSS 0x68ad(%RIP),%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	scal (6.3%)
MOVD %XMM1,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADDSS 0x68a1(%RIP),%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADDSS 0x6899(%RIP),%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVSS 0x6891(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADDSS %XMM1,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADDSS %XMM1,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MOVSS %XMM3,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
UCOMISS 0x687c(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 409236 <__svml_sexp_cout_rare_internal+0x156>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x17,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD $0x5d800000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7f800000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MULSS -0xc(%RSP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
MOVSS %XMM0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0xc(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS 0x6853(%RIP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
MOVSS %XMM0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x4,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 409282 <__svml_sexp_cout_rare_internal+0x1a2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOVSX %AX,%ECX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD $0x7f,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP $0xfe,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JA 409253 <__svml_sexp_cout_rare_internal+0x173>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x17,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOVD %ECX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MULSS -0xc(%RSP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
JMP 40927a <__svml_sexp_cout_rare_internal+0x19a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
SAL $0x17,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD $0x3f000000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7f800000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MULSS -0xc(%RSP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
MOVSS %XMM0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0xc(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADDSS %XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MOVSS %XMM0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSS -0xc(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVSS %XMM1,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 1.80% of application time for run run_0

Source file and lines
Module	attention-avx512

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=7

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISS: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

MOVSX: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

26 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 23 FP arithmetical operations:

10: addition or subtraction
13: multiply

The binary function is loading 100 bytes (25 single precision FP elements). The binary function is storing 48 bytes (12 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	91
nb uops	92
loop length	432
used x86 registers	5
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.77

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.00	11.00	9.00	9.00	6.00	11.10	10.90	6.00	6.00	6.00	11.00	9.00
cycles	11.00	11.50	9.00	9.00	6.00	11.10	10.90	6.00	6.00	6.00	11.00	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.33
Dispatch	11.50
Overall L1	15.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	7%
load	6%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	6%
load	6%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

3% of peak load performance is reached (6.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4090e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
MOV (%RDI),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
NOT %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
TEST $0x7f800000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JNE 409110 <__svml_sexp_cout_rare_internal+0x30>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $-0x7f800001,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XORPS %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JO 409109 <__svml_sexp_cout_rare_internal+0x29>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MULSS %XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVAPS %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSS %XMM1,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOVSS 0x6930(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
UCOMISS %XMM0,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JAE 40912f <__svml_sexp_cout_rare_internal+0x4f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVL $0x7f800000,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x3,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 409282 <__svml_sexp_cout_rare_internal+0x1a2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
UCOMISS 0x6916(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 409145 <__svml_sexp_cout_rare_internal+0x65>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVL $0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 40922f <__svml_sexp_cout_rare_internal+0x14f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOVSS 0x6903(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS %XMM0,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVSS %XMM1,-0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0x8(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADDSS 0x68ef(%RIP),%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	scal (6.3%)
MOVSS %XMM1,-0x4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0x4(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVSS 0x68df(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADDSS %XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MOVSS %XMM2,-0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0x8(%RSP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS 0x68cb(%RIP),%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
MOVSS -0x8(%RSP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS 0x68c1(%RIP),%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
ADDSS %XMM0,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
ADDSS %XMM3,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MOVSS 0x68b5(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADDSS 0x68ad(%RIP),%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	scal (6.3%)
MOVD %XMM1,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADDSS 0x68a1(%RIP),%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADDSS 0x6899(%RIP),%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	2-3	0.50	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVSS 0x6891(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADDSS %XMM1,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MULSS %XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
ADDSS %XMM1,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MOVSS %XMM3,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
UCOMISS 0x687c(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 409236 <__svml_sexp_cout_rare_internal+0x156>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x17,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD $0x5d800000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7f800000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MULSS -0xc(%RSP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
MOVSS %XMM0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0xc(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MULSS 0x6853(%RIP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
MOVSS %XMM0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x4,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 409282 <__svml_sexp_cout_rare_internal+0x1a2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOVSX %AX,%ECX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD $0x7f,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP $0xfe,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JA 409253 <__svml_sexp_cout_rare_internal+0x173>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x17,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOVD %ECX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MULSS -0xc(%RSP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
JMP 40927a <__svml_sexp_cout_rare_internal+0x19a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
SAL $0x17,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD $0x3f000000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7f800000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVD %EAX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
MULSS -0xc(%RSP),%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
MOVSS %XMM0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSS -0xc(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADDSS %XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	2-3	0.50	scal (6.3%)
MOVSS %XMM0,-0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSS -0xc(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVSS %XMM1,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
○__svml_sexp_cout_rare_internal	1.80	0.09

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code