OV - attention-avx512 - Function __svml_expf8

	Function: __svml_expf8_l9	Module: attention-avx512	Source: :0-0	Coverage (incl. loops): 1.90% \| (excl. loops): 1.90%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x408a40 ENDBR64

0x408a44 VMOVUPS	0x9ab4(%RIP),%YMM1

0x408a4c VMOVUPS	0x9cec(%RIP),%YMM2

0x408a54 VMOVUPS	0x9a64(%RIP),%YMM3

0x408a5c VFMADD213PS	%YMM1,%YMM0,%YMM3

0x408a61 VSUBPS	%YMM1,%YMM3,%YMM1

0x408a65 VANDPS	0x9d13(%RIP),%YMM0,%YMM4

0x408a6d VPCMPGTD	0x9d4b(%RIP),%YMM4,%YMM4

0x408a75 VMOVMSKPS	%YMM4,%EAX

0x408a79 VPSLLD	$0x17,%YMM3,%YMM3

0x408a7e VMOVUPS	0x9aba(%RIP),%YMM4

0x408a86 VFNMADD213PS	%YMM0,%YMM1,%YMM4

0x408a8b VFNMADD231PS	0x9aec(%RIP),%YMM1,%YMM4

0x408a94 VFMADD213PS	0x9c63(%RIP),%YMM4,%YMM2

0x408a9d VFMADD213PS	0x9c1a(%RIP),%YMM4,%YMM2

0x408aa6 VFMADD213PS	0x9bd1(%RIP),%YMM4,%YMM2

0x408aaf VFMADD213PS	0x9b88(%RIP),%YMM4,%YMM2

0x408ab8 VFMADD213PS	0x9b3f(%RIP),%YMM4,%YMM2

0x408ac1 VPADDD	%YMM2,%YMM3,%YMM1

0x408ac5 TEST	%EAX,%EAX

0x408ac7 JNE	408ace

0x408ac9 VMOVAPS	%YMM1,%YMM0

0x408acd RET

0x408ace MOVZX	%AL,%EAX

0x408ad1 VMOVUPS	0x9d27(%RIP),%YMM2

0x408ad9 VBROADCASTSS	0x6a3e(%RIP),%YMM3

0x408ae2 VCMPPS	$0x1,%YMM0,%YMM2,%YMM2

0x408ae7 VBLENDVPS	%YMM2,%YMM3,%YMM1,%YMM1

0x408aed VCMPPS	$0x1,0x9d4a(%RIP),%YMM0,%YMM3

0x408af6 VANDNPS	%YMM1,%YMM3,%YMM1

0x408afa VORPS	%YMM3,%YMM2,%YMM2

0x408afe VMOVMSKPS	%YMM2,%ECX

0x408b02 ANDN	%EAX,%ECX,%EDX

0x408b07 JE	408ac9

0x408b09 PUSH	%RBP

0x408b0a MOV	%RSP,%RBP

0x408b0d PUSH	%RSI

0x408b0e PUSH	%RDI

0x408b0f AND	$-0x40,%RSP

0x408b13 SUB	$0x180,%RSP

0x408b1a VMOVUPS	%YMM15,-0x30(%RBP)

0x408b1f VMOVUPS	%YMM14,-0x50(%RBP)

0x408b24 VMOVUPS	%YMM13,-0x70(%RBP)

0x408b29 VMOVUPS	%YMM12,-0x90(%RBP)

0x408b31 VMOVUPS	%YMM11,-0xb0(%RBP)

0x408b39 VMOVUPS	%YMM10,-0xd0(%RBP)

0x408b41 VMOVUPS	%YMM9,-0xf0(%RBP)

0x408b49 VMOVUPS	%YMM8,-0x110(%RBP)

0x408b51 VMOVUPS	%YMM0,0x40(%RSP)

0x408b57 VMOVUPS	%YMM1,(%RSP)

0x408b5c LEA	0x40(%RSP),%RDI

0x408b61 MOV	%RSP,%RSI

0x408b64 VZEROUPPER

0x408b67 CALL	408bc0 <__svml_l9__svml_sexp_cout_rare_internal_wrapper>

0x408b6d VMOVUPS	(%RSP),%YMM1

0x408b72 VMOVUPS	-0x110(%RBP),%YMM8

0x408b7a VMOVUPS	-0xf0(%RBP),%YMM9

0x408b82 VMOVUPS	-0xd0(%RBP),%YMM10

0x408b8a VMOVUPS	-0xb0(%RBP),%YMM11

0x408b92 VMOVUPS	-0x90(%RBP),%YMM12

0x408b9a VMOVUPS	-0x70(%RBP),%YMM13

0x408b9f VMOVUPS	-0x50(%RBP),%YMM14

0x408ba4 VMOVUPS	-0x30(%RBP),%YMM15

0x408ba9 LEA	-0x10(%RBP),%RSP

0x408bad POP	%RDI

0x408bae POP	%RSI

0x408baf POP	%RBP

0x408bb0 VMOVAPS	%YMM1,%YMM0

0x408bb4 RET

0x408bb5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○33.33	main	attention.cpp:53	attention-avx512
○11.11	main	attention.cpp:56	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 1.90% of application time for run run_0

Source file and lines
Module	attention-avx512

This function has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

96% of SSE/AVX loads are used in vector version.
86% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

FMA

Detected 64 FMA (fused multiply-add) operations.

Type of elements and instruction set

10 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 136 FP arithmetical operations:

72: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary function is loading 525 bytes (131 single precision FP elements). The binary function is storing 106 bytes (26 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	41.33
nb uops	42.67
loop length	237
used x86 registers	3.67
used mmx registers	0
used xmm registers	0
used ymm registers	7.67
used zmm registers	0
nb stack references	3.67

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	7.11 cycles
front end	7.11 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.72	6.72	6.33	6.33	2.33	5.89	3.00	2.33	2.33	2.33	2.33	6.33
cycles	6.72	6.72	6.33	6.33	2.33	5.89	3.00	2.33	2.33	2.33	2.33	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.11
Dispatch	7.39
Overall L1	8.22

Vectorization ratios

INT

all	77%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	72%

all	97%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

INT+FP

all	94%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	86%

Vector efficiency ratios

INT

all	39%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	36%

all	49%
load	48%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

INT+FP

all	47%
load	48%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.22 cycles. At this rate:

33% of peak load performance is reached (64.66 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.01 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

The code analyzed by CQA in that panel excludes loops and represents 1.90% of application time for run run_0

Source file and lines
Module	attention-avx512

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.50 to 4.33 cycles (1.27x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

FMA

Detected 64 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 4 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

9 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 136 FP arithmetical operations:

72: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary function is loading 384 bytes (96 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.35 FP operations per loaded or stored byte.

General properties

nb instructions	23
nb uops	22
loop length	142
used x86 registers	1
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	5.50	4.33	4.33	0.00	3.00	2.00	0.00	0.00	0.00	1.00	4.33
cycles	5.50	5.50	4.33	4.33	0.00	3.00	2.00	0.00	0.00	0.00	1.00	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.67
Dispatch	5.50
Overall L1	5.50

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

36% of peak load performance is reached (69.82 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 408a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVUPS 0x9ab4(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x9cec(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x9a64(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PS %YMM1,%YMM0,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM1,%YMM3,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VANDPS 0x9d13(%RIP),%YMM0,%YMM4	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPCMPGTD 0x9d4b(%RIP),%YMM4,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	0-3	0.50	vect (50.0%)
VMOVMSKPS %YMM4,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
VPSLLD $0x17,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VMOVUPS 0x9aba(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFNMADD213PS %YMM0,%YMM1,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD231PS 0x9aec(%RIP),%YMM1,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9c63(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9c1a(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9bd1(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9b88(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9b3f(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VPADDD %YMM2,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408ace <__svml_expf8_l9+0x8e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPS %YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 1.90% of application time for run run_0

Source file and lines
Module	attention-avx512

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.83 to 9.33 cycles (1.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is highly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions).

Details

92% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

95% of SSE/AVX loads are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

FMA

Detected 64 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_l9__svml_sexp_cout_rare_internal_wrapper: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPS: 1 occurrences►
VCMPPS: 1 occurrences►
VZEROUPPER: 1 occurrences►

Vector unaligned load/store instructions

Detected 24 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 24 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

11 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 136 FP arithmetical operations:

72: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary function is loading 740 bytes (185 single precision FP elements). The binary function is storing 320 bytes (80 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	67
nb uops	71
loop length	368
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	13
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.83 cycles
front end	11.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.33	7.33	9.33	9.33	7.00	7.33	4.00	7.00	7.00	7.00	4.00	9.33
cycles	7.33	7.33	9.33	9.33	7.00	7.33	4.00	7.00	7.00	7.00	4.00	9.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.83
Dispatch	9.33
Overall L1	11.83

Vectorization ratios

INT

all	57%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	97%
load	95%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	92%
load	95%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Vector efficiency ratios

INT

all	28%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	48%
load	48%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	46%
load	48%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.83 cycles. At this rate:

32% of peak load performance is reached (62.54 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (27.04 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.83 to 9.33 cycles (1.27x speedup).

ASM code

In the binary file, the address of the function is: 408a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVUPS 0x9ab4(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x9cec(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x9a64(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PS %YMM1,%YMM0,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM1,%YMM3,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VANDPS 0x9d13(%RIP),%YMM0,%YMM4	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPCMPGTD 0x9d4b(%RIP),%YMM4,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	0-3	0.50	vect (50.0%)
VMOVMSKPS %YMM4,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
VPSLLD $0x17,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VMOVUPS 0x9aba(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFNMADD213PS %YMM0,%YMM1,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD231PS 0x9aec(%RIP),%YMM1,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9c63(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9c1a(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9bd1(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9b88(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9b3f(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VPADDD %YMM2,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JNE 408ace <__svml_expf8_l9+0x8e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVZX %AL,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS 0x9d27(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VBROADCASTSS 0x6a3e(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VCMPPS $0x1,%YMM0,%YMM2,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBLENDVPS %YMM2,%YMM3,%YMM1,%YMM1	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (50.0%)
VCMPPS $0x1,0x9d4a(%RIP),%YMM0,%YMM3	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VANDNPS %YMM1,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VORPS %YMM3,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVMSKPS %YMM2,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
ANDN %EAX,%ECX,%EDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	scal (6.3%)
JE 408ac9 <__svml_expf8_l9+0x89>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RSI	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RDI	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x180,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS %YMM15,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM14,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM13,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM12,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM11,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM10,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM9,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM8,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM1,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
LEA 0x40(%RSP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSP,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 408bc0 <__svml_l9__svml_sexp_cout_rare_internal_wrapper>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVUPS (%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0x110(%RBP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0xf0(%RBP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0xd0(%RBP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0xb0(%RBP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0x90(%RBP),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0x70(%RBP),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0x50(%RBP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0x30(%RBP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
LEA -0x10(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VMOVAPS %YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 1.90% of application time for run run_0

Source file and lines
Module	attention-avx512

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is highly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions).

Details

92% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

93% of SSE/AVX loads are used in vector version.
84% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPS: 1 occurrences►
VCMPPS: 1 occurrences►

Vector unaligned load/store instructions

Detected 5 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 5 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

11 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 136 FP arithmetical operations:

72: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary function is loading 452 bytes (113 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	34
nb uops	35
loop length	201
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.33	7.33	5.33	5.33	0.00	7.33	3.00	0.00	0.00	0.00	2.00	5.33
cycles	7.33	7.33	5.33	5.33	0.00	7.33	3.00	0.00	0.00	0.00	2.00	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.83
Dispatch	7.33
Overall L1	7.33

Vectorization ratios

INT

all	75%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	95%
load	92%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	92%
load	93%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	84%

Vector efficiency ratios

INT

all	39%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	48%
load	46%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	46%
load	47%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.33 cycles. At this rate:

32% of peak load performance is reached (61.64 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 408a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVUPS 0x9ab4(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x9cec(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x9a64(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PS %YMM1,%YMM0,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM1,%YMM3,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VANDPS 0x9d13(%RIP),%YMM0,%YMM4	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPCMPGTD 0x9d4b(%RIP),%YMM4,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	0-3	0.50	vect (50.0%)
VMOVMSKPS %YMM4,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
VPSLLD $0x17,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VMOVUPS 0x9aba(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFNMADD213PS %YMM0,%YMM1,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD231PS 0x9aec(%RIP),%YMM1,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9c63(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9c1a(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9bd1(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9b88(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0x9b3f(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VPADDD %YMM2,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408ace <__svml_expf8_l9+0x8e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPS %YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOVZX %AL,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS 0x9d27(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VBROADCASTSS 0x6a3e(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VCMPPS $0x1,%YMM0,%YMM2,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBLENDVPS %YMM2,%YMM3,%YMM1,%YMM1	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (50.0%)
VCMPPS $0x1,0x9d4a(%RIP),%YMM0,%YMM3	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VANDNPS %YMM1,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VORPS %YMM3,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVMSKPS %YMM2,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
ANDN %EAX,%ECX,%EDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	scal (6.3%)
JE 408ac9 <__svml_expf8_l9+0x89>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Name	Coverage (%)	Time (s)
○__svml_expf8_l9	1.90	0.09

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

FMA

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

FMA

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround