OV - attention-avx512 - Loop 41

0x403dc0 LEA	0x1(%R11),%R14D

0x403dc4 MOV	0x30(%RSP),%RAX

0x403dc9 ADD	%RAX,%R10

0x403dcc CMP	%EDX,%R11D

0x403dcf MOV	%R14D,%R11D

0x403dd2 JE	403da0

0x403dd4 MOV	%R11D,%R14D

0x403dd7 IMUL	%EAX,%R14D

0x403ddb VPBROADCASTD	%R14D,%YMM4

0x403de1 XOR	%R15D,%R15D

0x403de4 JMP	403e9b

  (42) 0x403df0 VPBROADCASTQ	%R12,%ZMM7

  (42) 0x403df6 VPSUBQ	%ZMM7,%ZMM11,%ZMM8

  (42) 0x403dfc VPCMPNLEUQ	%ZMM0,%ZMM8,%K1

  (42) 0x403e03 VPMOVQD	%ZMM7,%YMM7

  (42) 0x403e09 VPADDD	%YMM1,%YMM7,%YMM7

  (42) 0x403e0d VPADDD	%YMM7,%YMM4,%YMM8

  (42) 0x403e11 VPSUBD	%YMM2,%YMM8,%YMM8

  (42) 0x403e15 KMOVQ	%K1,%K2

  (42) 0x403e1a VXORPS	%XMM9,%XMM9,%XMM9

  (42) 0x403e1f VGATHERDPS	(%R8,%YMM8,4),%YMM9{%K2}

  (42) 0x403e26 VCVTPS2PD	%YMM9,%ZMM8

  (42) 0x403e2c VPMULLD	%YMM7,%YMM10,%YMM7

  (42) 0x403e31 VPADDD	%YMM7,%YMM6,%YMM6

  (42) 0x403e35 VPSUBD	%YMM2,%YMM6,%YMM6

  (42) 0x403e39 KMOVQ	%K1,%K2

  (42) 0x403e3e VPXOR	%XMM7,%XMM7,%XMM7

  (42) 0x403e42 VGATHERDPS	(%R9,%YMM6,4),%YMM7{%K2}

  (42) 0x403e49 VCVTPS2PD	%YMM7,%ZMM6

  (42) 0x403e4f VFMADD231PD	%ZMM8,%ZMM6,%ZMM5{%K1}

  (42) 0x403e55 VEXTRACTF64X4	$0x1,%ZMM5,%YMM6

  (42) 0x403e5c VADDPD	%ZMM6,%ZMM5,%ZMM5

  (42) 0x403e62 VEXTRACTF128	$0x1,%YMM5,%XMM6

  (42) 0x403e68 VADDPD	%XMM6,%XMM5,%XMM5

  (42) 0x403e6c VSHUFPD	$0x1,%XMM5,%XMM5,%XMM6

  (42) 0x403e71 VADDSD	%XMM6,%XMM5,%XMM5

  (42) 0x403e75 VCVTSD2SS	%XMM5,%XMM5,%XMM5

  (42) 0x403e79 LEA	(%R14,%R15,1),%R12D

  (42) 0x403e7d MOV	0xc8(%RSP),%RAX

  (42) 0x403e85 VMOVSS	%XMM5,(%RAX,%R12,4)

  (42) 0x403e8b LEA	0x1(%R15),%R12

  (42) 0x403e8f CMP	%RSI,%R15

  (42) 0x403e92 MOV	%R12,%R15

  (42) 0x403e95 JE	403dc0

  (42) 0x403e9b VPBROADCASTD	%R15D,%YMM6

  (42) 0x403ea1 VXORPD	%XMM5,%XMM5,%XMM5

  (42) 0x403ea5 XOR	%R12D,%R12D

  (42) 0x403ea8 TEST	%RDI,%RDI

  (42) 0x403eab JE	403df0

  (42) 0x403eb1 NOPW	%CS:(%RAX,%RAX,1)

    (43) 0x403ec0 LEA	(%R10,%R12,1),%R13D

    (43) 0x403ec4 VPBROADCASTD	%R13D,%YMM7

    (43) 0x403eca VPADDD	%YMM3,%YMM7,%YMM7

    (43) 0x403ece VPCMPEQB	%XMM0,%XMM0,%K1

    (43) 0x403ed4 VXORPD	%XMM8,%XMM8,%XMM8

    (43) 0x403ed9 VGATHERDPS	(%R8,%YMM7,4),%YMM8{%K1}

    (43) 0x403ee0 VCVTPS2PD	%YMM8,%ZMM7

    (43) 0x403ee6 VPBROADCASTD	%R12D,%YMM8

    (43) 0x403eec VPADDD	%YMM1,%YMM8,%YMM8

    (43) 0x403ef0 VPMULLD	%YMM8,%YMM10,%YMM8

    (43) 0x403ef5 VPADDD	%YMM6,%YMM8,%YMM8

    (43) 0x403ef9 VPSUBD	%YMM2,%YMM8,%YMM8

    (43) 0x403efd VPCMPEQB	%XMM0,%XMM0,%K1

    (43) 0x403f03 VXORPS	%XMM9,%XMM9,%XMM9

    (43) 0x403f08 VGATHERDPS	(%R9,%YMM8,4),%YMM9{%K1}

    (43) 0x403f0f VCVTPS2PD	%YMM9,%ZMM8

    (43) 0x403f15 VFMADD231PD	%ZMM8,%ZMM7,%ZMM5

    (43) 0x403f1b ADD	$0x8,%R12

    (43) 0x403f1f CMP	%RDI,%R12

    (43) 0x403f22 JB	403ec0

  (42) 0x403f24 MOV	%RDI,%R12

  (42) 0x403f27 CMP	%EDI,0x38(%RSP)

  (42) 0x403f2b MOV	0x88(%RSP),%R13

  (42) 0x403f33 JNE	403df0

  (42) 0x403f39 JMP	403e55

/home/eoseret/llm-attention/attention.cpp: 26 - 98

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:31-31
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.83
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.14
Front-end cycles	1.83
P0 cycles	1.30
P1 cycles	1.60
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.00
P5 cycles	1.20
P6 cycles	1.10
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.20
P11 cycles	0.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.36
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:31-31
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.83
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.14
Front-end cycles	1.83
P0 cycles	1.30
P1 cycles	1.60
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.00
P5 cycles	1.20
P6 cycles	1.10
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.20
P11 cycles	0.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.36
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-98
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,31.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.83 to 1.00 cycles (1.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	11
nb uops	11
loop length	41
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.83 cycles
front end	1.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.30	1.20	0.33	0.33	0.00	1.20	1.10	0.00	0.00	0.00	1.20	0.33
cycles	1.30	1.60	0.33	0.33	0.00	1.20	1.10	0.00	0.00	0.00	1.20	0.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	1.83
Dispatch	1.60
Data deps.	0.00
Overall L1	1.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.83 cycles. At this rate:

2% of peak load performance is reached (4.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.83 to 1.60 cycles (1.15x speedup).

ASM code

In the binary file, the address of the loop is: 403dd4

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%R11),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
CMP %EDX,%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %R14D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 403da0 <main+0xae0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R11D,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %EAX,%R14D	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %R14D,%YMM4	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 403e9b <main+0xbdb>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:26-98
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,31.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.83 to 1.00 cycles (1.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	11
nb uops	11
loop length	41
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.83 cycles
front end	1.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.30	1.20	0.33	0.33	0.00	1.20	1.10	0.00	0.00	0.00	1.20	0.33
cycles	1.30	1.60	0.33	0.33	0.00	1.20	1.10	0.00	0.00	0.00	1.20	0.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	1.83
Dispatch	1.60
Data deps.	0.00
Overall L1	1.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.83 cycles. At this rate:

2% of peak load performance is reached (4.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.83 to 1.60 cycles (1.15x speedup).

ASM code

In the binary file, the address of the loop is: 403dd4

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%R11),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
CMP %EDX,%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %R14D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 403da0 <main+0xae0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R11D,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %EAX,%R14D	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %R14D,%YMM4	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 403e9b <main+0xbdb>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code