OV - attention-avx512 - Loop 30

	Loop Id: 30	Module: attention-avx512	Source: attention.cpp:27-98 [...]	Coverage: 19.96%

0x404610 VPBROADCASTQ	%R12,%ZMM9

0x404616 VPSUBQ	%ZMM9,%ZMM12,%ZMM10

0x40461c VPCMPNLEUQ	%ZMM2,%ZMM10,%K1

0x404623 VPMOVQD	%ZMM9,%YMM9

0x404629 VPADDD	%YMM3,%YMM9,%YMM9

0x40462d VPADDD	%YMM6,%YMM9,%YMM10

0x404631 VPSUBD	%YMM4,%YMM10,%YMM10

0x404635 VXORPS	%XMM11,%XMM11,%XMM11

0x40463a KMOVQ	%K1,%K2

0x40463f VGATHERDPS	(%R8,%YMM10,4),%YMM11{%K2}

0x404646 VCVTPS2PD	%YMM11,%ZMM10

0x40464c VPMULLD	%YMM9,%YMM0,%YMM9

0x404651 VPADDD	%YMM9,%YMM8,%YMM8

0x404656 VPSUBD	%YMM4,%YMM8,%YMM8

0x40465a VPXOR	%XMM9,%XMM9,%XMM9

0x40465f KMOVQ	%K1,%K2

0x404664 VGATHERDPS	(%R9,%YMM8,4),%YMM9{%K2}

0x40466b VCVTPS2PD	%YMM9,%ZMM8

0x404671 VFMADD231PD	%ZMM10,%ZMM8,%ZMM7{%K1}

0x404677 VEXTRACTF64X4	$0x1,%ZMM7,%YMM8

0x40467e VADDPD	%ZMM8,%ZMM7,%ZMM7

0x404684 VEXTRACTF128	$0x1,%YMM7,%XMM8

0x40468a VADDPD	%XMM7,%XMM8,%XMM7

0x40468e VSHUFPD	$0x1,%XMM7,%XMM7,%XMM8

0x404693 VADDSD	%XMM7,%XMM8,%XMM7

0x404697 VCVTSD2SS	%XMM7,%XMM7,%XMM7

0x40469b VMULSS	%XMM1,%XMM7,%XMM7

0x40469f LEA	(%R14,%R15,1),%R12D

0x4046a3 MOV	0x58(%RSP),%RAX

0x4046a8 VMOVSS	%XMM7,(%RAX,%R12,4)

0x4046ae LEA	0x1(%R15),%R12

0x4046b2 CMP	%RSI,%R15

0x4046b5 MOV	%R12,%R15

0x4046b8 JE	4045d0

0x4046be VPBROADCASTD	%R15D,%YMM8

0x4046c4 VXORPD	%XMM7,%XMM7,%XMM7

0x4046c8 XOR	%R12D,%R12D

0x4046cb TEST	%RDI,%RDI

0x4046ce JE	404610

0x4046d4 NOPW	%CS:(%RAX,%RAX,1)

  (31) 0x4046e0 LEA	(%R10,%R12,1),%R13D

  (31) 0x4046e4 VPBROADCASTD	%R13D,%YMM9

  (31) 0x4046ea VPADDD	%YMM5,%YMM9,%YMM9

  (31) 0x4046ee VPXOR	%XMM10,%XMM10,%XMM10

  (31) 0x4046f3 VPCMPEQB	%XMM0,%XMM0,%K1

  (31) 0x4046f9 VGATHERDPS	(%R8,%YMM9,4),%YMM10{%K1}

  (31) 0x404700 VCVTPS2PD	%YMM10,%ZMM9

  (31) 0x404706 VPBROADCASTD	%R12D,%YMM10

  (31) 0x40470c VPADDD	%YMM3,%YMM10,%YMM10

  (31) 0x404710 VPMULLD	%YMM10,%YMM0,%YMM10

  (31) 0x404715 VPADDD	%YMM10,%YMM8,%YMM10

  (31) 0x40471a VPSUBD	%YMM4,%YMM10,%YMM10

  (31) 0x40471e VPXOR	%XMM11,%XMM11,%XMM11

  (31) 0x404723 VPCMPEQB	%XMM0,%XMM0,%K1

  (31) 0x404729 VGATHERDPS	(%R9,%YMM10,4),%YMM11{%K1}

  (31) 0x404730 VCVTPS2PD	%YMM11,%ZMM10

  (31) 0x404736 VFMADD231PD	%ZMM10,%ZMM9,%ZMM7

  (31) 0x40473c ADD	$0x8,%R12

  (31) 0x404740 CMP	%RDI,%R12

  (31) 0x404743 JB	4046e0

0x404745 MOV	%RDI,%R12

0x404748 CMP	%EDI,0x38(%RSP)

0x40474c MOV	0x88(%RSP),%R13

0x404754 JNE	404610

0x40475a JMP	404677

/home/eoseret/llm-attention/attention.cpp: 27 - 98

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.10
CQA speedup if fully vectorized	1.90
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33,attention.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.94
CQA cycles if no scalar integer	8.33
CQA cycles if FP arith vectorized	8.13
CQA cycles if fully vectorized	4.72
Front-end cycles	7.28
P0 cycles	8.47
P1 cycles	8.51
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	0.50
P5 cycles	8.56
P6 cycles	2.93
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.87
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.33
Nb uops	43.67
Nb loads	3.67
Nb stores	1.00
Nb stack references	2.33
FLOP/cycle	2.53
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	5.33
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.67
Bytes prefetched	0.00
Bytes loaded	58.67
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	63.23
Vectorization ratio load	55.56
Vectorization ratio store	0.00
Vectorization ratio mul	33.33
Vectorization ratio add_sub	81.48
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	65.20
Vector-efficiency ratio all	36.38
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	20.83
Vector-efficiency ratio add_sub	51.39
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.30

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.10
CQA speedup if fully vectorized	2.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P1,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33,attention.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	10.17
CQA cycles if fully vectorized	5.50
Front-end cycles	8.17
P0 cycles	11.00
P1 cycles	11.17
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	0.50
P5 cycles	10.83
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	5.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	49.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	2.51
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.81
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.86
Vectorization ratio load	100.00
Vectorization ratio store	0.00
Vectorization ratio mul	50.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	75.00
Vector-efficiency ratio all	43.75
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	28.13
Vector-efficiency ratio add_sub	54.17
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	38.67

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	1.11
CQA speedup if fully vectorized	1.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33,attention.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.06
CQA cycles if fully vectorized	2.78
Front-end cycles	4.50
P0 cycles	3.40
P1 cycles	3.20
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.50
P5 cycles	4.00
P6 cycles	3.20
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	3.20
P11 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	27.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	2.67
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.33
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	42.86
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	23.66
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.09

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.10
CQA speedup if fully vectorized	1.90
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P1,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-33,attention.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	10.17
CQA cycles if fully vectorized	5.87
Front-end cycles	9.17
P0 cycles	11.00
P1 cycles	11.17
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	0.50
P5 cycles	10.83
P6 cycles	3.60
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	3.40
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	55.00
Nb loads	5.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	2.51
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.88
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	70.97
Vectorization ratio load	66.67
Vectorization ratio store	0.00
Vectorization ratio mul	50.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	70.59
Vector-efficiency ratio all	41.73
Vector-efficiency ratio load	37.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	28.13
Vector-efficiency ratio add_sub	54.17
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:27-98
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:27-33,98.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:27,30-33,98.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 36% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.94 to 4.72 cycles (1.90x speedup).

Details

63% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

55% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
81% of SSE/AVX addition or subtraction instructions are used in vector version.
33% of SSE/AVX multiply instructions are used in vector version.
65% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 5.33 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 0 occurrences
VCVTSD2SS: 0 occurrences
VGATHERDPS: 0 occurrences
VPMULLD: 0 occurrences

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 0 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 0 occurrences
VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences
VPMOVQD: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 22.666666666667 FP arithmetical operations:

16.33: addition or subtraction (5 inside FMA instructions)
6.33: multiply (5 inside FMA instructions)

The binary loop is loading 58 bytes (7 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.36 FP operations per loaded or stored byte.

General properties

nb instructions	36.33
nb uops	43.67
loop length	185.33
used x86 registers	9
used mmx registers	0
used xmm registers	4.33
used ymm registers	6.67
used zmm registers	4.67
nb stack references	2.33
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	7.28 cycles
front end	7.28 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.47	8.51	4.33	4.33	0.50	8.56	2.93	0.50	0.50	0.50	2.87	4.33
cycles	8.47	8.51	4.33	4.33	0.50	8.56	2.93	0.50	0.50	0.50	2.87	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	7.28
Dispatch	8.78
Data deps.	0.00
Overall L1	8.94

Vectorization ratios

INT

all	47%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	70%
load	100%
store	0%
mul	0%
add-sub	66%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	86%

INT+FP

all	63%
load	55%
store	0%
mul	33%
add-sub	81%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	65%

Vector efficiency ratios

INT

all	35%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	35%
load	50%
store	6%
mul	6%
add-sub	45%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	36%
load	33%
store	6%
mul	20%
add-sub	51%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.94 cycles. At this rate:

3% of peak load performance is reached (6.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.54 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention.cpp:27-98
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 10.50 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 43% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.17 to 5.50 cycles (2.03x speedup).

Details

75% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX stores are used in vector version.
88% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
VPMOVQD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 2 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

19: addition or subtraction (8 inside FMA instructions)
9: multiply (8 inside FMA instructions)

The binary loop is loading 72 bytes (9 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	39
nb uops	49
loop length	196
used x86 registers	9
used mmx registers	0
used xmm registers	5
used ymm registers	9
used zmm registers	6
nb stack references	1
ADD-SUB / MUL ratio	3.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.17 cycles
front end	8.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.00	11.17	5.67	5.67	0.50	10.83	2.00	0.50	0.50	0.50	2.00	5.67
cycles	11.00	11.17	5.67	5.67	0.50	10.83	2.00	0.50	0.50	0.50	2.00	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.17
Dispatch	11.17
Data deps.	0.00
Overall L1	11.17

Vectorization ratios

INT

all	76%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	75%
load	100%
store	0%
mul	0%
add-sub	66%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	75%
load	100%
store	0%
mul	50%
add-sub	88%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	38%
load	50%
store	6%
mul	6%
add-sub	45%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

INT+FP

all	43%
load	50%
store	6%
mul	28%
add-sub	54%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

3% of peak load performance is reached (6.45 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4046be

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %R12,%ZMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM9,%ZMM12,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM2,%ZMM10,%K1																vect (100.0%)
VPMOVQD %ZMM9,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPADDD %YMM3,%YMM9,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM6,%YMM9,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM4,%YMM10,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VXORPS %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPS (%R8,%YMM10,4),%YMM11{%K2}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM11,%ZMM10	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VPMULLD %YMM9,%YMM0,%YMM9	2	1	1	0	0	0	0	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM9,%YMM8,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM4,%YMM8,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPS (%R9,%YMM8,4),%YMM9{%K2}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM9,%ZMM8	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM10,%ZMM8,%ZMM7{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM7,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM8,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM7,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM7,%XMM8,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM7,%XMM7,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM7,%XMM8,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM7,%XMM7,%XMM7	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM1,%XMM7,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA (%R14,%R15,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM7,(%RAX,%R12,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R15),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4045d0 <main+0x1310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %R15D,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 404610 <main+0x1350>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:27-98
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.50 to 4.00 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 23% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.50 to 2.78 cycles (1.62x speedup).

Details

42% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

11: addition or subtraction
1: multiply

The binary loop is loading 20 bytes (5 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	26
nb uops	27
loop length	131
used x86 registers	8
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	2
nb stack references	3
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.50 cycles
front end	4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.40	3.20	1.00	1.00	0.50	4.00	3.20	0.50	0.50	0.50	3.20	1.00
cycles	3.40	3.20	1.00	1.00	0.50	4.00	3.20	0.50	0.50	0.50	3.20	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.50
Dispatch	4.00
Data deps.	0.00
Overall L1	4.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	60%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

INT+FP

all	42%
load	0%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	28%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	23%
load	12%
store	6%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

2% of peak load performance is reached (4.44 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.89 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.50 to 4.00 cycles (1.13x speedup).

ASM code

In the binary file, the address of the loop is: 4046be

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VEXTRACTF64X4 $0x1,%ZMM7,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM8,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM7,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM7,%XMM8,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM7,%XMM7,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM7,%XMM8,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM7,%XMM7,%XMM7	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM1,%XMM7,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA (%R14,%R15,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM7,(%RAX,%R12,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R15),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4045d0 <main+0x1310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %R15D,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 404610 <main+0x1350>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDI,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV 0x88(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 404610 <main+0x1350>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 404677 <main+0x13b7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:27-98
Module	attention-avx512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 41% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.17 to 5.87 cycles (1.90x speedup).

Details

70% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
88% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
70% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31
- /home/eoseret/llm-attention/attention.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:33
VPMOVQD: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:31

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 2 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

19: addition or subtraction (8 inside FMA instructions)
9: multiply (8 inside FMA instructions)

The binary loop is loading 84 bytes (10 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	55
loop length	229
used x86 registers	10
used mmx registers	0
used xmm registers	5
used ymm registers	9
used zmm registers	6
nb stack references	3
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.00	11.17	6.33	6.33	0.50	10.83	3.60	0.50	0.50	0.50	3.40	6.33
cycles	11.00	11.17	6.33	6.33	0.50	10.83	3.60	0.50	0.50	0.50	3.40	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.17
Dispatch	11.17
Data deps.	0.00
Overall L1	11.17

Vectorization ratios

INT

all	66%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	75%
load	100%
store	0%
mul	0%
add-sub	66%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	70%
load	66%
store	0%
mul	50%
add-sub	88%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

Vector efficiency ratios

INT

all	45%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	38%

all	38%
load	50%
store	6%
mul	6%
add-sub	45%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

INT+FP

all	41%
load	37%
store	6%
mul	28%
add-sub	54%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

3% of peak load performance is reached (7.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4046be

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %R12,%ZMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM9,%ZMM12,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM2,%ZMM10,%K1																vect (100.0%)
VPMOVQD %ZMM9,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPADDD %YMM3,%YMM9,%YMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM6,%YMM9,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM4,%YMM10,%YMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VXORPS %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPS (%R8,%YMM10,4),%YMM11{%K2}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM11,%ZMM10	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VPMULLD %YMM9,%YMM0,%YMM9	2	1	1	0	0	0	0	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM9,%YMM8,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPSUBD %YMM4,%YMM8,%YMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPS (%R9,%YMM8,4),%YMM9{%K2}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM9,%ZMM8	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM10,%ZMM8,%ZMM7{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM7,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM8,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM7,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM7,%XMM8,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM7,%XMM7,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM7,%XMM8,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM7,%XMM7,%XMM7	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VMULSS %XMM1,%XMM7,%XMM7	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
LEA (%R14,%R15,1),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM7,(%RAX,%R12,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R15),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4045d0 <main+0x1310>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %R15D,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 404610 <main+0x1350>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EDI,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV 0x88(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JNE 404610 <main+0x1350>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details