OV - attention-avx512 - Loop 29

0x4045d0 LEA	0x1(%R11),%R14D

0x4045d4 MOV	0x30(%RSP),%RAX

0x4045d9 ADD	%RAX,%R10

0x4045dc CMP	%EDX,%R11D

0x4045df MOV	%R14D,%R11D

0x4045e2 JE	4045b0

0x4045e4 MOV	%R11D,%R14D

0x4045e7 IMUL	%EAX,%R14D

0x4045eb VPBROADCASTD	%R14D,%YMM6

0x4045f1 MOV	%R11D,%R14D

0x4045f4 IMUL	0x50(%RSP),%R14D

0x4045fa XOR	%R15D,%R15D

0x4045fd JMP	4046be

  (30) 0x404610 VPBROADCASTQ	%R12,%ZMM9

  (30) 0x404616 VPSUBQ	%ZMM9,%ZMM12,%ZMM10

  (30) 0x40461c VPCMPNLEUQ	%ZMM2,%ZMM10,%K1

  (30) 0x404623 VPMOVQD	%ZMM9,%YMM9

  (30) 0x404629 VPADDD	%YMM3,%YMM9,%YMM9

  (30) 0x40462d VPADDD	%YMM6,%YMM9,%YMM10

  (30) 0x404631 VPSUBD	%YMM4,%YMM10,%YMM10

  (30) 0x404635 VXORPS	%XMM11,%XMM11,%XMM11

  (30) 0x40463a KMOVQ	%K1,%K2

  (30) 0x40463f VGATHERDPS	(%R8,%YMM10,4),%YMM11{%K2}

  (30) 0x404646 VCVTPS2PD	%YMM11,%ZMM10

  (30) 0x40464c VPMULLD	%YMM9,%YMM0,%YMM9

  (30) 0x404651 VPADDD	%YMM9,%YMM8,%YMM8

  (30) 0x404656 VPSUBD	%YMM4,%YMM8,%YMM8

  (30) 0x40465a VPXOR	%XMM9,%XMM9,%XMM9

  (30) 0x40465f KMOVQ	%K1,%K2

  (30) 0x404664 VGATHERDPS	(%R9,%YMM8,4),%YMM9{%K2}

  (30) 0x40466b VCVTPS2PD	%YMM9,%ZMM8

  (30) 0x404671 VFMADD231PD	%ZMM10,%ZMM8,%ZMM7{%K1}

  (30) 0x404677 VEXTRACTF64X4	$0x1,%ZMM7,%YMM8

  (30) 0x40467e VADDPD	%ZMM8,%ZMM7,%ZMM7

  (30) 0x404684 VEXTRACTF128	$0x1,%YMM7,%XMM8

  (30) 0x40468a VADDPD	%XMM7,%XMM8,%XMM7

  (30) 0x40468e VSHUFPD	$0x1,%XMM7,%XMM7,%XMM8

  (30) 0x404693 VADDSD	%XMM7,%XMM8,%XMM7

  (30) 0x404697 VCVTSD2SS	%XMM7,%XMM7,%XMM7

  (30) 0x40469b VMULSS	%XMM1,%XMM7,%XMM7

  (30) 0x40469f LEA	(%R14,%R15,1),%R12D

  (30) 0x4046a3 MOV	0x58(%RSP),%RAX

  (30) 0x4046a8 VMOVSS	%XMM7,(%RAX,%R12,4)

  (30) 0x4046ae LEA	0x1(%R15),%R12

  (30) 0x4046b2 CMP	%RSI,%R15

  (30) 0x4046b5 MOV	%R12,%R15

  (30) 0x4046b8 JE	4045d0

  (30) 0x4046be VPBROADCASTD	%R15D,%YMM8

  (30) 0x4046c4 VXORPD	%XMM7,%XMM7,%XMM7

  (30) 0x4046c8 XOR	%R12D,%R12D

  (30) 0x4046cb TEST	%RDI,%RDI

  (30) 0x4046ce JE	404610

  (30) 0x4046d4 NOPW	%CS:(%RAX,%RAX,1)

    (31) 0x4046e0 LEA	(%R10,%R12,1),%R13D

    (31) 0x4046e4 VPBROADCASTD	%R13D,%YMM9

    (31) 0x4046ea VPADDD	%YMM5,%YMM9,%YMM9

    (31) 0x4046ee VPXOR	%XMM10,%XMM10,%XMM10

    (31) 0x4046f3 VPCMPEQB	%XMM0,%XMM0,%K1

    (31) 0x4046f9 VGATHERDPS	(%R8,%YMM9,4),%YMM10{%K1}

    (31) 0x404700 VCVTPS2PD	%YMM10,%ZMM9

    (31) 0x404706 VPBROADCASTD	%R12D,%YMM10

    (31) 0x40470c VPADDD	%YMM3,%YMM10,%YMM10

    (31) 0x404710 VPMULLD	%YMM10,%YMM0,%YMM10

    (31) 0x404715 VPADDD	%YMM10,%YMM8,%YMM10

    (31) 0x40471a VPSUBD	%YMM4,%YMM10,%YMM10

    (31) 0x40471e VPXOR	%XMM11,%XMM11,%XMM11

    (31) 0x404723 VPCMPEQB	%XMM0,%XMM0,%K1

    (31) 0x404729 VGATHERDPS	(%R9,%YMM10,4),%YMM11{%K1}

    (31) 0x404730 VCVTPS2PD	%YMM11,%ZMM10

    (31) 0x404736 VFMADD231PD	%ZMM10,%ZMM9,%ZMM7

    (31) 0x40473c ADD	$0x8,%R12

    (31) 0x404740 CMP	%RDI,%R12

    (31) 0x404743 JB	4046e0

  (30) 0x404745 MOV	%RDI,%R12

  (30) 0x404748 CMP	%EDI,0x38(%RSP)

  (30) 0x40474c MOV	0x88(%RSP),%R13

  (30) 0x404754 JNE	404610

  (30) 0x40475a JMP	404677

/home/eoseret/llm-attention/attention.cpp: 26 - 98

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P1,
Function	main
Source	attention.cpp:26-26,attention.cpp:31-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.60
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.60
CQA cycles if fully vectorized	0.17
Front-end cycles	2.17
P0 cycles	1.30
P1 cycles	2.60
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.00
P5 cycles	1.20
P6 cycles	1.30
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.20
P11 cycles	0.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.62
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.81
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	2.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P1,
Function	main
Source	attention.cpp:26-26,attention.cpp:31-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.60
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.60
CQA cycles if fully vectorized	0.17
Front-end cycles	2.17
P0 cycles	1.30
P1 cycles	2.60
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.00
P5 cycles	1.20
P6 cycles	1.30
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.20
P11 cycles	0.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.62
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.81
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-98
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,31-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.60 to 1.00 cycles (2.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes.

General properties

nb instructions	13
nb uops	13
loop length	50
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.30	2.00	0.67	0.67	0.00	1.20	1.30	0.00	0.00	0.00	1.20	0.67
cycles	1.30	2.60	0.67	0.67	0.00	1.20	1.30	0.00	0.00	0.00	1.20	0.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.17
Dispatch	2.60
Data deps.	0.00
Overall L1	2.60

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.60 cycles. At this rate:

2% of peak load performance is reached (4.62 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4045e4

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%R11),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
CMP %EDX,%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %R14D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4045b0 <main+0x12f0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R11D,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %EAX,%R14D	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %R14D,%YMM6	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
MOV %R11D,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL 0x50(%RSP),%R14D	1	0	1	0.33	0.33	0	0	0	0.33	3	1	scal (6.3%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4046be <main+0x13fe>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:26-98
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,31-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.60 to 1.00 cycles (2.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes.

General properties

nb instructions	13
nb uops	13
loop length	50
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.30	2.00	0.67	0.67	0.00	1.20	1.30	0.00	0.00	0.00	1.20	0.67
cycles	1.30	2.60	0.67	0.67	0.00	1.20	1.30	0.00	0.00	0.00	1.20	0.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.17
Dispatch	2.60
Data deps.	0.00
Overall L1	2.60

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.60 cycles. At this rate:

2% of peak load performance is reached (4.62 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4045e4

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x1(%R11),%R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
CMP %EDX,%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %R14D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4045b0 <main+0x12f0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV %R11D,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %EAX,%R14D	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %R14D,%YMM6	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
MOV %R11D,%R14D	1	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL 0x50(%RSP),%R14D	1	0	1	0.33	0.33	0	0	0	0.33	3	1	scal (6.3%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 4046be <main+0x13fe>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code