OV - attention-avx512 - Loop 23

	Loop Id: 23	Module: attention-avx512	Source: attention.cpp:43-284 [...]	Coverage: 0.58%

0x4048b0 MOV	0xa8(%RSP),%RAX

0x4048b8 VMOVSS	%XMM19,(%RAX,%RDI,4)

0x4048bf MOV	0xb0(%RSP),%RAX

0x4048c7 MOV	0xd0(%RSP),%RDX

0x4048cf ADD	%RAX,%RDX

0x4048d2 INC	%R14

0x4048d5 ADD	%RAX,%R12

0x4048d8 ADD	%RAX,%R15

0x4048db CMP	0xf0(%RSP),%RDI

0x4048e3 MOV	%RSI,%RDI

0x4048e6 JE	404870

0x4048e8 LEA	0x1(%RDI),%RSI

0x4048ec VMOVAPS	%XMM21,%XMM16

0x4048f2 CMP	$0x8,%RSI

0x4048f6 JB	404944

0x4048f8 MOV	%R14,%RAX

0x4048fb SHR	$0x3,%RAX

0x4048ff MOV	%RDX,%RCX

0x404902 VMOVAPS	%XMM21,%XMM16

0x404908 NOPL	(%RAX,%RAX,1)

  (27) 0x404910 VMAXSS	-0x1c(%RCX),%XMM16,%XMM0

  (27) 0x404917 VMAXSS	-0x18(%RCX),%XMM0,%XMM0

  (27) 0x40491c VMAXSS	-0x14(%RCX),%XMM0,%XMM0

  (27) 0x404921 VMAXSS	-0x10(%RCX),%XMM0,%XMM0

  (27) 0x404926 VMAXSS	-0xc(%RCX),%XMM0,%XMM0

  (27) 0x40492b VMAXSS	-0x8(%RCX),%XMM0,%XMM0

  (27) 0x404930 VMAXSS	-0x4(%RCX),%XMM0,%XMM0

  (27) 0x404935 VMAXSS	(%RCX),%XMM0,%XMM16

  (27) 0x40493b ADD	$0x20,%RCX

  (27) 0x40493f DEC	%RAX

  (27) 0x404942 JNE	404910

0x404944 MOV	%RSI,%RAX

0x404947 AND	$-0x8,%RAX

0x40494b CMP	%RSI,%RAX

0x40494e MOV	0x40(%RSP),%RCX

0x404953 JE	40496f

0x404955 NOPW	%CS:(%RAX,%RAX,1)

  (26) 0x404960 VMAXSS	(%R12,%RAX,4),%XMM16,%XMM16

  (26) 0x404967 INC	%RAX

  (26) 0x40496a CMP	%RAX,%R14

  (26) 0x40496d JNE	404960

0x40496f MOV	%RDX,0xd0(%RSP)

0x404977 MOV	%RSI,%R13

0x40497a AND	$-0x10,%R13

0x40497e VPBROADCASTQ	%R13,%ZMM17

0x404984 MOV	%RDI,0x28(%RSP)

0x404989 MOV	%RSI,0x180(%RSP)

0x404991 MOV	%R13,0x140(%RSP)

0x404999 JE	404a20

0x40499f VPBROADCASTQ	%RSI,%ZMM19

0x4049a5 LEA	-0x1(%R13),%RSI

0x4049a9 IMUL	%RDI,%RCX

0x4049ad MOV	%RCX,0x80(%RSP)

0x4049b5 VBROADCASTSS	%XMM16,%ZMM20

0x4049bb VXORPS	%XMM18,%XMM18,%XMM18

0x4049c1 XOR	%EDI,%EDI

0x4049c3 MOV	$0x405780,%R13

0x4049ca NOPW	(%RAX,%RAX,1)

  (25) 0x4049d0 VMOVUPS	(%R12,%RDI,4),%ZMM0

  (25) 0x4049d7 VSUBPS	%ZMM20,%ZMM0,%ZMM0

  (25) 0x4049dd CALL	%R13

  (25) 0x4049e0 VADDPS	%ZMM18,%ZMM0,%ZMM18

  (25) 0x4049e6 ADD	$0x10,%RDI

  (25) 0x4049ea CMP	%RSI,%RDI

  (25) 0x4049ed JLE	4049d0

0x4049ef VPCMPEQQ	%ZMM17,%ZMM19,%K0

0x4049f5 KMOVD	%K0,%ECX

0x4049f9 MOV	0x140(%RSP),%R13

0x404a01 MOV	%R13,%RAX

0x404a04 TEST	$0x1,%CL

0x404a07 MOV	0x28(%RSP),%RDI

0x404a0c MOV	0x180(%RSP),%RSI

0x404a14 MOV	0x80(%RSP),%RCX

0x404a1c JE	404a38

0x404a1e JMP	404a8f

0x404a20 VPBROADCASTQ	%RSI,%ZMM19

0x404a26 IMUL	%RDI,%RCX

0x404a2a VBROADCASTSS	%XMM16,%ZMM20

0x404a30 VXORPS	%XMM18,%XMM18,%XMM18

0x404a36 XOR	%EAX,%EAX

0x404a38 VPBROADCASTQ	%RAX,%ZMM0

0x404a3e VPSUBQ	%ZMM0,%ZMM19,%ZMM1

0x404a44 VPSUBQ	%ZMM0,%ZMM19,%ZMM0

0x404a4a VPCMPNLEUQ	%ZMM22,%ZMM0,%K0

0x404a51 VPCMPNLEUQ	%ZMM23,%ZMM1,%K1

0x404a58 KUNPCKBW	%K0,%K1,%K1

0x404a5c KMOVW	%K1,0x80(%RSP)

0x404a65 ADD	%RAX,%RCX

0x404a68 MOV	0x58(%RSP),%RAX

0x404a6d VMOVUPS	(%RAX,%RCX,4),%ZMM0{%K1}{z}

0x404a74 VSUBPS	%ZMM20,%ZMM0,%ZMM1

0x404a7a CALL	405820 <__svml_expf16_mask_z0>

0x404a80 KMOVW	0x80(%RSP),%K1

0x404a89 VADDPS	%ZMM0,%ZMM18,%ZMM18{%K1}

0x404a8f VEXTRACTF64X4	$0x1,%ZMM18,%YMM0

0x404a96 VADDPS	%ZMM0,%ZMM18,%ZMM0

0x404a9c VEXTRACTF128	$0x1,%YMM0,%XMM1

0x404aa2 VADDPS	%XMM1,%XMM0,%XMM0

0x404aa6 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x404aab VADDPS	%XMM1,%XMM0,%XMM0

0x404aaf VMOVSHDUP	%XMM0,%XMM1

0x404ab3 VADDSS	%XMM1,%XMM0,%XMM19

0x404ab9 VDIVSS	%XMM19,%XMM24,%XMM1

0x404abf TEST	%R13,%R13

0x404ac2 JE	404b80

0x404ac8 LEA	-0x1(%R13),%RSI

0x404acc MOV	0x40(%RSP),%RAX

0x404ad1 IMUL	%RDI,%RAX

0x404ad5 MOV	%RAX,0x80(%RSP)

0x404add VBROADCASTSS	%XMM16,%ZMM18

0x404ae3 VBROADCASTSS	%XMM1,%ZMM16

0x404ae9 XOR	%R13D,%R13D

0x404aec MOV	$0x405780,%RDI

0x404af3 NOPW	%CS:(%RAX,%RAX,1)

  (24) 0x404b00 VMOVUPS	(%R12,%R13,4),%ZMM0

  (24) 0x404b07 VSUBPS	%ZMM18,%ZMM0,%ZMM0

  (24) 0x404b0d CALL	%RDI

  (24) 0x404b0f VMULPS	%ZMM16,%ZMM0,%ZMM0

  (24) 0x404b15 VMOVUPS	%ZMM0,(%R15,%R13,4)

  (24) 0x404b1c ADD	$0x10,%R13

  (24) 0x404b20 CMP	%RSI,%R13

  (24) 0x404b23 JLE	404b00

0x404b25 MOV	0x180(%RSP),%RSI

0x404b2d VPBROADCASTQ	%RSI,%ZMM0

0x404b33 VPCMPEQQ	%ZMM17,%ZMM0,%K0

0x404b39 KMOVD	%K0,%EAX

0x404b3d TEST	$0x1,%AL

0x404b3f MOV	0x28(%RSP),%RDI

0x404b44 MOV	0x140(%RSP),%RAX

0x404b4c MOV	0x80(%RSP),%R13

0x404b54 JE	404b9d

0x404b56 CMP	0x100(%RSP),%RSI

0x404b5e MOV	0x88(%RSP),%R13

0x404b66 JAE	4048b0

0x404b6c JMP	404c11

0x404b80 VPBROADCASTQ	%RSI,%ZMM0

0x404b86 MOV	0x40(%RSP),%R13

0x404b8b IMUL	%RDI,%R13

0x404b8f VBROADCASTSS	%XMM16,%ZMM18

0x404b95 VBROADCASTSS	%XMM1,%ZMM16

0x404b9b XOR	%EAX,%EAX

0x404b9d VPBROADCASTQ	%RAX,%ZMM1

0x404ba3 VPSUBQ	%ZMM1,%ZMM0,%ZMM2

0x404ba9 VPSUBQ	%ZMM1,%ZMM0,%ZMM0

0x404baf VPCMPNLEUQ	%ZMM22,%ZMM0,%K0

0x404bb6 VPCMPNLEUQ	%ZMM23,%ZMM2,%K1

0x404bbd KUNPCKBW	%K0,%K1,%K1

0x404bc1 KMOVW	%K1,0x140(%RSP)

0x404bca ADD	%RAX,%R13

0x404bcd MOV	0x58(%RSP),%RAX

0x404bd2 VMOVUPS	(%RAX,%R13,4),%ZMM0{%K1}{z}

0x404bd9 VSUBPS	%ZMM18,%ZMM0,%ZMM1

0x404bdf CALL	405820 <__svml_expf16_mask_z0>

0x404be5 VMULPS	%ZMM16,%ZMM0,%ZMM0

0x404beb KMOVW	0x140(%RSP),%K1

0x404bf4 VMOVUPS	%ZMM0,(%RBX,%R13,4){%K1}

0x404bfb CMP	0x100(%RSP),%RSI

0x404c03 MOV	0x88(%RSP),%R13

0x404c0b JAE	4048b0

0x404c11 MOV	0x130(%RSP),%RDI

0x404c19 IMUL	0x28(%RSP),%RDI

0x404c1f ADD	$0x4,%RDI

0x404c23 MOV	0x138(%RSP),%RDX

0x404c2b SUB	0x28(%RSP),%RDX

0x404c30 MOV	$0x3fffffffc,%RAX

0x404c3a AND	%RAX,%RDI

0x404c3d ADD	%RBX,%RDI

0x404c40 SAL	$0x2,%RDX

0x404c44 AND	%RAX,%RDX

0x404c47 ADD	$0x4,%RDX

0x404c4b XOR	%ESI,%ESI

0x404c4d VMOVSS	%XMM19,0x140(%RSP)

0x404c55 VZEROUPPER

0x404c58 CALL	406790 <_intel_fast_memset>

0x404c5d VMOVSS	0x140(%RSP),%XMM19

0x404c65 MOV	0x180(%RSP),%RSI

0x404c6d MOV	0x28(%RSP),%RDI

0x404c72 VMOVSS	0x73ec(%RIP),%XMM24

0x404c7c VPMOVSXBQ	0x760a(%RIP),%ZMM23

0x404c86 VPMOVSXBQ	0x75f8(%RIP),%ZMM22

0x404c90 VMOVSS	0x73ca(%RIP),%XMM21

0x404c9a JMP	4048b0

/home/eoseret/llm-attention/attention.cpp: 43 - 284

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

[...]

98:    if (argc < 4) {

[...]

284:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.39
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-61,attention.cpp:98-98,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	26.33
CQA cycles if no scalar integer	19.00
CQA cycles if FP arith vectorized	25.75
CQA cycles if fully vectorized	19.39
Front-end cycles	26.33
P0 cycles	13.70
P1 cycles	13.80
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	7.00
P5 cycles	23.00
P6 cycles	13.70
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	13.80
P11 cycles	12.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	152.00
Nb uops	158.00
Nb loads	36.00
Nb stores	11.00
Nb stack references	14.00
FLOP/cycle	3.42
Nb FLOP add-sub	73.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.99
Bytes prefetched	0.00
Bytes loaded	376.00
Bytes stored	124.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	44.29
Vectorization ratio load	30.77
Vectorization ratio store	11.11
Vectorization ratio mul	100.00
Vectorization ratio add_sub	71.43
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	35.89
Vector-efficiency ratio load	24.52
Vector-efficiency ratio store	20.83
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	63.84
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	29.82

Metric	Value
CQA speedup if no scalar integer	1.39
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-61,attention.cpp:98-98,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	26.33
CQA cycles if no scalar integer	19.00
CQA cycles if FP arith vectorized	25.75
CQA cycles if fully vectorized	19.39
Front-end cycles	26.33
P0 cycles	13.70
P1 cycles	13.80
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	7.00
P5 cycles	23.00
P6 cycles	13.70
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	13.80
P11 cycles	12.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	152.00
Nb uops	158.00
Nb loads	36.00
Nb stores	11.00
Nb stack references	14.00
FLOP/cycle	3.42
Nb FLOP add-sub	73.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.99
Bytes prefetched	0.00
Bytes loaded	376.00
Bytes stored	124.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	44.29
Vectorization ratio load	30.77
Vectorization ratio store	11.11
Vectorization ratio mul	100.00
Vectorization ratio add_sub	71.43
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	35.89
Vector-efficiency ratio load	24.52
Vector-efficiency ratio store	20.83
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	63.84
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	29.82

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,98,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52-61,98,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 72 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.33 to 19.00 cycles (1.39x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 35% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 26.33 to 19.39 cycles (1.36x speedup).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

30% of SSE/AVX loads are used in vector version.
11% of SSE/AVX stores are used in vector version.
71% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_expf16_mask_z0: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
VPMOVSXBQ: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
- /home/eoseret/llm-attention/attention.cpp:59
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
- /home/eoseret/llm-attention/attention.cpp:59

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 5 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

73: addition or subtraction
16: multiply
1: divide

The binary loop is loading 376 bytes (94 single precision FP elements). The binary loop is storing 124 bytes (31 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	152
nb uops	158
loop length	857
used x86 registers	11
used mmx registers	0
used xmm registers	7
used ymm registers	1
used zmm registers	10
nb stack references	14
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.33 cycles
front end	26.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.70	13.80	12.00	12.00	7.00	23.00	13.70	7.00	7.00	7.00	13.80	12.00
cycles	13.70	13.80	12.00	12.00	7.00	23.00	13.70	7.00	7.00	7.00	13.80	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	26.33
Dispatch	23.00
DIV/SQRT	3.00
Overall L1	26.33

Vectorization ratios

INT

all	33%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	58%
load	40%
store	33%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	57%

INT+FP

all	44%
load	30%
store	11%
mul	100%
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	42%

Vector efficiency ratios

INT

all	35%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	36%
load	43%
store	37%
mul	100%
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	17%

INT+FP

all	35%
load	24%
store	20%
mul	100%
add-sub	63%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	29%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 26.33 cycles. At this rate:

7% of peak load performance is reached (14.28 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.71 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 26.33 to 23.00 cycles (1.14x speedup).

ASM code

In the binary file, the address of the loop is: 4048e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xa8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM19,(%RAX,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0xb0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RAX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP 0xf0(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 404870 <main+0x15b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RDI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMP $0x8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404944 <main+0x1684>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x40(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 40496f <main+0x16af>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %R13,%ZMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 404a20 <main+0x1760>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTQ %RSI,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA -0x1(%R13),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x405780,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %ZMM17,%ZMM19,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x140(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x180(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x80(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 404a38 <main+0x1778>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 404a8f <main+0x17cf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VPBROADCASTQ %RSI,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM0,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM1,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RCX,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM20,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 405820 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
KMOVW 0x80(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %ZMM0,%ZMM18,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPS %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VDIVSS %XMM19,%XMM24,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %R13,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 404b80 <main+0x18c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R13),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x405780,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x180(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %RSI,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %ZMM17,%ZMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x140(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 404b9d <main+0x18dd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0x100(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 4048b0 <main+0x15f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 404c11 <main+0x1951>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPBROADCASTQ %RSI,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x40(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM2,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%R13,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM18,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 405820 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMULPS %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVW 0x140(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %ZMM0,(%RBX,%R13,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP 0x100(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 4048b0 <main+0x15f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x130(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x28(%RSP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x138(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB 0x28(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV $0x3fffffffc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSS %XMM19,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406790 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x140(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x180(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x73ec(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBQ 0x760a(%RIP),%ZMM23	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBQ 0x75f8(%RIP),%ZMM22	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VMOVSS 0x73ca(%RIP),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 4048b0 <main+0x15f0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,98,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52-61,98,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

30% of SSE/AVX loads are used in vector version.
11% of SSE/AVX stores are used in vector version.
71% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

__svml_expf16_mask_z0: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53
- /home/eoseret/llm-attention/attention.cpp:56
VPMOVSXBQ: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
- /home/eoseret/llm-attention/attention.cpp:59
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VPMOVSXBQ: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59
- /home/eoseret/llm-attention/attention.cpp:59

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

73: addition or subtraction
16: multiply
1: divide

The binary loop is loading 376 bytes (94 single precision FP elements). The binary loop is storing 124 bytes (31 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	152
nb uops	158
loop length	857
used x86 registers	11
used mmx registers	0
used xmm registers	7
used ymm registers	1
used zmm registers	10
nb stack references	14
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.33 cycles
front end	26.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.70	13.80	12.00	12.00	7.00	23.00	13.70	7.00	7.00	7.00	13.80	12.00
cycles	13.70	13.80	12.00	12.00	7.00	23.00	13.70	7.00	7.00	7.00	13.80	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	26.33
Dispatch	23.00
DIV/SQRT	3.00
Overall L1	26.33

Vectorization ratios

INT

all	33%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	58%
load	40%
store	33%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	57%

INT+FP

all	44%
load	30%
store	11%
mul	100%
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	42%

Vector efficiency ratios

INT

all	35%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	36%
load	43%
store	37%
mul	100%
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	17%

INT+FP

all	35%
load	24%
store	20%
mul	100%
add-sub	63%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	29%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 26.33 cycles. At this rate:

7% of peak load performance is reached (14.28 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.71 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4048e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xa8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM19,(%RAX,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0xb0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RAX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP 0xf0(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 404870 <main+0x15b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RDI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMP $0x8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404944 <main+0x1684>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM21,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x40(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 40496f <main+0x16af>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %R13,%ZMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 404a20 <main+0x1760>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTQ %RSI,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
LEA -0x1(%R13),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x405780,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %ZMM17,%ZMM19,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x140(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x180(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x80(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 404a38 <main+0x1778>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 404a8f <main+0x17cf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VPBROADCASTQ %RSI,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM0,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM1,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RCX,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM20,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 405820 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
KMOVW 0x80(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %ZMM0,%ZMM18,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPS %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VDIVSS %XMM19,%XMM24,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %R13,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 404b80 <main+0x18c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R13),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x405780,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x180(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %RSI,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %ZMM17,%ZMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x140(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 404b9d <main+0x18dd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0x100(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 4048b0 <main+0x15f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 404c11 <main+0x1951>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPBROADCASTQ %RSI,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x40(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ %ZMM22,%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ %ZMM23,%ZMM2,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%R13,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM18,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 405820 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMULPS %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVW 0x140(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %ZMM0,(%RBX,%R13,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP 0x100(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JAE 4048b0 <main+0x15f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x130(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x28(%RSP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x138(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB 0x28(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV $0x3fffffffc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSS %XMM19,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406790 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x140(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x180(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x73ec(%RIP),%XMM24	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPMOVSXBQ 0x760a(%RIP),%ZMM23	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBQ 0x75f8(%RIP),%ZMM22	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VMOVSS 0x73ca(%RIP),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 4048b0 <main+0x15f0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code