OV - attention-gnr-512 - Loop 75

0x4096c7 VMOVDQA	%YMM0,(%R11)    [2]

0x4096cc VMOVDQA	%YMM0,0x20(%R11)    [2]

0x4096d2 VMOVDQA	%YMM0,0x40(%R11)    [2]

0x4096d8 VMOVDQA	%YMM0,0x60(%R11)    [2]

0x4096de ADD	$0x100,%R11

0x4096e5 SUB	$0x100,%RDX

0x4096ec VMOVDQA	%YMM0,-0x80(%R11)    [1]

0x4096f2 VMOVDQA	%YMM0,-0x60(%R11)    [1]

0x4096f8 VMOVDQA	%YMM0,-0x40(%R11)    [1]

0x4096fe VMOVDQA	%YMM0,-0x20(%R11)    [1]

0x409704 CMP	$0x100,%RDX

0x40970b JGE	4096c7

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
○40.00	main	stl_algobase.h:924	attention-gnr-512
○20.00	main	stl_algobase.h:924	attention-gnr-512
○20.00	main	stl_algobase.h:924	attention-gnr-512
○20.00	main	stl_algobase.h:924	attention-gnr-512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.18
Bottlenecks	P4, P7, P8, P9,
Function	__intel_avx_rep_memset
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	2.00
Front-end cycles	1.83
P0 cycles	0.70
P1 cycles	0.60
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	4.00
P5 cycles	0.60
P6 cycles	0.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.60
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	11.00
Nb loads	0.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.18
Bottlenecks	P4, P7, P8, P9,
Function	__intel_avx_rep_memset
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	2.00
Front-end cycles	1.83
P0 cycles	0.70
P1 cycles	0.60
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	4.00
P5 cycles	0.60
P6 cycles	0.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.60
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	11.00
Nb loads	0.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__intel_avx_rep_memset
Source file and lines
Module	attention-gnr-512

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

General properties

nb instructions	12
nb uops	11
loop length	70
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.83 cycles
front end	1.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.70	0.60	0.00	0.00	4.00	0.60	0.50	4.00	4.00	4.00	0.60	0.00
cycles	0.70	0.60	0.00	0.00	4.00	0.60	0.50	4.00	4.00	4.00	0.60	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.83
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

50% of peak store performance is reached (64.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4096c7

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VMOVDQA %YMM0,(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,0x20(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,0x40(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,0x60(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
ADD $0x100,%R11	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
SUB $0x100,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
VMOVDQA %YMM0,-0x80(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,-0x60(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,-0x40(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,-0x20(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
CMP $0x100,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JGE 4096c7 <__intel_avx_rep_memset+0xa7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	__intel_avx_rep_memset
Source file and lines
Module	attention-gnr-512

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

General properties

nb instructions	12
nb uops	11
loop length	70
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.83 cycles
front end	1.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.70	0.60	0.00	0.00	4.00	0.60	0.50	4.00	4.00	4.00	0.60	0.00
cycles	0.70	0.60	0.00	0.00	4.00	0.60	0.50	4.00	4.00	4.00	0.60	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.83
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

50% of peak store performance is reached (64.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4096c7

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VMOVDQA %YMM0,(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,0x20(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,0x40(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,0x60(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
ADD $0x100,%R11	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
SUB $0x100,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
VMOVDQA %YMM0,-0x80(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,-0x60(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,-0x40(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
VMOVDQA %YMM0,-0x20(%R11)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (50.0%)
CMP $0x100,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JGE 4096c7 <__intel_avx_rep_memset+0xa7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code